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M433 BSP V3.01.000
The Board Support Package for M433
|
| #define ACMP_CTL_ACMPEN_Msk (0x1ul << ACMP_CTL_ACMPEN_Pos) |
ACMP_T::CTL: ACMPEN Mask
Definition at line 161 of file acmp_reg.h.
| #define ACMP_CTL_ACMPEN_Pos (0) |
@addtogroup ACMP_CONST ACMP Bit Field Definition Constant Definitions for ACMP Controller
ACMP_T::CTL: ACMPEN Position
Definition at line 160 of file acmp_reg.h.
| #define ACMP_CTL_ACMPIE_Msk (0x1ul << ACMP_CTL_ACMPIE_Pos) |
ACMP_T::CTL: ACMPIE Mask
Definition at line 164 of file acmp_reg.h.
| #define ACMP_CTL_ACMPIE_Pos (1) |
ACMP_T::CTL: ACMPIE Position
Definition at line 163 of file acmp_reg.h.
| #define ACMP_CTL_ACMPOINV_Msk (0x1ul << ACMP_CTL_ACMPOINV_Pos) |
ACMP_T::CTL: ACMPOINV Mask
Definition at line 167 of file acmp_reg.h.
| #define ACMP_CTL_ACMPOINV_Pos (3) |
ACMP_T::CTL: ACMPOINV Position
Definition at line 166 of file acmp_reg.h.
| #define ACMP_CTL_FILTSEL_Msk (0x7ul << ACMP_CTL_FILTSEL_Pos) |
ACMP_T::CTL: FILTSEL Mask
Definition at line 182 of file acmp_reg.h.
| #define ACMP_CTL_FILTSEL_Pos (13) |
ACMP_T::CTL: FILTSEL Position
Definition at line 181 of file acmp_reg.h.
| #define ACMP_CTL_HYSSEL_Msk (0x3ul << ACMP_CTL_HYSSEL_Pos) |
ACMP_T::CTL: HYSSEL Mask
Definition at line 194 of file acmp_reg.h.
| #define ACMP_CTL_HYSSEL_Pos (24) |
ACMP_T::CTL: HYSSEL Position
Definition at line 193 of file acmp_reg.h.
| #define ACMP_CTL_INTPOL_Msk (0x3ul << ACMP_CTL_INTPOL_Pos) |
ACMP_T::CTL: INTPOL Mask
Definition at line 176 of file acmp_reg.h.
| #define ACMP_CTL_INTPOL_Pos (8) |
ACMP_T::CTL: INTPOL Position
Definition at line 175 of file acmp_reg.h.
| #define ACMP_CTL_MODESEL_Msk (0x3ul << ACMP_CTL_MODESEL_Pos) |
ACMP_T::CTL: MODESEL Mask
Definition at line 197 of file acmp_reg.h.
| #define ACMP_CTL_MODESEL_Pos (28) |
ACMP_T::CTL: MODESEL Position
Definition at line 196 of file acmp_reg.h.
| #define ACMP_CTL_NEGSEL_Msk (0x3ul << ACMP_CTL_NEGSEL_Pos) |
ACMP_T::CTL: NEGSEL Mask
Definition at line 170 of file acmp_reg.h.
| #define ACMP_CTL_NEGSEL_Pos (4) |
ACMP_T::CTL: NEGSEL Position
Definition at line 169 of file acmp_reg.h.
| #define ACMP_CTL_OUTSEL_Msk (0x1ul << ACMP_CTL_OUTSEL_Pos) |
ACMP_T::CTL: OUTSEL Mask
Definition at line 179 of file acmp_reg.h.
| #define ACMP_CTL_OUTSEL_Pos (12) |
ACMP_T::CTL: OUTSEL Position
Definition at line 178 of file acmp_reg.h.
| #define ACMP_CTL_POSSEL_Msk (0x3ul << ACMP_CTL_POSSEL_Pos) |
ACMP_T::CTL: POSSEL Mask
Definition at line 173 of file acmp_reg.h.
| #define ACMP_CTL_POSSEL_Pos (6) |
ACMP_T::CTL: POSSEL Position
Definition at line 172 of file acmp_reg.h.
| #define ACMP_CTL_WCMPSEL_Msk (0x1ul << ACMP_CTL_WCMPSEL_Pos) |
ACMP_T::CTL: WCMPSEL Mask
Definition at line 191 of file acmp_reg.h.
| #define ACMP_CTL_WCMPSEL_Pos (18) |
ACMP_T::CTL: WCMPSEL Position
Definition at line 190 of file acmp_reg.h.
| #define ACMP_CTL_WKEN_Msk (0x1ul << ACMP_CTL_WKEN_Pos) |
ACMP_T::CTL: WKEN Mask
Definition at line 185 of file acmp_reg.h.
| #define ACMP_CTL_WKEN_Pos (16) |
ACMP_T::CTL: WKEN Position
Definition at line 184 of file acmp_reg.h.
| #define ACMP_CTL_WLATEN_Msk (0x1ul << ACMP_CTL_WLATEN_Pos) |
ACMP_T::CTL: WLATEN Mask
Definition at line 188 of file acmp_reg.h.
| #define ACMP_CTL_WLATEN_Pos (17) |
ACMP_T::CTL: WLATEN Position
Definition at line 187 of file acmp_reg.h.
| #define ACMP_STATUS_ACMPIF0_Msk (0x1ul << ACMP_STATUS_ACMPIF0_Pos) |
ACMP_T::STATUS: ACMPIF0 Mask
Definition at line 200 of file acmp_reg.h.
| #define ACMP_STATUS_ACMPIF0_Pos (0) |
ACMP_T::STATUS: ACMPIF0 Position
Definition at line 199 of file acmp_reg.h.
| #define ACMP_STATUS_ACMPIF1_Msk (0x1ul << ACMP_STATUS_ACMPIF1_Pos) |
ACMP_T::STATUS: ACMPIF1 Mask
Definition at line 203 of file acmp_reg.h.
| #define ACMP_STATUS_ACMPIF1_Pos (1) |
ACMP_T::STATUS: ACMPIF1 Position
Definition at line 202 of file acmp_reg.h.
| #define ACMP_STATUS_ACMPO0_Msk (0x1ul << ACMP_STATUS_ACMPO0_Pos) |
ACMP_T::STATUS: ACMPO0 Mask
Definition at line 206 of file acmp_reg.h.
| #define ACMP_STATUS_ACMPO0_Pos (4) |
ACMP_T::STATUS: ACMPO0 Position
Definition at line 205 of file acmp_reg.h.
| #define ACMP_STATUS_ACMPO1_Msk (0x1ul << ACMP_STATUS_ACMPO1_Pos) |
ACMP_T::STATUS: ACMPO1 Mask
Definition at line 209 of file acmp_reg.h.
| #define ACMP_STATUS_ACMPO1_Pos (5) |
ACMP_T::STATUS: ACMPO1 Position
Definition at line 208 of file acmp_reg.h.
| #define ACMP_STATUS_ACMPS0_Msk (0x1ul << ACMP_STATUS_ACMPS0_Pos) |
ACMP_T::STATUS: ACMPS0 Mask
Definition at line 218 of file acmp_reg.h.
| #define ACMP_STATUS_ACMPS0_Pos (12) |
ACMP_T::STATUS: ACMPS0 Position
Definition at line 217 of file acmp_reg.h.
| #define ACMP_STATUS_ACMPS1_Msk (0x1ul << ACMP_STATUS_ACMPS1_Pos) |
ACMP_T::STATUS: ACMPS1 Mask
Definition at line 221 of file acmp_reg.h.
| #define ACMP_STATUS_ACMPS1_Pos (13) |
ACMP_T::STATUS: ACMPS1 Position
Definition at line 220 of file acmp_reg.h.
| #define ACMP_STATUS_ACMPWO_Msk (0x1ul << ACMP_STATUS_ACMPWO_Pos) |
ACMP_T::STATUS: ACMPWO Mask
Definition at line 224 of file acmp_reg.h.
| #define ACMP_STATUS_ACMPWO_Pos (16) |
ACMP_T::STATUS: ACMPWO Position
Definition at line 223 of file acmp_reg.h.
| #define ACMP_STATUS_WKIF0_Msk (0x1ul << ACMP_STATUS_WKIF0_Pos) |
ACMP_T::STATUS: WKIF0 Mask
Definition at line 212 of file acmp_reg.h.
| #define ACMP_STATUS_WKIF0_Pos (8) |
ACMP_T::STATUS: WKIF0 Position
Definition at line 211 of file acmp_reg.h.
| #define ACMP_STATUS_WKIF1_Msk (0x1ul << ACMP_STATUS_WKIF1_Pos) |
ACMP_T::STATUS: WKIF1 Mask
Definition at line 215 of file acmp_reg.h.
| #define ACMP_STATUS_WKIF1_Pos (9) |
ACMP_T::STATUS: WKIF1 Position
Definition at line 214 of file acmp_reg.h.
| #define ACMP_VREF_CRVCTL_Msk (0xful << ACMP_VREF_CRVCTL_Pos) |
ACMP_T::VREF: CRVCTL Mask
Definition at line 227 of file acmp_reg.h.
| #define ACMP_VREF_CRVCTL_Pos (0) |
ACMP_T::VREF: CRVCTL Position
Definition at line 226 of file acmp_reg.h.
| #define ACMP_VREF_CRVSSEL_Msk (0x1ul << ACMP_VREF_CRVSSEL_Pos) |
ACMP_T::VREF: CRVSSEL Mask
Definition at line 230 of file acmp_reg.h.
| #define ACMP_VREF_CRVSSEL_Pos (6) |
ACMP_T::VREF: CRVSSEL Position
Definition at line 229 of file acmp_reg.h.
| #define BPWM_CAPCTL_CAPEN0_Msk (0x1ul << BPWM_CAPCTL_CAPEN0_Pos) |
BPWM_T::CAPCTL: CAPEN0 Mask
Definition at line 1597 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPEN0_Pos (0) |
BPWM_T::CAPCTL: CAPEN0 Position
Definition at line 1596 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPEN1_Msk (0x1ul << BPWM_CAPCTL_CAPEN1_Pos) |
BPWM_T::CAPCTL: CAPEN1 Mask
Definition at line 1600 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPEN1_Pos (1) |
BPWM_T::CAPCTL: CAPEN1 Position
Definition at line 1599 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPEN2_Msk (0x1ul << BPWM_CAPCTL_CAPEN2_Pos) |
BPWM_T::CAPCTL: CAPEN2 Mask
Definition at line 1603 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPEN2_Pos (2) |
BPWM_T::CAPCTL: CAPEN2 Position
Definition at line 1602 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPEN3_Msk (0x1ul << BPWM_CAPCTL_CAPEN3_Pos) |
BPWM_T::CAPCTL: CAPEN3 Mask
Definition at line 1606 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPEN3_Pos (3) |
BPWM_T::CAPCTL: CAPEN3 Position
Definition at line 1605 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPEN4_Msk (0x1ul << BPWM_CAPCTL_CAPEN4_Pos) |
BPWM_T::CAPCTL: CAPEN4 Mask
Definition at line 1609 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPEN4_Pos (4) |
BPWM_T::CAPCTL: CAPEN4 Position
Definition at line 1608 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPEN5_Msk (0x1ul << BPWM_CAPCTL_CAPEN5_Pos) |
BPWM_T::CAPCTL: CAPEN5 Mask
Definition at line 1612 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPEN5_Pos (5) |
BPWM_T::CAPCTL: CAPEN5 Position
Definition at line 1611 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPENn_Msk (0x3ful << BPWM_CAPCTL_CAPENn_Pos) |
BPWM_T::CAPCTL: CAPENn Mask
Definition at line 1615 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPENn_Pos (0) |
BPWM_T::CAPCTL: CAPENn Position
Definition at line 1614 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPINV0_Msk (0x1ul << BPWM_CAPCTL_CAPINV0_Pos) |
BPWM_T::CAPCTL: CAPINV0 Mask
Definition at line 1618 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPINV0_Pos (8) |
BPWM_T::CAPCTL: CAPINV0 Position
Definition at line 1617 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPINV1_Msk (0x1ul << BPWM_CAPCTL_CAPINV1_Pos) |
BPWM_T::CAPCTL: CAPINV1 Mask
Definition at line 1621 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPINV1_Pos (9) |
BPWM_T::CAPCTL: CAPINV1 Position
Definition at line 1620 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPINV2_Msk (0x1ul << BPWM_CAPCTL_CAPINV2_Pos) |
BPWM_T::CAPCTL: CAPINV2 Mask
Definition at line 1624 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPINV2_Pos (10) |
BPWM_T::CAPCTL: CAPINV2 Position
Definition at line 1623 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPINV3_Msk (0x1ul << BPWM_CAPCTL_CAPINV3_Pos) |
BPWM_T::CAPCTL: CAPINV3 Mask
Definition at line 1627 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPINV3_Pos (11) |
BPWM_T::CAPCTL: CAPINV3 Position
Definition at line 1626 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPINV4_Msk (0x1ul << BPWM_CAPCTL_CAPINV4_Pos) |
BPWM_T::CAPCTL: CAPINV4 Mask
Definition at line 1630 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPINV4_Pos (12) |
BPWM_T::CAPCTL: CAPINV4 Position
Definition at line 1629 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPINV5_Msk (0x1ul << BPWM_CAPCTL_CAPINV5_Pos) |
BPWM_T::CAPCTL: CAPINV5 Mask
Definition at line 1633 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPINV5_Pos (13) |
BPWM_T::CAPCTL: CAPINV5 Position
Definition at line 1632 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPINVn_Msk (0x3ful << BPWM_CAPCTL_CAPINVn_Pos) |
BPWM_T::CAPCTL: CAPINVn Mask
Definition at line 1636 of file bpwm_reg.h.
| #define BPWM_CAPCTL_CAPINVn_Pos (8) |
BPWM_T::CAPCTL: CAPINVn Position
Definition at line 1635 of file bpwm_reg.h.
| #define BPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN0_Pos) |
BPWM_T::CAPCTL: FCRLDEN0 Mask
Definition at line 1660 of file bpwm_reg.h.
| #define BPWM_CAPCTL_FCRLDEN0_Pos (24) |
BPWM_T::CAPCTL: FCRLDEN0 Position
Definition at line 1659 of file bpwm_reg.h.
| #define BPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN1_Pos) |
BPWM_T::CAPCTL: FCRLDEN1 Mask
Definition at line 1663 of file bpwm_reg.h.
| #define BPWM_CAPCTL_FCRLDEN1_Pos (25) |
BPWM_T::CAPCTL: FCRLDEN1 Position
Definition at line 1662 of file bpwm_reg.h.
| #define BPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN2_Pos) |
BPWM_T::CAPCTL: FCRLDEN2 Mask
Definition at line 1666 of file bpwm_reg.h.
| #define BPWM_CAPCTL_FCRLDEN2_Pos (26) |
BPWM_T::CAPCTL: FCRLDEN2 Position
Definition at line 1665 of file bpwm_reg.h.
| #define BPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN3_Pos) |
BPWM_T::CAPCTL: FCRLDEN3 Mask
Definition at line 1669 of file bpwm_reg.h.
| #define BPWM_CAPCTL_FCRLDEN3_Pos (27) |
BPWM_T::CAPCTL: FCRLDEN3 Position
Definition at line 1668 of file bpwm_reg.h.
| #define BPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN4_Pos) |
BPWM_T::CAPCTL: FCRLDEN4 Mask
Definition at line 1672 of file bpwm_reg.h.
| #define BPWM_CAPCTL_FCRLDEN4_Pos (28) |
BPWM_T::CAPCTL: FCRLDEN4 Position
Definition at line 1671 of file bpwm_reg.h.
| #define BPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_FCRLDEN5_Pos) |
BPWM_T::CAPCTL: FCRLDEN5 Mask
Definition at line 1675 of file bpwm_reg.h.
| #define BPWM_CAPCTL_FCRLDEN5_Pos (29) |
BPWM_T::CAPCTL: FCRLDEN5 Position
Definition at line 1674 of file bpwm_reg.h.
| #define BPWM_CAPCTL_FCRLDENn_Msk (0x3ful << BPWM_CAPCTL_FCRLDENn_Pos) |
BPWM_T::CAPCTL: FCRLDENn Mask
Definition at line 1678 of file bpwm_reg.h.
| #define BPWM_CAPCTL_FCRLDENn_Pos (24) |
BPWM_T::CAPCTL: FCRLDENn Position
Definition at line 1677 of file bpwm_reg.h.
| #define BPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN0_Pos) |
BPWM_T::CAPCTL: RCRLDEN0 Mask
Definition at line 1639 of file bpwm_reg.h.
| #define BPWM_CAPCTL_RCRLDEN0_Pos (16) |
BPWM_T::CAPCTL: RCRLDEN0 Position
Definition at line 1638 of file bpwm_reg.h.
| #define BPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN1_Pos) |
BPWM_T::CAPCTL: RCRLDEN1 Mask
Definition at line 1642 of file bpwm_reg.h.
| #define BPWM_CAPCTL_RCRLDEN1_Pos (17) |
BPWM_T::CAPCTL: RCRLDEN1 Position
Definition at line 1641 of file bpwm_reg.h.
| #define BPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN2_Pos) |
BPWM_T::CAPCTL: RCRLDEN2 Mask
Definition at line 1645 of file bpwm_reg.h.
| #define BPWM_CAPCTL_RCRLDEN2_Pos (18) |
BPWM_T::CAPCTL: RCRLDEN2 Position
Definition at line 1644 of file bpwm_reg.h.
| #define BPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN3_Pos) |
BPWM_T::CAPCTL: RCRLDEN3 Mask
Definition at line 1648 of file bpwm_reg.h.
| #define BPWM_CAPCTL_RCRLDEN3_Pos (19) |
BPWM_T::CAPCTL: RCRLDEN3 Position
Definition at line 1647 of file bpwm_reg.h.
| #define BPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN4_Pos) |
BPWM_T::CAPCTL: RCRLDEN4 Mask
Definition at line 1651 of file bpwm_reg.h.
| #define BPWM_CAPCTL_RCRLDEN4_Pos (20) |
BPWM_T::CAPCTL: RCRLDEN4 Position
Definition at line 1650 of file bpwm_reg.h.
| #define BPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << BPWM_CAPCTL_RCRLDEN5_Pos) |
BPWM_T::CAPCTL: RCRLDEN5 Mask
Definition at line 1654 of file bpwm_reg.h.
| #define BPWM_CAPCTL_RCRLDEN5_Pos (21) |
BPWM_T::CAPCTL: RCRLDEN5 Position
Definition at line 1653 of file bpwm_reg.h.
| #define BPWM_CAPCTL_RCRLDENn_Msk (0x3ful << BPWM_CAPCTL_RCRLDENn_Pos) |
BPWM_T::CAPCTL: RCRLDENn Mask
Definition at line 1657 of file bpwm_reg.h.
| #define BPWM_CAPCTL_RCRLDENn_Pos (16) |
BPWM_T::CAPCTL: RCRLDENn Position
Definition at line 1656 of file bpwm_reg.h.
| #define BPWM_CAPIEN_CAPFIENn_Msk (0x3ful << BPWM_CAPIEN_CAPFIENn_Pos) |
BPWM_T::CAPIEN: CAPFIENn Mask
Definition at line 1762 of file bpwm_reg.h.
| #define BPWM_CAPIEN_CAPFIENn_Pos (8) |
BPWM_T::CAPIEN: CAPFIENn Position
Definition at line 1761 of file bpwm_reg.h.
| #define BPWM_CAPIEN_CAPRIENn_Msk (0x3ful << BPWM_CAPIEN_CAPRIENn_Pos) |
BPWM_T::CAPIEN: CAPRIENn Mask
Definition at line 1759 of file bpwm_reg.h.
| #define BPWM_CAPIEN_CAPRIENn_Pos (0) |
BPWM_T::CAPIEN: CAPRIENn Position
Definition at line 1758 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPFIF0_Msk (0x1ul << BPWM_CAPIF_CAPFIF0_Pos) |
BPWM_T::CAPIF: CAPFIF0 Mask
Definition at line 1786 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPFIF0_Pos (8) |
BPWM_T::CAPIF: CAPFIF0 Position
Definition at line 1785 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPFIF1_Msk (0x1ul << BPWM_CAPIF_CAPFIF1_Pos) |
BPWM_T::CAPIF: CAPFIF1 Mask
Definition at line 1789 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPFIF1_Pos (9) |
BPWM_T::CAPIF: CAPFIF1 Position
Definition at line 1788 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPFIF2_Msk (0x1ul << BPWM_CAPIF_CAPFIF2_Pos) |
BPWM_T::CAPIF: CAPFIF2 Mask
Definition at line 1792 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPFIF2_Pos (10) |
BPWM_T::CAPIF: CAPFIF2 Position
Definition at line 1791 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPFIF3_Msk (0x1ul << BPWM_CAPIF_CAPFIF3_Pos) |
BPWM_T::CAPIF: CAPFIF3 Mask
Definition at line 1795 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPFIF3_Pos (11) |
BPWM_T::CAPIF: CAPFIF3 Position
Definition at line 1794 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPFIF4_Msk (0x1ul << BPWM_CAPIF_CAPFIF4_Pos) |
BPWM_T::CAPIF: CAPFIF4 Mask
Definition at line 1798 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPFIF4_Pos (12) |
BPWM_T::CAPIF: CAPFIF4 Position
Definition at line 1797 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPFIF5_Msk (0x1ul << BPWM_CAPIF_CAPFIF5_Pos) |
BPWM_T::CAPIF: CAPFIF5 Mask
Definition at line 1801 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPFIF5_Pos (13) |
BPWM_T::CAPIF: CAPFIF5 Position
Definition at line 1800 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPFIFn_Msk (0x3ful << BPWM_CAPIF_CAPFIFn_Pos) |
BPWM_T::CAPIF: CAPFIFn Mask
Definition at line 1804 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPFIFn_Pos (8) |
BPWM_T::CAPIF: CAPFIFn Position
Definition at line 1803 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPRIF0_Msk (0x1ul << BPWM_CAPIF_CAPRIF0_Pos) |
BPWM_T::CAPIF: CAPRIF0 Mask
Definition at line 1765 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPRIF0_Pos (0) |
BPWM_T::CAPIF: CAPRIF0 Position
Definition at line 1764 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPRIF1_Msk (0x1ul << BPWM_CAPIF_CAPRIF1_Pos) |
BPWM_T::CAPIF: CAPRIF1 Mask
Definition at line 1768 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPRIF1_Pos (1) |
BPWM_T::CAPIF: CAPRIF1 Position
Definition at line 1767 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPRIF2_Msk (0x1ul << BPWM_CAPIF_CAPRIF2_Pos) |
BPWM_T::CAPIF: CAPRIF2 Mask
Definition at line 1771 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPRIF2_Pos (2) |
BPWM_T::CAPIF: CAPRIF2 Position
Definition at line 1770 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPRIF3_Msk (0x1ul << BPWM_CAPIF_CAPRIF3_Pos) |
BPWM_T::CAPIF: CAPRIF3 Mask
Definition at line 1774 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPRIF3_Pos (3) |
BPWM_T::CAPIF: CAPRIF3 Position
Definition at line 1773 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPRIF4_Msk (0x1ul << BPWM_CAPIF_CAPRIF4_Pos) |
BPWM_T::CAPIF: CAPRIF4 Mask
Definition at line 1777 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPRIF4_Pos (4) |
BPWM_T::CAPIF: CAPRIF4 Position
Definition at line 1776 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPRIF5_Msk (0x1ul << BPWM_CAPIF_CAPRIF5_Pos) |
BPWM_T::CAPIF: CAPRIF5 Mask
Definition at line 1780 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPRIF5_Pos (5) |
BPWM_T::CAPIF: CAPRIF5 Position
Definition at line 1779 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPRIFn_Msk (0x3ful << BPWM_CAPIF_CAPRIFn_Pos) |
BPWM_T::CAPIF: CAPRIFn Mask
Definition at line 1783 of file bpwm_reg.h.
| #define BPWM_CAPIF_CAPRIFn_Pos (0) |
BPWM_T::CAPIF: CAPRIFn Position
Definition at line 1782 of file bpwm_reg.h.
| #define BPWM_CAPINEN_CAPINEN0_Msk (0x1ul << BPWM_CAPINEN_CAPINEN0_Pos) |
BPWM_T::CAPINEN: CAPINEN0 Mask
Definition at line 1576 of file bpwm_reg.h.
| #define BPWM_CAPINEN_CAPINEN0_Pos (0) |
BPWM_T::CAPINEN: CAPINEN0 Position
Definition at line 1575 of file bpwm_reg.h.
| #define BPWM_CAPINEN_CAPINEN1_Msk (0x1ul << BPWM_CAPINEN_CAPINEN1_Pos) |
BPWM_T::CAPINEN: CAPINEN1 Mask
Definition at line 1579 of file bpwm_reg.h.
| #define BPWM_CAPINEN_CAPINEN1_Pos (1) |
BPWM_T::CAPINEN: CAPINEN1 Position
Definition at line 1578 of file bpwm_reg.h.
| #define BPWM_CAPINEN_CAPINEN2_Msk (0x1ul << BPWM_CAPINEN_CAPINEN2_Pos) |
BPWM_T::CAPINEN: CAPINEN2 Mask
Definition at line 1582 of file bpwm_reg.h.
| #define BPWM_CAPINEN_CAPINEN2_Pos (2) |
BPWM_T::CAPINEN: CAPINEN2 Position
Definition at line 1581 of file bpwm_reg.h.
| #define BPWM_CAPINEN_CAPINEN3_Msk (0x1ul << BPWM_CAPINEN_CAPINEN3_Pos) |
BPWM_T::CAPINEN: CAPINEN3 Mask
Definition at line 1585 of file bpwm_reg.h.
| #define BPWM_CAPINEN_CAPINEN3_Pos (3) |
BPWM_T::CAPINEN: CAPINEN3 Position
Definition at line 1584 of file bpwm_reg.h.
| #define BPWM_CAPINEN_CAPINEN4_Msk (0x1ul << BPWM_CAPINEN_CAPINEN4_Pos) |
BPWM_T::CAPINEN: CAPINEN4 Mask
Definition at line 1588 of file bpwm_reg.h.
| #define BPWM_CAPINEN_CAPINEN4_Pos (4) |
BPWM_T::CAPINEN: CAPINEN4 Position
Definition at line 1587 of file bpwm_reg.h.
| #define BPWM_CAPINEN_CAPINEN5_Msk (0x1ul << BPWM_CAPINEN_CAPINEN5_Pos) |
BPWM_T::CAPINEN: CAPINEN5 Mask
Definition at line 1591 of file bpwm_reg.h.
| #define BPWM_CAPINEN_CAPINEN5_Pos (5) |
BPWM_T::CAPINEN: CAPINEN5 Position
Definition at line 1590 of file bpwm_reg.h.
| #define BPWM_CAPINEN_CAPINENn_Msk (0x3ful << BPWM_CAPINEN_CAPINENn_Pos) |
BPWM_T::CAPINEN: CAPINENn Mask
Definition at line 1594 of file bpwm_reg.h.
| #define BPWM_CAPINEN_CAPINENn_Pos (0) |
BPWM_T::CAPINEN: CAPINENn Position
Definition at line 1593 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CFIFOV0_Msk (0x1ul << BPWM_CAPSTS_CFIFOV0_Pos) |
BPWM_T::CAPSTS: CFIFOV0 Mask
Definition at line 1702 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CFIFOV0_Pos (8) |
BPWM_T::CAPSTS: CFIFOV0 Position
Definition at line 1701 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CFIFOV1_Msk (0x1ul << BPWM_CAPSTS_CFIFOV1_Pos) |
BPWM_T::CAPSTS: CFIFOV1 Mask
Definition at line 1705 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CFIFOV1_Pos (9) |
BPWM_T::CAPSTS: CFIFOV1 Position
Definition at line 1704 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CFIFOV2_Msk (0x1ul << BPWM_CAPSTS_CFIFOV2_Pos) |
BPWM_T::CAPSTS: CFIFOV2 Mask
Definition at line 1708 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CFIFOV2_Pos (10) |
BPWM_T::CAPSTS: CFIFOV2 Position
Definition at line 1707 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CFIFOV3_Msk (0x1ul << BPWM_CAPSTS_CFIFOV3_Pos) |
BPWM_T::CAPSTS: CFIFOV3 Mask
Definition at line 1711 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CFIFOV3_Pos (11) |
BPWM_T::CAPSTS: CFIFOV3 Position
Definition at line 1710 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CFIFOV4_Msk (0x1ul << BPWM_CAPSTS_CFIFOV4_Pos) |
BPWM_T::CAPSTS: CFIFOV4 Mask
Definition at line 1714 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CFIFOV4_Pos (12) |
BPWM_T::CAPSTS: CFIFOV4 Position
Definition at line 1713 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CFIFOV5_Msk (0x1ul << BPWM_CAPSTS_CFIFOV5_Pos) |
BPWM_T::CAPSTS: CFIFOV5 Mask
Definition at line 1717 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CFIFOV5_Pos (13) |
BPWM_T::CAPSTS: CFIFOV5 Position
Definition at line 1716 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CFIFOVn_Msk (0x3ful << BPWM_CAPSTS_CFIFOVn_Pos) |
BPWM_T::CAPSTS: CFIFOVn Mask
Definition at line 1720 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CFIFOVn_Pos (8) |
BPWM_T::CAPSTS: CFIFOVn Position
Definition at line 1719 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CRIFOV0_Msk (0x1ul << BPWM_CAPSTS_CRIFOV0_Pos) |
BPWM_T::CAPSTS: CRIFOV0 Mask
Definition at line 1681 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CRIFOV0_Pos (0) |
BPWM_T::CAPSTS: CRIFOV0 Position
Definition at line 1680 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CRIFOV1_Msk (0x1ul << BPWM_CAPSTS_CRIFOV1_Pos) |
BPWM_T::CAPSTS: CRIFOV1 Mask
Definition at line 1684 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CRIFOV1_Pos (1) |
BPWM_T::CAPSTS: CRIFOV1 Position
Definition at line 1683 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CRIFOV2_Msk (0x1ul << BPWM_CAPSTS_CRIFOV2_Pos) |
BPWM_T::CAPSTS: CRIFOV2 Mask
Definition at line 1687 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CRIFOV2_Pos (2) |
BPWM_T::CAPSTS: CRIFOV2 Position
Definition at line 1686 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CRIFOV3_Msk (0x1ul << BPWM_CAPSTS_CRIFOV3_Pos) |
BPWM_T::CAPSTS: CRIFOV3 Mask
Definition at line 1690 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CRIFOV3_Pos (3) |
BPWM_T::CAPSTS: CRIFOV3 Position
Definition at line 1689 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CRIFOV4_Msk (0x1ul << BPWM_CAPSTS_CRIFOV4_Pos) |
BPWM_T::CAPSTS: CRIFOV4 Mask
Definition at line 1693 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CRIFOV4_Pos (4) |
BPWM_T::CAPSTS: CRIFOV4 Position
Definition at line 1692 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CRIFOV5_Msk (0x1ul << BPWM_CAPSTS_CRIFOV5_Pos) |
BPWM_T::CAPSTS: CRIFOV5 Mask
Definition at line 1696 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CRIFOV5_Pos (5) |
BPWM_T::CAPSTS: CRIFOV5 Position
Definition at line 1695 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CRIFOVn_Msk (0x3ful << BPWM_CAPSTS_CRIFOVn_Pos) |
BPWM_T::CAPSTS: CRIFOVn Mask
Definition at line 1699 of file bpwm_reg.h.
| #define BPWM_CAPSTS_CRIFOVn_Pos (0) |
BPWM_T::CAPSTS: CRIFOVn Position
Definition at line 1698 of file bpwm_reg.h.
| #define BPWM_CLKPSC_CLKPSC_Msk (0xffful << BPWM_CLKPSC_CLKPSC_Pos) |
BPWM_T::CLKPSC: CLKPSC Mask
Definition at line 1207 of file bpwm_reg.h.
| #define BPWM_CLKPSC_CLKPSC_Pos (0) |
BPWM_T::CLKPSC: CLKPSC Position
Definition at line 1206 of file bpwm_reg.h.
| #define BPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << BPWM_CLKSRC_ECLKSRC0_Pos) |
BPWM_T::CLKSRC: ECLKSRC0 Mask
Definition at line 1204 of file bpwm_reg.h.
| #define BPWM_CLKSRC_ECLKSRC0_Pos (0) |
BPWM_T::CLKSRC: ECLKSRC0 Position
Definition at line 1203 of file bpwm_reg.h.
| #define BPWM_CMPBUF0_CMPBUF_Msk (0xfffful << BPWM_CMPBUF0_CMPBUF_Pos) |
BPWM_T::CMPBUF0: CMPBUF Mask
Definition at line 1810 of file bpwm_reg.h.
| #define BPWM_CMPBUF0_CMPBUF_Pos (0) |
BPWM_T::CMPBUF0: CMPBUF Position
Definition at line 1809 of file bpwm_reg.h.
| #define BPWM_CMPBUF1_CMPBUF_Msk (0xfffful << BPWM_CMPBUF1_CMPBUF_Pos) |
BPWM_T::CMPBUF1: CMPBUF Mask
Definition at line 1813 of file bpwm_reg.h.
| #define BPWM_CMPBUF1_CMPBUF_Pos (0) |
BPWM_T::CMPBUF1: CMPBUF Position
Definition at line 1812 of file bpwm_reg.h.
| #define BPWM_CMPBUF2_CMPBUF_Msk (0xfffful << BPWM_CMPBUF2_CMPBUF_Pos) |
BPWM_T::CMPBUF2: CMPBUF Mask
Definition at line 1816 of file bpwm_reg.h.
| #define BPWM_CMPBUF2_CMPBUF_Pos (0) |
BPWM_T::CMPBUF2: CMPBUF Position
Definition at line 1815 of file bpwm_reg.h.
| #define BPWM_CMPBUF3_CMPBUF_Msk (0xfffful << BPWM_CMPBUF3_CMPBUF_Pos) |
BPWM_T::CMPBUF3: CMPBUF Mask
Definition at line 1819 of file bpwm_reg.h.
| #define BPWM_CMPBUF3_CMPBUF_Pos (0) |
BPWM_T::CMPBUF3: CMPBUF Position
Definition at line 1818 of file bpwm_reg.h.
| #define BPWM_CMPBUF4_CMPBUF_Msk (0xfffful << BPWM_CMPBUF4_CMPBUF_Pos) |
BPWM_T::CMPBUF4: CMPBUF Mask
Definition at line 1822 of file bpwm_reg.h.
| #define BPWM_CMPBUF4_CMPBUF_Pos (0) |
BPWM_T::CMPBUF4: CMPBUF Position
Definition at line 1821 of file bpwm_reg.h.
| #define BPWM_CMPBUF5_CMPBUF_Msk (0xfffful << BPWM_CMPBUF5_CMPBUF_Pos) |
BPWM_T::CMPBUF5: CMPBUF Mask
Definition at line 1825 of file bpwm_reg.h.
| #define BPWM_CMPBUF5_CMPBUF_Pos (0) |
BPWM_T::CMPBUF5: CMPBUF Position
Definition at line 1824 of file bpwm_reg.h.
| #define BPWM_CMPDAT0_CMPDAT_Msk (0xfffful << BPWM_CMPDAT0_CMPDAT_Pos) |
BPWM_T::CMPDAT0: CMPDAT Mask
Definition at line 1219 of file bpwm_reg.h.
| #define BPWM_CMPDAT0_CMPDAT_Pos (0) |
BPWM_T::CMPDAT0: CMPDAT Position
Definition at line 1218 of file bpwm_reg.h.
| #define BPWM_CMPDAT1_CMPDAT_Msk (0xfffful << BPWM_CMPDAT1_CMPDAT_Pos) |
BPWM_T::CMPDAT1: CMPDAT Mask
Definition at line 1222 of file bpwm_reg.h.
| #define BPWM_CMPDAT1_CMPDAT_Pos (0) |
BPWM_T::CMPDAT1: CMPDAT Position
Definition at line 1221 of file bpwm_reg.h.
| #define BPWM_CMPDAT2_CMPDAT_Msk (0xfffful << BPWM_CMPDAT2_CMPDAT_Pos) |
BPWM_T::CMPDAT2: CMPDAT Mask
Definition at line 1225 of file bpwm_reg.h.
| #define BPWM_CMPDAT2_CMPDAT_Pos (0) |
BPWM_T::CMPDAT2: CMPDAT Position
Definition at line 1224 of file bpwm_reg.h.
| #define BPWM_CMPDAT3_CMPDAT_Msk (0xfffful << BPWM_CMPDAT3_CMPDAT_Pos) |
BPWM_T::CMPDAT3: CMPDAT Mask
Definition at line 1228 of file bpwm_reg.h.
| #define BPWM_CMPDAT3_CMPDAT_Pos (0) |
BPWM_T::CMPDAT3: CMPDAT Position
Definition at line 1227 of file bpwm_reg.h.
| #define BPWM_CMPDAT4_CMPDAT_Msk (0xfffful << BPWM_CMPDAT4_CMPDAT_Pos) |
BPWM_T::CMPDAT4: CMPDAT Mask
Definition at line 1231 of file bpwm_reg.h.
| #define BPWM_CMPDAT4_CMPDAT_Pos (0) |
BPWM_T::CMPDAT4: CMPDAT Position
Definition at line 1230 of file bpwm_reg.h.
| #define BPWM_CMPDAT5_CMPDAT_Msk (0xfffful << BPWM_CMPDAT5_CMPDAT_Pos) |
BPWM_T::CMPDAT5: CMPDAT Mask
Definition at line 1234 of file bpwm_reg.h.
| #define BPWM_CMPDAT5_CMPDAT_Pos (0) |
BPWM_T::CMPDAT5: CMPDAT Position
Definition at line 1233 of file bpwm_reg.h.
| #define BPWM_CNT_CNT_Msk (0xfffful << BPWM_CNT_CNT_Pos) |
BPWM_T::CNT: CNT Mask
Definition at line 1237 of file bpwm_reg.h.
| #define BPWM_CNT_CNT_Pos (0) |
BPWM_T::CNT: CNT Position
Definition at line 1236 of file bpwm_reg.h.
| #define BPWM_CNT_DIRF_Msk (0x1ul << BPWM_CNT_DIRF_Pos) |
BPWM_T::CNT: DIRF Mask
Definition at line 1240 of file bpwm_reg.h.
| #define BPWM_CNT_DIRF_Pos (16) |
BPWM_T::CNT: DIRF Position
Definition at line 1239 of file bpwm_reg.h.
| #define BPWM_CNTCLR_CNTCLR0_Msk (0x1ul << BPWM_CNTCLR_CNTCLR0_Pos) |
BPWM_T::CNTCLR: CNTCLR0 Mask
Definition at line 1213 of file bpwm_reg.h.
| #define BPWM_CNTCLR_CNTCLR0_Pos (0) |
BPWM_T::CNTCLR: CNTCLR0 Position
Definition at line 1212 of file bpwm_reg.h.
| #define BPWM_CNTEN_CNTEN0_Msk (0x1ul << BPWM_CNTEN_CNTEN0_Pos) |
BPWM_T::CNTEN: CNTEN0 Mask
Definition at line 1210 of file bpwm_reg.h.
| #define BPWM_CNTEN_CNTEN0_Pos (0) |
BPWM_T::CNTEN: CNTEN0 Position
Definition at line 1209 of file bpwm_reg.h.
| #define BPWM_CTL0_CTRLD0_Msk (0x1ul << BPWM_CTL0_CTRLD0_Pos) |
BPWM_T::CTL0: CTRLD0 Mask
Definition at line 1159 of file bpwm_reg.h.
| #define BPWM_CTL0_CTRLD0_Pos (0) |
@addtogroup BPWM_CONST BPWM Bit Field Definition Constant Definitions for BPWM Controller
BPWM_T::CTL0: CTRLD0 Position
Definition at line 1158 of file bpwm_reg.h.
| #define BPWM_CTL0_CTRLD1_Msk (0x1ul << BPWM_CTL0_CTRLD1_Pos) |
BPWM_T::CTL0: CTRLD1 Mask
Definition at line 1162 of file bpwm_reg.h.
| #define BPWM_CTL0_CTRLD1_Pos (1) |
BPWM_T::CTL0: CTRLD1 Position
Definition at line 1161 of file bpwm_reg.h.
| #define BPWM_CTL0_CTRLD2_Msk (0x1ul << BPWM_CTL0_CTRLD2_Pos) |
BPWM_T::CTL0: CTRLD2 Mask
Definition at line 1165 of file bpwm_reg.h.
| #define BPWM_CTL0_CTRLD2_Pos (2) |
BPWM_T::CTL0: CTRLD2 Position
Definition at line 1164 of file bpwm_reg.h.
| #define BPWM_CTL0_CTRLD3_Msk (0x1ul << BPWM_CTL0_CTRLD3_Pos) |
BPWM_T::CTL0: CTRLD3 Mask
Definition at line 1168 of file bpwm_reg.h.
| #define BPWM_CTL0_CTRLD3_Pos (3) |
BPWM_T::CTL0: CTRLD3 Position
Definition at line 1167 of file bpwm_reg.h.
| #define BPWM_CTL0_CTRLD4_Msk (0x1ul << BPWM_CTL0_CTRLD4_Pos) |
BPWM_T::CTL0: CTRLD4 Mask
Definition at line 1171 of file bpwm_reg.h.
| #define BPWM_CTL0_CTRLD4_Pos (4) |
BPWM_T::CTL0: CTRLD4 Position
Definition at line 1170 of file bpwm_reg.h.
| #define BPWM_CTL0_CTRLD5_Msk (0x1ul << BPWM_CTL0_CTRLD5_Pos) |
BPWM_T::CTL0: CTRLD5 Mask
Definition at line 1174 of file bpwm_reg.h.
| #define BPWM_CTL0_CTRLD5_Pos (5) |
BPWM_T::CTL0: CTRLD5 Position
Definition at line 1173 of file bpwm_reg.h.
| #define BPWM_CTL0_DBGHALT_Msk (0x1ul << BPWM_CTL0_DBGHALT_Pos) |
BPWM_T::CTL0: DBGHALT Mask
Definition at line 1195 of file bpwm_reg.h.
| #define BPWM_CTL0_DBGHALT_Pos (30) |
BPWM_T::CTL0: DBGHALT Position
Definition at line 1194 of file bpwm_reg.h.
| #define BPWM_CTL0_DBGTRIOFF_Msk (0x1ul << BPWM_CTL0_DBGTRIOFF_Pos) |
BPWM_T::CTL0: DBGTRIOFF Mask
Definition at line 1198 of file bpwm_reg.h.
| #define BPWM_CTL0_DBGTRIOFF_Pos (31) |
BPWM_T::CTL0: DBGTRIOFF Position
Definition at line 1197 of file bpwm_reg.h.
| #define BPWM_CTL0_IMMLDEN0_Msk (0x1ul << BPWM_CTL0_IMMLDEN0_Pos) |
BPWM_T::CTL0: IMMLDEN0 Mask
Definition at line 1177 of file bpwm_reg.h.
| #define BPWM_CTL0_IMMLDEN0_Pos (16) |
BPWM_T::CTL0: IMMLDEN0 Position
Definition at line 1176 of file bpwm_reg.h.
| #define BPWM_CTL0_IMMLDEN1_Msk (0x1ul << BPWM_CTL0_IMMLDEN1_Pos) |
BPWM_T::CTL0: IMMLDEN1 Mask
Definition at line 1180 of file bpwm_reg.h.
| #define BPWM_CTL0_IMMLDEN1_Pos (17) |
BPWM_T::CTL0: IMMLDEN1 Position
Definition at line 1179 of file bpwm_reg.h.
| #define BPWM_CTL0_IMMLDEN2_Msk (0x1ul << BPWM_CTL0_IMMLDEN2_Pos) |
BPWM_T::CTL0: IMMLDEN2 Mask
Definition at line 1183 of file bpwm_reg.h.
| #define BPWM_CTL0_IMMLDEN2_Pos (18) |
BPWM_T::CTL0: IMMLDEN2 Position
Definition at line 1182 of file bpwm_reg.h.
| #define BPWM_CTL0_IMMLDEN3_Msk (0x1ul << BPWM_CTL0_IMMLDEN3_Pos) |
BPWM_T::CTL0: IMMLDEN3 Mask
Definition at line 1186 of file bpwm_reg.h.
| #define BPWM_CTL0_IMMLDEN3_Pos (19) |
BPWM_T::CTL0: IMMLDEN3 Position
Definition at line 1185 of file bpwm_reg.h.
| #define BPWM_CTL0_IMMLDEN4_Msk (0x1ul << BPWM_CTL0_IMMLDEN4_Pos) |
BPWM_T::CTL0: IMMLDEN4 Mask
Definition at line 1189 of file bpwm_reg.h.
| #define BPWM_CTL0_IMMLDEN4_Pos (20) |
BPWM_T::CTL0: IMMLDEN4 Position
Definition at line 1188 of file bpwm_reg.h.
| #define BPWM_CTL0_IMMLDEN5_Msk (0x1ul << BPWM_CTL0_IMMLDEN5_Pos) |
BPWM_T::CTL0: IMMLDEN5 Mask
Definition at line 1192 of file bpwm_reg.h.
| #define BPWM_CTL0_IMMLDEN5_Pos (21) |
BPWM_T::CTL0: IMMLDEN5 Position
Definition at line 1191 of file bpwm_reg.h.
| #define BPWM_CTL1_CNTTYPE0_Msk (0x3ul << BPWM_CTL1_CNTTYPE0_Pos) |
BPWM_T::CTL1: CNTTYPE0 Mask
Definition at line 1201 of file bpwm_reg.h.
| #define BPWM_CTL1_CNTTYPE0_Pos (0) |
BPWM_T::CTL1: CNTTYPE0 Position
Definition at line 1200 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGEN0_Msk (0x1ul << BPWM_EADCTS0_TRGEN0_Pos) |
BPWM_T::EADCTS0: TRGEN0 Mask
Definition at line 1510 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGEN0_Pos (7) |
BPWM_T::EADCTS0: TRGEN0 Position
Definition at line 1509 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGEN1_Msk (0x1ul << BPWM_EADCTS0_TRGEN1_Pos) |
BPWM_T::EADCTS0: TRGEN1 Mask
Definition at line 1516 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGEN1_Pos (15) |
BPWM_T::EADCTS0: TRGEN1 Position
Definition at line 1515 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGEN2_Msk (0x1ul << BPWM_EADCTS0_TRGEN2_Pos) |
BPWM_T::EADCTS0: TRGEN2 Mask
Definition at line 1522 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGEN2_Pos (23) |
BPWM_T::EADCTS0: TRGEN2 Position
Definition at line 1521 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGEN3_Msk (0x1ul << BPWM_EADCTS0_TRGEN3_Pos) |
BPWM_T::EADCTS0: TRGEN3 Mask
Definition at line 1528 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGEN3_Pos (31) |
BPWM_T::EADCTS0: TRGEN3 Position
Definition at line 1527 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGSEL0_Msk (0xful << BPWM_EADCTS0_TRGSEL0_Pos) |
BPWM_T::EADCTS0: TRGSEL0 Mask
Definition at line 1507 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGSEL0_Pos (0) |
BPWM_T::EADCTS0: TRGSEL0 Position
Definition at line 1506 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGSEL1_Msk (0xful << BPWM_EADCTS0_TRGSEL1_Pos) |
BPWM_T::EADCTS0: TRGSEL1 Mask
Definition at line 1513 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGSEL1_Pos (8) |
BPWM_T::EADCTS0: TRGSEL1 Position
Definition at line 1512 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGSEL2_Msk (0xful << BPWM_EADCTS0_TRGSEL2_Pos) |
BPWM_T::EADCTS0: TRGSEL2 Mask
Definition at line 1519 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGSEL2_Pos (16) |
BPWM_T::EADCTS0: TRGSEL2 Position
Definition at line 1518 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGSEL3_Msk (0xful << BPWM_EADCTS0_TRGSEL3_Pos) |
BPWM_T::EADCTS0: TRGSEL3 Mask
Definition at line 1525 of file bpwm_reg.h.
| #define BPWM_EADCTS0_TRGSEL3_Pos (24) |
BPWM_T::EADCTS0: TRGSEL3 Position
Definition at line 1524 of file bpwm_reg.h.
| #define BPWM_EADCTS1_TRGEN4_Msk (0x1ul << BPWM_EADCTS1_TRGEN4_Pos) |
BPWM_T::EADCTS1: TRGEN4 Mask
Definition at line 1534 of file bpwm_reg.h.
| #define BPWM_EADCTS1_TRGEN4_Pos (7) |
BPWM_T::EADCTS1: TRGEN4 Position
Definition at line 1533 of file bpwm_reg.h.
| #define BPWM_EADCTS1_TRGEN5_Msk (0x1ul << BPWM_EADCTS1_TRGEN5_Pos) |
BPWM_T::EADCTS1: TRGEN5 Mask
Definition at line 1540 of file bpwm_reg.h.
| #define BPWM_EADCTS1_TRGEN5_Pos (15) |
BPWM_T::EADCTS1: TRGEN5 Position
Definition at line 1539 of file bpwm_reg.h.
| #define BPWM_EADCTS1_TRGSEL4_Msk (0xful << BPWM_EADCTS1_TRGSEL4_Pos) |
BPWM_T::EADCTS1: TRGSEL4 Mask
Definition at line 1531 of file bpwm_reg.h.
| #define BPWM_EADCTS1_TRGSEL4_Pos (0) |
BPWM_T::EADCTS1: TRGSEL4 Position
Definition at line 1530 of file bpwm_reg.h.
| #define BPWM_EADCTS1_TRGSEL5_Msk (0xful << BPWM_EADCTS1_TRGSEL5_Pos) |
BPWM_T::EADCTS1: TRGSEL5 Mask
Definition at line 1537 of file bpwm_reg.h.
| #define BPWM_EADCTS1_TRGSEL5_Pos (8) |
BPWM_T::EADCTS1: TRGSEL5 Position
Definition at line 1536 of file bpwm_reg.h.
| #define BPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT0_FCAPDAT_Pos) |
BPWM_T::FCAPDAT0: FCAPDAT Mask
Definition at line 1726 of file bpwm_reg.h.
| #define BPWM_FCAPDAT0_FCAPDAT_Pos (0) |
BPWM_T::FCAPDAT0: FCAPDAT Position
Definition at line 1725 of file bpwm_reg.h.
| #define BPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT1_FCAPDAT_Pos) |
BPWM_T::FCAPDAT1: FCAPDAT Mask
Definition at line 1732 of file bpwm_reg.h.
| #define BPWM_FCAPDAT1_FCAPDAT_Pos (0) |
BPWM_T::FCAPDAT1: FCAPDAT Position
Definition at line 1731 of file bpwm_reg.h.
| #define BPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT2_FCAPDAT_Pos) |
BPWM_T::FCAPDAT2: FCAPDAT Mask
Definition at line 1738 of file bpwm_reg.h.
| #define BPWM_FCAPDAT2_FCAPDAT_Pos (0) |
BPWM_T::FCAPDAT2: FCAPDAT Position
Definition at line 1737 of file bpwm_reg.h.
| #define BPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT3_FCAPDAT_Pos) |
BPWM_T::FCAPDAT3: FCAPDAT Mask
Definition at line 1744 of file bpwm_reg.h.
| #define BPWM_FCAPDAT3_FCAPDAT_Pos (0) |
BPWM_T::FCAPDAT3: FCAPDAT Position
Definition at line 1743 of file bpwm_reg.h.
| #define BPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT4_FCAPDAT_Pos) |
BPWM_T::FCAPDAT4: FCAPDAT Mask
Definition at line 1750 of file bpwm_reg.h.
| #define BPWM_FCAPDAT4_FCAPDAT_Pos (0) |
BPWM_T::FCAPDAT4: FCAPDAT Position
Definition at line 1749 of file bpwm_reg.h.
| #define BPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << BPWM_FCAPDAT5_FCAPDAT_Pos) |
BPWM_T::FCAPDAT5: FCAPDAT Mask
Definition at line 1756 of file bpwm_reg.h.
| #define BPWM_FCAPDAT5_FCAPDAT_Pos (0) |
BPWM_T::FCAPDAT5: FCAPDAT Position
Definition at line 1755 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPDIEN0_Msk (0x1ul << BPWM_INTEN_CMPDIEN0_Pos) |
BPWM_T::INTEN: CMPDIEN0 Mask
Definition at line 1438 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPDIEN0_Pos (24) |
BPWM_T::INTEN: CMPDIEN0 Position
Definition at line 1437 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPDIEN1_Msk (0x1ul << BPWM_INTEN_CMPDIEN1_Pos) |
BPWM_T::INTEN: CMPDIEN1 Mask
Definition at line 1441 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPDIEN1_Pos (25) |
BPWM_T::INTEN: CMPDIEN1 Position
Definition at line 1440 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPDIEN2_Msk (0x1ul << BPWM_INTEN_CMPDIEN2_Pos) |
BPWM_T::INTEN: CMPDIEN2 Mask
Definition at line 1444 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPDIEN2_Pos (26) |
BPWM_T::INTEN: CMPDIEN2 Position
Definition at line 1443 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPDIEN3_Msk (0x1ul << BPWM_INTEN_CMPDIEN3_Pos) |
BPWM_T::INTEN: CMPDIEN3 Mask
Definition at line 1447 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPDIEN3_Pos (27) |
BPWM_T::INTEN: CMPDIEN3 Position
Definition at line 1446 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPDIEN4_Msk (0x1ul << BPWM_INTEN_CMPDIEN4_Pos) |
BPWM_T::INTEN: CMPDIEN4 Mask
Definition at line 1450 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPDIEN4_Pos (28) |
BPWM_T::INTEN: CMPDIEN4 Position
Definition at line 1449 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPDIEN5_Msk (0x1ul << BPWM_INTEN_CMPDIEN5_Pos) |
BPWM_T::INTEN: CMPDIEN5 Mask
Definition at line 1453 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPDIEN5_Pos (29) |
BPWM_T::INTEN: CMPDIEN5 Position
Definition at line 1452 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPDIENn_Msk (0x3ful << BPWM_INTEN_CMPDIENn_Pos) |
BPWM_T::INTEN: CMPDIENn Mask
Definition at line 1456 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPDIENn_Pos (24) |
BPWM_T::INTEN: CMPDIENn Position
Definition at line 1455 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPUIEN0_Msk (0x1ul << BPWM_INTEN_CMPUIEN0_Pos) |
BPWM_T::INTEN: CMPUIEN0 Mask
Definition at line 1417 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPUIEN0_Pos (16) |
BPWM_T::INTEN: CMPUIEN0 Position
Definition at line 1416 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPUIEN1_Msk (0x1ul << BPWM_INTEN_CMPUIEN1_Pos) |
BPWM_T::INTEN: CMPUIEN1 Mask
Definition at line 1420 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPUIEN1_Pos (17) |
BPWM_T::INTEN: CMPUIEN1 Position
Definition at line 1419 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPUIEN2_Msk (0x1ul << BPWM_INTEN_CMPUIEN2_Pos) |
BPWM_T::INTEN: CMPUIEN2 Mask
Definition at line 1423 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPUIEN2_Pos (18) |
BPWM_T::INTEN: CMPUIEN2 Position
Definition at line 1422 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPUIEN3_Msk (0x1ul << BPWM_INTEN_CMPUIEN3_Pos) |
BPWM_T::INTEN: CMPUIEN3 Mask
Definition at line 1426 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPUIEN3_Pos (19) |
BPWM_T::INTEN: CMPUIEN3 Position
Definition at line 1425 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPUIEN4_Msk (0x1ul << BPWM_INTEN_CMPUIEN4_Pos) |
BPWM_T::INTEN: CMPUIEN4 Mask
Definition at line 1429 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPUIEN4_Pos (20) |
BPWM_T::INTEN: CMPUIEN4 Position
Definition at line 1428 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPUIEN5_Msk (0x1ul << BPWM_INTEN_CMPUIEN5_Pos) |
BPWM_T::INTEN: CMPUIEN5 Mask
Definition at line 1432 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPUIEN5_Pos (21) |
BPWM_T::INTEN: CMPUIEN5 Position
Definition at line 1431 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPUIENn_Msk (0x3ful << BPWM_INTEN_CMPUIENn_Pos) |
BPWM_T::INTEN: CMPUIENn Mask
Definition at line 1435 of file bpwm_reg.h.
| #define BPWM_INTEN_CMPUIENn_Pos (16) |
BPWM_T::INTEN: CMPUIENn Position
Definition at line 1434 of file bpwm_reg.h.
| #define BPWM_INTEN_PIEN0_Msk (0x1ul << BPWM_INTEN_PIEN0_Pos) |
BPWM_T::INTEN: PIEN0 Mask
Definition at line 1414 of file bpwm_reg.h.
| #define BPWM_INTEN_PIEN0_Pos (8) |
BPWM_T::INTEN: PIEN0 Position
Definition at line 1413 of file bpwm_reg.h.
| #define BPWM_INTEN_ZIEN0_Msk (0x1ul << BPWM_INTEN_ZIEN0_Pos) |
BPWM_T::INTEN: ZIEN0 Mask
Definition at line 1411 of file bpwm_reg.h.
| #define BPWM_INTEN_ZIEN0_Pos (0) |
BPWM_T::INTEN: ZIEN0 Position
Definition at line 1410 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPDIF0_Msk (0x1ul << BPWM_INTSTS_CMPDIF0_Pos) |
BPWM_T::INTSTS: CMPDIF0 Mask
Definition at line 1486 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPDIF0_Pos (24) |
BPWM_T::INTSTS: CMPDIF0 Position
Definition at line 1485 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPDIF1_Msk (0x1ul << BPWM_INTSTS_CMPDIF1_Pos) |
BPWM_T::INTSTS: CMPDIF1 Mask
Definition at line 1489 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPDIF1_Pos (25) |
BPWM_T::INTSTS: CMPDIF1 Position
Definition at line 1488 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPDIF2_Msk (0x1ul << BPWM_INTSTS_CMPDIF2_Pos) |
BPWM_T::INTSTS: CMPDIF2 Mask
Definition at line 1492 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPDIF2_Pos (26) |
BPWM_T::INTSTS: CMPDIF2 Position
Definition at line 1491 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPDIF3_Msk (0x1ul << BPWM_INTSTS_CMPDIF3_Pos) |
BPWM_T::INTSTS: CMPDIF3 Mask
Definition at line 1495 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPDIF3_Pos (27) |
BPWM_T::INTSTS: CMPDIF3 Position
Definition at line 1494 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPDIF4_Msk (0x1ul << BPWM_INTSTS_CMPDIF4_Pos) |
BPWM_T::INTSTS: CMPDIF4 Mask
Definition at line 1498 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPDIF4_Pos (28) |
BPWM_T::INTSTS: CMPDIF4 Position
Definition at line 1497 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPDIF5_Msk (0x1ul << BPWM_INTSTS_CMPDIF5_Pos) |
BPWM_T::INTSTS: CMPDIF5 Mask
Definition at line 1501 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPDIF5_Pos (29) |
BPWM_T::INTSTS: CMPDIF5 Position
Definition at line 1500 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPDIFn_Msk (0x3ful << BPWM_INTSTS_CMPDIFn_Pos) |
BPWM_T::INTSTS: CMPDIFn Mask
Definition at line 1504 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPDIFn_Pos (24) |
BPWM_T::INTSTS: CMPDIFn Position
Definition at line 1503 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPUIF0_Msk (0x1ul << BPWM_INTSTS_CMPUIF0_Pos) |
BPWM_T::INTSTS: CMPUIF0 Mask
Definition at line 1465 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPUIF0_Pos (16) |
BPWM_T::INTSTS: CMPUIF0 Position
Definition at line 1464 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPUIF1_Msk (0x1ul << BPWM_INTSTS_CMPUIF1_Pos) |
BPWM_T::INTSTS: CMPUIF1 Mask
Definition at line 1468 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPUIF1_Pos (17) |
BPWM_T::INTSTS: CMPUIF1 Position
Definition at line 1467 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPUIF2_Msk (0x1ul << BPWM_INTSTS_CMPUIF2_Pos) |
BPWM_T::INTSTS: CMPUIF2 Mask
Definition at line 1471 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPUIF2_Pos (18) |
BPWM_T::INTSTS: CMPUIF2 Position
Definition at line 1470 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPUIF3_Msk (0x1ul << BPWM_INTSTS_CMPUIF3_Pos) |
BPWM_T::INTSTS: CMPUIF3 Mask
Definition at line 1474 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPUIF3_Pos (19) |
BPWM_T::INTSTS: CMPUIF3 Position
Definition at line 1473 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPUIF4_Msk (0x1ul << BPWM_INTSTS_CMPUIF4_Pos) |
BPWM_T::INTSTS: CMPUIF4 Mask
Definition at line 1477 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPUIF4_Pos (20) |
BPWM_T::INTSTS: CMPUIF4 Position
Definition at line 1476 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPUIF5_Msk (0x1ul << BPWM_INTSTS_CMPUIF5_Pos) |
BPWM_T::INTSTS: CMPUIF5 Mask
Definition at line 1480 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPUIF5_Pos (21) |
BPWM_T::INTSTS: CMPUIF5 Position
Definition at line 1479 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPUIFn_Msk (0x3ful << BPWM_INTSTS_CMPUIFn_Pos) |
BPWM_T::INTSTS: CMPUIFn Mask
Definition at line 1483 of file bpwm_reg.h.
| #define BPWM_INTSTS_CMPUIFn_Pos (16) |
BPWM_T::INTSTS: CMPUIFn Position
Definition at line 1482 of file bpwm_reg.h.
| #define BPWM_INTSTS_PIF0_Msk (0x1ul << BPWM_INTSTS_PIF0_Pos) |
BPWM_T::INTSTS: PIF0 Mask
Definition at line 1462 of file bpwm_reg.h.
| #define BPWM_INTSTS_PIF0_Pos (8) |
BPWM_T::INTSTS: PIF0 Position
Definition at line 1461 of file bpwm_reg.h.
| #define BPWM_INTSTS_ZIF0_Msk (0x1ul << BPWM_INTSTS_ZIF0_Pos) |
BPWM_T::INTSTS: ZIF0 Mask
Definition at line 1459 of file bpwm_reg.h.
| #define BPWM_INTSTS_ZIF0_Pos (0) |
BPWM_T::INTSTS: ZIF0 Position
Definition at line 1458 of file bpwm_reg.h.
| #define BPWM_MSK_MSKDAT0_Msk (0x1ul << BPWM_MSK_MSKDAT0_Pos) |
BPWM_T::MSK: MSKDAT0 Mask
Definition at line 1348 of file bpwm_reg.h.
| #define BPWM_MSK_MSKDAT0_Pos (0) |
BPWM_T::MSK: MSKDAT0 Position
Definition at line 1347 of file bpwm_reg.h.
| #define BPWM_MSK_MSKDAT1_Msk (0x1ul << BPWM_MSK_MSKDAT1_Pos) |
BPWM_T::MSK: MSKDAT1 Mask
Definition at line 1351 of file bpwm_reg.h.
| #define BPWM_MSK_MSKDAT1_Pos (1) |
BPWM_T::MSK: MSKDAT1 Position
Definition at line 1350 of file bpwm_reg.h.
| #define BPWM_MSK_MSKDAT2_Msk (0x1ul << BPWM_MSK_MSKDAT2_Pos) |
BPWM_T::MSK: MSKDAT2 Mask
Definition at line 1354 of file bpwm_reg.h.
| #define BPWM_MSK_MSKDAT2_Pos (2) |
BPWM_T::MSK: MSKDAT2 Position
Definition at line 1353 of file bpwm_reg.h.
| #define BPWM_MSK_MSKDAT3_Msk (0x1ul << BPWM_MSK_MSKDAT3_Pos) |
BPWM_T::MSK: MSKDAT3 Mask
Definition at line 1357 of file bpwm_reg.h.
| #define BPWM_MSK_MSKDAT3_Pos (3) |
BPWM_T::MSK: MSKDAT3 Position
Definition at line 1356 of file bpwm_reg.h.
| #define BPWM_MSK_MSKDAT4_Msk (0x1ul << BPWM_MSK_MSKDAT4_Pos) |
BPWM_T::MSK: MSKDAT4 Mask
Definition at line 1360 of file bpwm_reg.h.
| #define BPWM_MSK_MSKDAT4_Pos (4) |
BPWM_T::MSK: MSKDAT4 Position
Definition at line 1359 of file bpwm_reg.h.
| #define BPWM_MSK_MSKDAT5_Msk (0x1ul << BPWM_MSK_MSKDAT5_Pos) |
BPWM_T::MSK: MSKDAT5 Mask
Definition at line 1363 of file bpwm_reg.h.
| #define BPWM_MSK_MSKDAT5_Pos (5) |
BPWM_T::MSK: MSKDAT5 Position
Definition at line 1362 of file bpwm_reg.h.
| #define BPWM_MSK_MSKDATn_Msk (0x3ful << BPWM_MSK_MSKDATn_Pos) |
BPWM_T::MSK: MSKDATn Mask
Definition at line 1366 of file bpwm_reg.h.
| #define BPWM_MSK_MSKDATn_Pos (0) |
BPWM_T::MSK: MSKDATn Position
Definition at line 1365 of file bpwm_reg.h.
| #define BPWM_MSKEN_MSKEN0_Msk (0x1ul << BPWM_MSKEN_MSKEN0_Pos) |
BPWM_T::MSKEN: MSKEN0 Mask
Definition at line 1327 of file bpwm_reg.h.
| #define BPWM_MSKEN_MSKEN0_Pos (0) |
BPWM_T::MSKEN: MSKEN0 Position
Definition at line 1326 of file bpwm_reg.h.
| #define BPWM_MSKEN_MSKEN1_Msk (0x1ul << BPWM_MSKEN_MSKEN1_Pos) |
BPWM_T::MSKEN: MSKEN1 Mask
Definition at line 1330 of file bpwm_reg.h.
| #define BPWM_MSKEN_MSKEN1_Pos (1) |
BPWM_T::MSKEN: MSKEN1 Position
Definition at line 1329 of file bpwm_reg.h.
| #define BPWM_MSKEN_MSKEN2_Msk (0x1ul << BPWM_MSKEN_MSKEN2_Pos) |
BPWM_T::MSKEN: MSKEN2 Mask
Definition at line 1333 of file bpwm_reg.h.
| #define BPWM_MSKEN_MSKEN2_Pos (2) |
BPWM_T::MSKEN: MSKEN2 Position
Definition at line 1332 of file bpwm_reg.h.
| #define BPWM_MSKEN_MSKEN3_Msk (0x1ul << BPWM_MSKEN_MSKEN3_Pos) |
BPWM_T::MSKEN: MSKEN3 Mask
Definition at line 1336 of file bpwm_reg.h.
| #define BPWM_MSKEN_MSKEN3_Pos (3) |
BPWM_T::MSKEN: MSKEN3 Position
Definition at line 1335 of file bpwm_reg.h.
| #define BPWM_MSKEN_MSKEN4_Msk (0x1ul << BPWM_MSKEN_MSKEN4_Pos) |
BPWM_T::MSKEN: MSKEN4 Mask
Definition at line 1339 of file bpwm_reg.h.
| #define BPWM_MSKEN_MSKEN4_Pos (4) |
BPWM_T::MSKEN: MSKEN4 Position
Definition at line 1338 of file bpwm_reg.h.
| #define BPWM_MSKEN_MSKEN5_Msk (0x1ul << BPWM_MSKEN_MSKEN5_Pos) |
BPWM_T::MSKEN: MSKEN5 Mask
Definition at line 1342 of file bpwm_reg.h.
| #define BPWM_MSKEN_MSKEN5_Pos (5) |
BPWM_T::MSKEN: MSKEN5 Position
Definition at line 1341 of file bpwm_reg.h.
| #define BPWM_MSKEN_MSKENn_Msk (0x3ful << BPWM_MSKEN_MSKENn_Pos) |
BPWM_T::MSKEN: MSKENn Mask
Definition at line 1345 of file bpwm_reg.h.
| #define BPWM_MSKEN_MSKENn_Pos (0) |
BPWM_T::MSKEN: MSKENn Position
Definition at line 1344 of file bpwm_reg.h.
| #define BPWM_PBUF_PBUF_Msk (0xfffful << BPWM_PBUF_PBUF_Pos) |
BPWM_T::PBUF: PBUF Mask
Definition at line 1807 of file bpwm_reg.h.
| #define BPWM_PBUF_PBUF_Pos (0) |
BPWM_T::PBUF: PBUF Position
Definition at line 1806 of file bpwm_reg.h.
| #define BPWM_PERIOD_PERIOD_Msk (0xfffful << BPWM_PERIOD_PERIOD_Pos) |
BPWM_T::PERIOD: PERIOD Mask
Definition at line 1216 of file bpwm_reg.h.
| #define BPWM_PERIOD_PERIOD_Pos (0) |
BPWM_T::PERIOD: PERIOD Position
Definition at line 1215 of file bpwm_reg.h.
| #define BPWM_POEN_POEN0_Msk (0x1ul << BPWM_POEN_POEN0_Pos) |
BPWM_T::POEN: POEN0 Mask
Definition at line 1390 of file bpwm_reg.h.
| #define BPWM_POEN_POEN0_Pos (0) |
BPWM_T::POEN: POEN0 Position
Definition at line 1389 of file bpwm_reg.h.
| #define BPWM_POEN_POEN1_Msk (0x1ul << BPWM_POEN_POEN1_Pos) |
BPWM_T::POEN: POEN1 Mask
Definition at line 1393 of file bpwm_reg.h.
| #define BPWM_POEN_POEN1_Pos (1) |
BPWM_T::POEN: POEN1 Position
Definition at line 1392 of file bpwm_reg.h.
| #define BPWM_POEN_POEN2_Msk (0x1ul << BPWM_POEN_POEN2_Pos) |
BPWM_T::POEN: POEN2 Mask
Definition at line 1396 of file bpwm_reg.h.
| #define BPWM_POEN_POEN2_Pos (2) |
BPWM_T::POEN: POEN2 Position
Definition at line 1395 of file bpwm_reg.h.
| #define BPWM_POEN_POEN3_Msk (0x1ul << BPWM_POEN_POEN3_Pos) |
BPWM_T::POEN: POEN3 Mask
Definition at line 1399 of file bpwm_reg.h.
| #define BPWM_POEN_POEN3_Pos (3) |
BPWM_T::POEN: POEN3 Position
Definition at line 1398 of file bpwm_reg.h.
| #define BPWM_POEN_POEN4_Msk (0x1ul << BPWM_POEN_POEN4_Pos) |
BPWM_T::POEN: POEN4 Mask
Definition at line 1402 of file bpwm_reg.h.
| #define BPWM_POEN_POEN4_Pos (4) |
BPWM_T::POEN: POEN4 Position
Definition at line 1401 of file bpwm_reg.h.
| #define BPWM_POEN_POEN5_Msk (0x1ul << BPWM_POEN_POEN5_Pos) |
BPWM_T::POEN: POEN5 Mask
Definition at line 1405 of file bpwm_reg.h.
| #define BPWM_POEN_POEN5_Pos (5) |
BPWM_T::POEN: POEN5 Position
Definition at line 1404 of file bpwm_reg.h.
| #define BPWM_POEN_POENn_Msk (0x3ful << BPWM_POEN_POENn_Pos) |
BPWM_T::POEN: POENn Mask
Definition at line 1408 of file bpwm_reg.h.
| #define BPWM_POEN_POENn_Pos (0) |
BPWM_T::POEN: POENn Position
Definition at line 1407 of file bpwm_reg.h.
| #define BPWM_POLCTL_PINV0_Msk (0x1ul << BPWM_POLCTL_PINV0_Pos) |
BPWM_T::POLCTL: PINV0 Mask
Definition at line 1369 of file bpwm_reg.h.
| #define BPWM_POLCTL_PINV0_Pos (0) |
BPWM_T::POLCTL: PINV0 Position
Definition at line 1368 of file bpwm_reg.h.
| #define BPWM_POLCTL_PINV1_Msk (0x1ul << BPWM_POLCTL_PINV1_Pos) |
BPWM_T::POLCTL: PINV1 Mask
Definition at line 1372 of file bpwm_reg.h.
| #define BPWM_POLCTL_PINV1_Pos (1) |
BPWM_T::POLCTL: PINV1 Position
Definition at line 1371 of file bpwm_reg.h.
| #define BPWM_POLCTL_PINV2_Msk (0x1ul << BPWM_POLCTL_PINV2_Pos) |
BPWM_T::POLCTL: PINV2 Mask
Definition at line 1375 of file bpwm_reg.h.
| #define BPWM_POLCTL_PINV2_Pos (2) |
BPWM_T::POLCTL: PINV2 Position
Definition at line 1374 of file bpwm_reg.h.
| #define BPWM_POLCTL_PINV3_Msk (0x1ul << BPWM_POLCTL_PINV3_Pos) |
BPWM_T::POLCTL: PINV3 Mask
Definition at line 1378 of file bpwm_reg.h.
| #define BPWM_POLCTL_PINV3_Pos (3) |
BPWM_T::POLCTL: PINV3 Position
Definition at line 1377 of file bpwm_reg.h.
| #define BPWM_POLCTL_PINV4_Msk (0x1ul << BPWM_POLCTL_PINV4_Pos) |
BPWM_T::POLCTL: PINV4 Mask
Definition at line 1381 of file bpwm_reg.h.
| #define BPWM_POLCTL_PINV4_Pos (4) |
BPWM_T::POLCTL: PINV4 Position
Definition at line 1380 of file bpwm_reg.h.
| #define BPWM_POLCTL_PINV5_Msk (0x1ul << BPWM_POLCTL_PINV5_Pos) |
BPWM_T::POLCTL: PINV5 Mask
Definition at line 1384 of file bpwm_reg.h.
| #define BPWM_POLCTL_PINV5_Pos (5) |
BPWM_T::POLCTL: PINV5 Position
Definition at line 1383 of file bpwm_reg.h.
| #define BPWM_POLCTL_PINVn_Msk (0x3ful << BPWM_POLCTL_PINVn_Pos) |
BPWM_T::POLCTL: PINVn Mask
Definition at line 1387 of file bpwm_reg.h.
| #define BPWM_POLCTL_PINVn_Pos (0) |
BPWM_T::POLCTL: PINVn Position
Definition at line 1386 of file bpwm_reg.h.
| #define BPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT0_RCAPDAT_Pos) |
BPWM_T::RCAPDAT0: RCAPDAT Mask
Definition at line 1723 of file bpwm_reg.h.
| #define BPWM_RCAPDAT0_RCAPDAT_Pos (0) |
BPWM_T::RCAPDAT0: RCAPDAT Position
Definition at line 1722 of file bpwm_reg.h.
| #define BPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT1_RCAPDAT_Pos) |
BPWM_T::RCAPDAT1: RCAPDAT Mask
Definition at line 1729 of file bpwm_reg.h.
| #define BPWM_RCAPDAT1_RCAPDAT_Pos (0) |
BPWM_T::RCAPDAT1: RCAPDAT Position
Definition at line 1728 of file bpwm_reg.h.
| #define BPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT2_RCAPDAT_Pos) |
BPWM_T::RCAPDAT2: RCAPDAT Mask
Definition at line 1735 of file bpwm_reg.h.
| #define BPWM_RCAPDAT2_RCAPDAT_Pos (0) |
BPWM_T::RCAPDAT2: RCAPDAT Position
Definition at line 1734 of file bpwm_reg.h.
| #define BPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT3_RCAPDAT_Pos) |
BPWM_T::RCAPDAT3: RCAPDAT Mask
Definition at line 1741 of file bpwm_reg.h.
| #define BPWM_RCAPDAT3_RCAPDAT_Pos (0) |
BPWM_T::RCAPDAT3: RCAPDAT Position
Definition at line 1740 of file bpwm_reg.h.
| #define BPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT4_RCAPDAT_Pos) |
BPWM_T::RCAPDAT4: RCAPDAT Mask
Definition at line 1747 of file bpwm_reg.h.
| #define BPWM_RCAPDAT4_RCAPDAT_Pos (0) |
BPWM_T::RCAPDAT4: RCAPDAT Position
Definition at line 1746 of file bpwm_reg.h.
| #define BPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << BPWM_RCAPDAT5_RCAPDAT_Pos) |
BPWM_T::RCAPDAT5: RCAPDAT Mask
Definition at line 1753 of file bpwm_reg.h.
| #define BPWM_RCAPDAT5_RCAPDAT_Pos (0) |
BPWM_T::RCAPDAT5: RCAPDAT Position
Definition at line 1752 of file bpwm_reg.h.
| #define BPWM_SSCTL_SSEN0_Msk (0x1ul << BPWM_SSCTL_SSEN0_Pos) |
BPWM_T::SSCTL: SSEN0 Mask
Definition at line 1543 of file bpwm_reg.h.
| #define BPWM_SSCTL_SSEN0_Pos (0) |
BPWM_T::SSCTL: SSEN0 Position
Definition at line 1542 of file bpwm_reg.h.
| #define BPWM_SSCTL_SSRC_Msk (0x3ul << BPWM_SSCTL_SSRC_Pos) |
BPWM_T::SSCTL: SSRC Mask
Definition at line 1546 of file bpwm_reg.h.
| #define BPWM_SSCTL_SSRC_Pos (8) |
BPWM_T::SSCTL: SSRC Position
Definition at line 1545 of file bpwm_reg.h.
| #define BPWM_SSTRG_CNTSEN_Msk (0x1ul << BPWM_SSTRG_CNTSEN_Pos) |
BPWM_T::SSTRG: CNTSEN Mask
Definition at line 1549 of file bpwm_reg.h.
| #define BPWM_SSTRG_CNTSEN_Pos (0) |
BPWM_T::SSTRG: CNTSEN Position
Definition at line 1548 of file bpwm_reg.h.
| #define BPWM_STATUS_CNTMAX0_Msk (0x1ul << BPWM_STATUS_CNTMAX0_Pos) |
BPWM_T::STATUS: CNTMAX0 Mask
Definition at line 1552 of file bpwm_reg.h.
| #define BPWM_STATUS_CNTMAX0_Pos (0) |
BPWM_T::STATUS: CNTMAX0 Position
Definition at line 1551 of file bpwm_reg.h.
| #define BPWM_STATUS_EADCTRG0_Msk (0x1ul << BPWM_STATUS_EADCTRG0_Pos) |
BPWM_T::STATUS: EADCTRG0 Mask
Definition at line 1555 of file bpwm_reg.h.
| #define BPWM_STATUS_EADCTRG0_Pos (16) |
BPWM_T::STATUS: EADCTRG0 Position
Definition at line 1554 of file bpwm_reg.h.
| #define BPWM_STATUS_EADCTRG1_Msk (0x1ul << BPWM_STATUS_EADCTRG1_Pos) |
BPWM_T::STATUS: EADCTRG1 Mask
Definition at line 1558 of file bpwm_reg.h.
| #define BPWM_STATUS_EADCTRG1_Pos (17) |
BPWM_T::STATUS: EADCTRG1 Position
Definition at line 1557 of file bpwm_reg.h.
| #define BPWM_STATUS_EADCTRG2_Msk (0x1ul << BPWM_STATUS_EADCTRG2_Pos) |
BPWM_T::STATUS: EADCTRG2 Mask
Definition at line 1561 of file bpwm_reg.h.
| #define BPWM_STATUS_EADCTRG2_Pos (18) |
BPWM_T::STATUS: EADCTRG2 Position
Definition at line 1560 of file bpwm_reg.h.
| #define BPWM_STATUS_EADCTRG3_Msk (0x1ul << BPWM_STATUS_EADCTRG3_Pos) |
BPWM_T::STATUS: EADCTRG3 Mask
Definition at line 1564 of file bpwm_reg.h.
| #define BPWM_STATUS_EADCTRG3_Pos (19) |
BPWM_T::STATUS: EADCTRG3 Position
Definition at line 1563 of file bpwm_reg.h.
| #define BPWM_STATUS_EADCTRG4_Msk (0x1ul << BPWM_STATUS_EADCTRG4_Pos) |
BPWM_T::STATUS: EADCTRG4 Mask
Definition at line 1567 of file bpwm_reg.h.
| #define BPWM_STATUS_EADCTRG4_Pos (20) |
BPWM_T::STATUS: EADCTRG4 Position
Definition at line 1566 of file bpwm_reg.h.
| #define BPWM_STATUS_EADCTRG5_Msk (0x1ul << BPWM_STATUS_EADCTRG5_Pos) |
BPWM_T::STATUS: EADCTRG5 Mask
Definition at line 1570 of file bpwm_reg.h.
| #define BPWM_STATUS_EADCTRG5_Pos (21) |
BPWM_T::STATUS: EADCTRG5 Position
Definition at line 1569 of file bpwm_reg.h.
| #define BPWM_STATUS_EADCTRGn_Msk (0x3ful << BPWM_STATUS_EADCTRGn_Pos) |
BPWM_T::STATUS: EADCTRGn Mask
Definition at line 1573 of file bpwm_reg.h.
| #define BPWM_STATUS_EADCTRGn_Pos (16) |
BPWM_T::STATUS: EADCTRGn Position
Definition at line 1572 of file bpwm_reg.h.
| #define BPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL0_Pos) |
BPWM_T::WGCTL0: PRDPCTL0 Mask
Definition at line 1264 of file bpwm_reg.h.
| #define BPWM_WGCTL0_PRDPCTL0_Pos (16) |
BPWM_T::WGCTL0: PRDPCTL0 Position
Definition at line 1263 of file bpwm_reg.h.
| #define BPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL1_Pos) |
BPWM_T::WGCTL0: PRDPCTL1 Mask
Definition at line 1267 of file bpwm_reg.h.
| #define BPWM_WGCTL0_PRDPCTL1_Pos (18) |
BPWM_T::WGCTL0: PRDPCTL1 Position
Definition at line 1266 of file bpwm_reg.h.
| #define BPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL2_Pos) |
BPWM_T::WGCTL0: PRDPCTL2 Mask
Definition at line 1270 of file bpwm_reg.h.
| #define BPWM_WGCTL0_PRDPCTL2_Pos (20) |
BPWM_T::WGCTL0: PRDPCTL2 Position
Definition at line 1269 of file bpwm_reg.h.
| #define BPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL3_Pos) |
BPWM_T::WGCTL0: PRDPCTL3 Mask
Definition at line 1273 of file bpwm_reg.h.
| #define BPWM_WGCTL0_PRDPCTL3_Pos (22) |
BPWM_T::WGCTL0: PRDPCTL3 Position
Definition at line 1272 of file bpwm_reg.h.
| #define BPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL4_Pos) |
BPWM_T::WGCTL0: PRDPCTL4 Mask
Definition at line 1276 of file bpwm_reg.h.
| #define BPWM_WGCTL0_PRDPCTL4_Pos (24) |
BPWM_T::WGCTL0: PRDPCTL4 Position
Definition at line 1275 of file bpwm_reg.h.
| #define BPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << BPWM_WGCTL0_PRDPCTL5_Pos) |
BPWM_T::WGCTL0: PRDPCTL5 Mask
Definition at line 1279 of file bpwm_reg.h.
| #define BPWM_WGCTL0_PRDPCTL5_Pos (26) |
BPWM_T::WGCTL0: PRDPCTL5 Position
Definition at line 1278 of file bpwm_reg.h.
| #define BPWM_WGCTL0_PRDPCTLn_Msk (0xffful << BPWM_WGCTL0_PRDPCTLn_Pos) |
BPWM_T::WGCTL0: PRDPCTLn Mask
Definition at line 1282 of file bpwm_reg.h.
| #define BPWM_WGCTL0_PRDPCTLn_Pos (16) |
BPWM_T::WGCTL0: PRDPCTLn Position
Definition at line 1281 of file bpwm_reg.h.
| #define BPWM_WGCTL0_ZPCTL0_Msk (0x3ul << BPWM_WGCTL0_ZPCTL0_Pos) |
BPWM_T::WGCTL0: ZPCTL0 Mask
Definition at line 1243 of file bpwm_reg.h.
| #define BPWM_WGCTL0_ZPCTL0_Pos (0) |
BPWM_T::WGCTL0: ZPCTL0 Position
Definition at line 1242 of file bpwm_reg.h.
| #define BPWM_WGCTL0_ZPCTL1_Msk (0x3ul << BPWM_WGCTL0_ZPCTL1_Pos) |
BPWM_T::WGCTL0: ZPCTL1 Mask
Definition at line 1246 of file bpwm_reg.h.
| #define BPWM_WGCTL0_ZPCTL1_Pos (2) |
BPWM_T::WGCTL0: ZPCTL1 Position
Definition at line 1245 of file bpwm_reg.h.
| #define BPWM_WGCTL0_ZPCTL2_Msk (0x3ul << BPWM_WGCTL0_ZPCTL2_Pos) |
BPWM_T::WGCTL0: ZPCTL2 Mask
Definition at line 1249 of file bpwm_reg.h.
| #define BPWM_WGCTL0_ZPCTL2_Pos (4) |
BPWM_T::WGCTL0: ZPCTL2 Position
Definition at line 1248 of file bpwm_reg.h.
| #define BPWM_WGCTL0_ZPCTL3_Msk (0x3ul << BPWM_WGCTL0_ZPCTL3_Pos) |
BPWM_T::WGCTL0: ZPCTL3 Mask
Definition at line 1252 of file bpwm_reg.h.
| #define BPWM_WGCTL0_ZPCTL3_Pos (6) |
BPWM_T::WGCTL0: ZPCTL3 Position
Definition at line 1251 of file bpwm_reg.h.
| #define BPWM_WGCTL0_ZPCTL4_Msk (0x3ul << BPWM_WGCTL0_ZPCTL4_Pos) |
BPWM_T::WGCTL0: ZPCTL4 Mask
Definition at line 1255 of file bpwm_reg.h.
| #define BPWM_WGCTL0_ZPCTL4_Pos (8) |
BPWM_T::WGCTL0: ZPCTL4 Position
Definition at line 1254 of file bpwm_reg.h.
| #define BPWM_WGCTL0_ZPCTL5_Msk (0x3ul << BPWM_WGCTL0_ZPCTL5_Pos) |
BPWM_T::WGCTL0: ZPCTL5 Mask
Definition at line 1258 of file bpwm_reg.h.
| #define BPWM_WGCTL0_ZPCTL5_Pos (10) |
BPWM_T::WGCTL0: ZPCTL5 Position
Definition at line 1257 of file bpwm_reg.h.
| #define BPWM_WGCTL0_ZPCTLn_Msk (0xffful << BPWM_WGCTL0_ZPCTLn_Pos) |
BPWM_T::WGCTL0: ZPCTLn Mask
Definition at line 1261 of file bpwm_reg.h.
| #define BPWM_WGCTL0_ZPCTLn_Pos (0) |
BPWM_T::WGCTL0: ZPCTLn Position
Definition at line 1260 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL0_Pos) |
BPWM_T::WGCTL1: CMPDCTL0 Mask
Definition at line 1306 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPDCTL0_Pos (16) |
BPWM_T::WGCTL1: CMPDCTL0 Position
Definition at line 1305 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL1_Pos) |
BPWM_T::WGCTL1: CMPDCTL1 Mask
Definition at line 1309 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPDCTL1_Pos (18) |
BPWM_T::WGCTL1: CMPDCTL1 Position
Definition at line 1308 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL2_Pos) |
BPWM_T::WGCTL1: CMPDCTL2 Mask
Definition at line 1312 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPDCTL2_Pos (20) |
BPWM_T::WGCTL1: CMPDCTL2 Position
Definition at line 1311 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL3_Pos) |
BPWM_T::WGCTL1: CMPDCTL3 Mask
Definition at line 1315 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPDCTL3_Pos (22) |
BPWM_T::WGCTL1: CMPDCTL3 Position
Definition at line 1314 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL4_Pos) |
BPWM_T::WGCTL1: CMPDCTL4 Mask
Definition at line 1318 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPDCTL4_Pos (24) |
BPWM_T::WGCTL1: CMPDCTL4 Position
Definition at line 1317 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPDCTL5_Pos) |
BPWM_T::WGCTL1: CMPDCTL5 Mask
Definition at line 1321 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPDCTL5_Pos (26) |
BPWM_T::WGCTL1: CMPDCTL5 Position
Definition at line 1320 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPDCTLn_Msk (0xffful << BPWM_WGCTL1_CMPDCTLn_Pos) |
BPWM_T::WGCTL1: CMPDCTLn Mask
Definition at line 1324 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPDCTLn_Pos (16) |
BPWM_T::WGCTL1: CMPDCTLn Position
Definition at line 1323 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL0_Pos) |
BPWM_T::WGCTL1: CMPUCTL0 Mask
Definition at line 1285 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPUCTL0_Pos (0) |
BPWM_T::WGCTL1: CMPUCTL0 Position
Definition at line 1284 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL1_Pos) |
BPWM_T::WGCTL1: CMPUCTL1 Mask
Definition at line 1288 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPUCTL1_Pos (2) |
BPWM_T::WGCTL1: CMPUCTL1 Position
Definition at line 1287 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL2_Pos) |
BPWM_T::WGCTL1: CMPUCTL2 Mask
Definition at line 1291 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPUCTL2_Pos (4) |
BPWM_T::WGCTL1: CMPUCTL2 Position
Definition at line 1290 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL3_Pos) |
BPWM_T::WGCTL1: CMPUCTL3 Mask
Definition at line 1294 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPUCTL3_Pos (6) |
BPWM_T::WGCTL1: CMPUCTL3 Position
Definition at line 1293 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL4_Pos) |
BPWM_T::WGCTL1: CMPUCTL4 Mask
Definition at line 1297 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPUCTL4_Pos (8) |
BPWM_T::WGCTL1: CMPUCTL4 Position
Definition at line 1296 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << BPWM_WGCTL1_CMPUCTL5_Pos) |
BPWM_T::WGCTL1: CMPUCTL5 Mask
Definition at line 1300 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPUCTL5_Pos (10) |
BPWM_T::WGCTL1: CMPUCTL5 Position
Definition at line 1299 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPUCTLn_Msk (0xffful << BPWM_WGCTL1_CMPUCTLn_Pos) |
BPWM_T::WGCTL1: CMPUCTLn Mask
Definition at line 1303 of file bpwm_reg.h.
| #define BPWM_WGCTL1_CMPUCTLn_Pos (0) |
BPWM_T::WGCTL1: CMPUCTLn Position
Definition at line 1302 of file bpwm_reg.h.
| #define CAN_BRPE_BRPE_Msk (0xful << CAN_BRPE_BRPE_Pos) |
CAN_T::BRPE: BRPE Mask
| #define CAN_BRPE_BRPE_Pos (0) |
CAN_T::BRPE: BRPE Position
| #define CAN_BTIME_BRP_Msk (0x3ful << CAN_BTIME_BRP_Pos) |
CAN_T::BTIME: BRP Mask
| #define CAN_BTIME_BRP_Pos (0) |
CAN_T::BTIME: BRP Position
| #define CAN_BTIME_SJW_Msk (0x3ul << CAN_BTIME_SJW_Pos) |
CAN_T::BTIME: SJW Mask
| #define CAN_BTIME_SJW_Pos (6) |
CAN_T::BTIME: SJW Position
| #define CAN_BTIME_TSEG1_Msk (0xful << CAN_BTIME_TSEG1_Pos) |
CAN_T::BTIME: TSeg1 Mask
| #define CAN_BTIME_TSEG1_Pos (8) |
CAN_T::BTIME: TSeg1 Position
| #define CAN_BTIME_TSEG2_Msk (0x7ul << CAN_BTIME_TSEG2_Pos) |
CAN_T::BTIME: TSeg2 Mask
| #define CAN_BTIME_TSEG2_Pos (12) |
CAN_T::BTIME: TSeg2 Position
| #define CAN_CON_CCE_Msk (0x1ul << CAN_CON_CCE_Pos) |
CAN_T::CON: CCE Mask
| #define CAN_CON_CCE_Pos (6) |
CAN_T::CON: CCE Position
| #define CAN_CON_DAR_Msk (0x1ul << CAN_CON_DAR_Pos) |
CAN_T::CON: DAR Mask
| #define CAN_CON_DAR_Pos (5) |
CAN_T::CON: DAR Position
| #define CAN_CON_EIE_Msk (0x1ul << CAN_CON_EIE_Pos) |
CAN_T::CON: EIE Mask
| #define CAN_CON_EIE_Pos (3) |
CAN_T::CON: EIE Position
| #define CAN_CON_IE_Msk (0x1ul << CAN_CON_IE_Pos) |
CAN_T::CON: IE Mask
| #define CAN_CON_IE_Pos (1) |
CAN_T::CON: IE Position
| #define CAN_CON_INIT_Msk (0x1ul << CAN_CON_INIT_Pos) |
CAN_T::CON: Init Mask
| #define CAN_CON_INIT_Pos (0) |
@addtogroup CAN_CONST CAN Bit Field Definition Constant Definitions for CAN Controller
CAN_T::CON: Init Position
| #define CAN_CON_SIE_Msk (0x1ul << CAN_CON_SIE_Pos) |
CAN_T::CON: SIE Mask
| #define CAN_CON_SIE_Pos (2) |
CAN_T::CON: SIE Position
| #define CAN_CON_TEST_Msk (0x1ul << CAN_CON_TEST_Pos) |
CAN_T::CON: Test Mask
| #define CAN_CON_TEST_Pos (7) |
CAN_T::CON: Test Position
| #define CAN_ERR_REC_Msk (0x7ful << CAN_ERR_REC_Pos) |
CAN_T::ERR: REC Mask
| #define CAN_ERR_REC_Pos (8) |
CAN_T::ERR: REC Position
| #define CAN_ERR_RP_Msk (0x1ul << CAN_ERR_RP_Pos) |
CAN_T::ERR: RP Mask
| #define CAN_ERR_RP_Pos (15) |
CAN_T::ERR: RP Position
| #define CAN_ERR_TEC_Msk (0xfful << CAN_ERR_TEC_Pos) |
CAN_T::ERR: TEC Mask
| #define CAN_ERR_TEC_Pos (0) |
CAN_T::ERR: TEC Position
| #define CAN_IF_ARB1_ID_Msk (0xfffful << CAN_IF_ARB1_ID_Pos) |
CAN_IF_T::ARB1: ID Mask
| #define CAN_IF_ARB1_ID_Pos (0) |
CAN_IF_T::ARB1: ID Position
| #define CAN_IF_ARB2_DIR_Msk (0x1ul << CAN_IF_ARB2_DIR_Pos) |
CAN_IF_T::ARB2: Dir Mask
| #define CAN_IF_ARB2_DIR_Pos (13) |
CAN_IF_T::ARB2: Dir Position
| #define CAN_IF_ARB2_ID_Msk (0x1ffful << CAN_IF_ARB2_ID_Pos) |
CAN_IF_T::ARB2: ID Mask
| #define CAN_IF_ARB2_ID_Pos (0) |
CAN_IF_T::ARB2: ID Position
| #define CAN_IF_ARB2_MSGVAL_Msk (0x1ul << CAN_IF_ARB2_MSGVAL_Pos) |
CAN_IF_T::ARB2: MsgVal Mask
| #define CAN_IF_ARB2_MSGVAL_Pos (15) |
CAN_IF_T::ARB2: MsgVal Position
| #define CAN_IF_ARB2_XTD_Msk (0x1ul << CAN_IF_ARB2_XTD_Pos) |
CAN_IF_T::ARB2: Xtd Mask
| #define CAN_IF_ARB2_XTD_Pos (14) |
CAN_IF_T::ARB2: Xtd Position
| #define CAN_IF_CMASK_ARB_Msk (0x1ul << CAN_IF_CMASK_ARB_Pos) |
CAN_IF_T::CMASK: Arb Mask
| #define CAN_IF_CMASK_ARB_Pos (5) |
CAN_IF_T::CMASK: Arb Position
| #define CAN_IF_CMASK_CLRINTPND_Msk (0x1ul << CAN_IF_CMASK_CLRINTPND_Pos) |
CAN_IF_T::CMASK: ClrIntPnd Mask
| #define CAN_IF_CMASK_CLRINTPND_Pos (3) |
CAN_IF_T::CMASK: ClrIntPnd Position
| #define CAN_IF_CMASK_CONTROL_Msk (0x1ul << CAN_IF_CMASK_CONTROL_Pos) |
CAN_IF_T::CMASK: Control Mask
| #define CAN_IF_CMASK_CONTROL_Pos (4) |
CAN_IF_T::CMASK: Control Position
| #define CAN_IF_CMASK_DATAA_Msk (0x1ul << CAN_IF_CMASK_DATAA_Pos) |
CAN_IF_T::CMASK: DAT_A Mask
| #define CAN_IF_CMASK_DATAA_Pos (1) |
CAN_IF_T::CMASK: DAT_A Position
| #define CAN_IF_CMASK_DATAB_Msk (0x1ul << CAN_IF_CMASK_DATAB_Pos) |
CAN_IF_T::CMASK: DAT_B Mask
| #define CAN_IF_CMASK_DATAB_Pos (0) |
CAN_IF_T::CMASK: DAT_B Position
| #define CAN_IF_CMASK_MASK_Msk (0x1ul << CAN_IF_CMASK_MASK_Pos) |
CAN_IF_T::CMASK: Mask Mask
| #define CAN_IF_CMASK_MASK_Pos (6) |
CAN_IF_T::CMASK: Mask Position
| #define CAN_IF_CMASK_TXRQSTNEWDAT_Msk (0x1ul << CAN_IF_CMASK_TXRQSTNEWDAT_Pos) |
CAN_IF_T::CMASK: TxRqst_NewDat Mask
| #define CAN_IF_CMASK_TXRQSTNEWDAT_Pos (2) |
CAN_IF_T::CMASK: TxRqst_NewDat Position
| #define CAN_IF_CMASK_WRRD_Msk (0x1ul << CAN_IF_CMASK_WRRD_Pos) |
CAN_IF_T::CMASK: WR_RD Mask
| #define CAN_IF_CMASK_WRRD_Pos (7) |
CAN_IF_T::CMASK: WR_RD Position
| #define CAN_IF_CREQ_BUSY_Msk (0x1ul << CAN_IF_CREQ_BUSY_Pos) |
CAN_IF_T::CREQ: Busy Mask
| #define CAN_IF_CREQ_BUSY_Pos (15) |
CAN_IF_T::CREQ: Busy Position
| #define CAN_IF_CREQ_MSGNUM_Msk (0x3ful << CAN_IF_CREQ_MSGNUM_Pos) |
CAN_IF_T::CREQ: MessageNumber Mask
| #define CAN_IF_CREQ_MSGNUM_Pos (0) |
CAN_IF_T::CREQ: MessageNumber Position
| #define CAN_IF_DAT_A1_DATA0_Msk (0xfful << CAN_IF_DAT_A1_DATA0_Pos) |
CAN_IF_T::DAT_A1: Data_0_ Mask
| #define CAN_IF_DAT_A1_DATA0_Pos (0) |
CAN_IF_T::DAT_A1: Data_0_ Position
| #define CAN_IF_DAT_A1_DATA1_Msk (0xfful << CAN_IF_DAT_A1_DATA1_Pos) |
CAN_IF_T::DAT_A1: Data_1_ Mask
| #define CAN_IF_DAT_A1_DATA1_Pos (8) |
CAN_IF_T::DAT_A1: Data_1_ Position
| #define CAN_IF_DAT_A2_DATA2_Msk (0xfful << CAN_IF_DAT_A2_DATA2_Pos) |
CAN_IF_T::DAT_A2: Data_2_ Mask
| #define CAN_IF_DAT_A2_DATA2_Pos (0) |
CAN_IF_T::DAT_A2: Data_2_ Position
| #define CAN_IF_DAT_A2_DATA3_Msk (0xfful << CAN_IF_DAT_A2_DATA3_Pos) |
CAN_IF_T::DAT_A2: Data_3_ Mask
| #define CAN_IF_DAT_A2_DATA3_Pos (8) |
CAN_IF_T::DAT_A2: Data_3_ Position
| #define CAN_IF_DAT_B1_DATA4_Msk (0xfful << CAN_IF_DAT_B1_DATA4_Pos) |
CAN_IF_T::DAT_B1: Data_4_ Mask
| #define CAN_IF_DAT_B1_DATA4_Pos (0) |
CAN_IF_T::DAT_B1: Data_4_ Position
| #define CAN_IF_DAT_B1_DATA5_Msk (0xfful << CAN_IF_DAT_B1_DATA5_Pos) |
CAN_IF_T::DAT_B1: Data_5_ Mask
| #define CAN_IF_DAT_B1_DATA5_Pos (8) |
CAN_IF_T::DAT_B1: Data_5_ Position
| #define CAN_IF_DAT_B2_DATA6_Msk (0xfful << CAN_IF_DAT_B2_DATA6_Pos) |
CAN_IF_T::DAT_B2: Data_6_ Mask
| #define CAN_IF_DAT_B2_DATA6_Pos (0) |
CAN_IF_T::DAT_B2: Data_6_ Position
| #define CAN_IF_DAT_B2_DATA7_Msk (0xfful << CAN_IF_DAT_B2_DATA7_Pos) |
CAN_IF_T::DAT_B2: Data_7_ Mask
| #define CAN_IF_DAT_B2_DATA7_Pos (8) |
CAN_IF_T::DAT_B2: Data_7_ Position
| #define CAN_IF_MASK1_Msk_Msk (0xfffful << CAN_IF_MASK1_Msk_Pos) |
CAN_IF_T::MASK1: Msk Mask
| #define CAN_IF_MASK1_Msk_Pos (0) |
CAN_IF_T::MASK1: Msk Position
| #define CAN_IF_MASK2_MDIR_Msk (0x1ul << CAN_IF_MASK2_MDIR_Pos) |
CAN_IF_T::MASK2: MDir Mask
| #define CAN_IF_MASK2_MDIR_Pos (14) |
CAN_IF_T::MASK2: MDir Position
| #define CAN_IF_MASK2_Msk_Msk (0x1ffful << CAN_IF_MASK2_Msk_Pos) |
CAN_IF_T::MASK2: Msk Mask
| #define CAN_IF_MASK2_Msk_Pos (0) |
CAN_IF_T::MASK2: Msk Position
| #define CAN_IF_MASK2_MXTD_Msk (0x1ul << CAN_IF_MASK2_MXTD_Pos) |
CAN_IF_T::MASK2: MXtd Mask
| #define CAN_IF_MASK2_MXTD_Pos (15) |
CAN_IF_T::MASK2: MXtd Position
| #define CAN_IF_MCON_DLC_Msk (0xful << CAN_IF_MCON_DLC_Pos) |
CAN_IF_T::MCON: DLC Mask
| #define CAN_IF_MCON_DLC_Pos (0) |
CAN_IF_T::MCON: DLC Position
| #define CAN_IF_MCON_EOB_Msk (0x1ul << CAN_IF_MCON_EOB_Pos) |
CAN_IF_T::MCON: EoB Mask
| #define CAN_IF_MCON_EOB_Pos (7) |
CAN_IF_T::MCON: EoB Position
| #define CAN_IF_MCON_IntPnd_Msk (0x1ul << CAN_IF_MCON_IntPnd_Pos) |
CAN_IF_T::MCON: IntPnd Mask
| #define CAN_IF_MCON_IntPnd_Pos (13) |
CAN_IF_T::MCON: IntPnd Position
| #define CAN_IF_MCON_MsgLst_Msk (0x1ul << CAN_IF_MCON_MsgLst_Pos) |
CAN_IF_T::MCON: MsgLst Mask
| #define CAN_IF_MCON_MsgLst_Pos (14) |
CAN_IF_T::MCON: MsgLst Position
| #define CAN_IF_MCON_NEWDAT_Msk (0x1ul << CAN_IF_MCON_NEWDAT_Pos) |
CAN_IF_T::MCON: NewDat Mask
| #define CAN_IF_MCON_NEWDAT_Pos (15) |
CAN_IF_T::MCON: NewDat Position
| #define CAN_IF_MCON_RmtEn_Msk (0x1ul << CAN_IF_MCON_RmtEn_Pos) |
CAN_IF_T::MCON: RmtEn Mask
| #define CAN_IF_MCON_RmtEn_Pos (9) |
CAN_IF_T::MCON: RmtEn Position
| #define CAN_IF_MCON_RXIE_Msk (0x1ul << CAN_IF_MCON_RXIE_Pos) |
CAN_IF_T::MCON: RxIE Mask
| #define CAN_IF_MCON_RXIE_Pos (10) |
CAN_IF_T::MCON: RxIE Position
| #define CAN_IF_MCON_TXIE_Msk (0x1ul << CAN_IF_MCON_TXIE_Pos) |
CAN_IF_T::MCON: TxIE Mask
| #define CAN_IF_MCON_TXIE_Pos (11) |
CAN_IF_T::MCON: TxIE Position
| #define CAN_IF_MCON_TxRqst_Msk (0x1ul << CAN_IF_MCON_TxRqst_Pos) |
CAN_IF_T::MCON: TxRqst Mask
| #define CAN_IF_MCON_TxRqst_Pos (8) |
CAN_IF_T::MCON: TxRqst Position
| #define CAN_IF_MCON_UMASK_Msk (0x1ul << CAN_IF_MCON_UMASK_Pos) |
CAN_IF_T::MCON: UMask Mask
| #define CAN_IF_MCON_UMASK_Pos (12) |
CAN_IF_T::MCON: UMask Position
| #define CAN_IIDR_IntId_Msk (0xfffful << CAN_IIDR_IntId_Pos) |
CAN_T::IIDR: IntId Mask
| #define CAN_IIDR_IntId_Pos (0) |
CAN_T::IIDR: IntId Position
| #define CAN_IPND1_IntPnd16_1_Msk (0xfffful << CAN_IPND1_IntPnd16_1_Pos) |
CAN_T::IPND1: IntPnd16_1 Mask
| #define CAN_IPND1_IntPnd16_1_Pos (0) |
CAN_T::IPND1: IntPnd16_1 Position
| #define CAN_IPND2_IntPnd32_17_Msk (0xfffful << CAN_IPND2_IntPnd32_17_Pos) |
CAN_T::IPND2: IntPnd32_17 Mask
| #define CAN_IPND2_IntPnd32_17_Pos (0) |
CAN_T::IPND2: IntPnd32_17 Position
| #define CAN_MVLD1_MsgVal16_1_Msk (0xfffful << CAN_MVLD1_MsgVal16_1_Pos) |
CAN_T::MVLD1: MsgVal16_1 Mask
| #define CAN_MVLD1_MsgVal16_1_Pos (0) |
CAN_T::MVLD1: MsgVal16_1 Position
| #define CAN_MVLD2_MsgVal32_17_Msk (0xfffful << CAN_MVLD2_MsgVal32_17_Pos) |
CAN_T::MVLD2: MsgVal32_17 Mask
| #define CAN_MVLD2_MsgVal32_17_Pos (0) |
CAN_T::MVLD2: MsgVal32_17 Position
| #define CAN_NDAT1_NewData16_1_Msk (0xfffful << CAN_NDAT1_NewData16_1_Pos) |
CAN_T::NDAT1: NewData16_1 Mask
| #define CAN_NDAT1_NewData16_1_Pos (0) |
CAN_T::NDAT1: NewData16_1 Position
| #define CAN_NDAT2_NewData32_17_Msk (0xfffful << CAN_NDAT2_NewData32_17_Pos) |
CAN_T::NDAT2: NewData32_17 Mask
| #define CAN_NDAT2_NewData32_17_Pos (0) |
CAN_T::NDAT2: NewData32_17 Position
| #define CAN_STATUS_BOFF_Msk (0x1ul << CAN_STATUS_BOFF_Pos) |
CAN_T::STATUS: BOff Mask
| #define CAN_STATUS_BOFF_Pos (7) |
CAN_T::STATUS: BOff Position
| #define CAN_STATUS_EPASS_Msk (0x1ul << CAN_STATUS_EPASS_Pos) |
CAN_T::STATUS: EPass Mask
| #define CAN_STATUS_EPASS_Pos (5) |
CAN_T::STATUS: EPass Position
| #define CAN_STATUS_EWARN_Msk (0x1ul << CAN_STATUS_EWARN_Pos) |
CAN_T::STATUS: EWarn Mask
| #define CAN_STATUS_EWARN_Pos (6) |
CAN_T::STATUS: EWarn Position
| #define CAN_STATUS_LEC_Msk (0x7ul << CAN_STATUS_LEC_Pos) |
CAN_T::STATUS: LEC Mask
| #define CAN_STATUS_LEC_Pos (0) |
CAN_T::STATUS: LEC Position
| #define CAN_STATUS_RXOK_Msk (0x1ul << CAN_STATUS_RXOK_Pos) |
CAN_T::STATUS: RxOK Mask
| #define CAN_STATUS_RXOK_Pos (4) |
CAN_T::STATUS: RxOK Position
| #define CAN_STATUS_TXOK_Msk (0x1ul << CAN_STATUS_TXOK_Pos) |
CAN_T::STATUS: TxOK Mask
| #define CAN_STATUS_TXOK_Pos (3) |
CAN_T::STATUS: TxOK Position
| #define CAN_TEST_BASIC_Msk (0x1ul << CAN_TEST_BASIC_Pos) |
CAN_T::TEST: Basic Mask
| #define CAN_TEST_BASIC_Pos (2) |
CAN_T::TEST: Basic Position
| #define CAN_TEST_LBACK_Msk (0x1ul << CAN_TEST_LBACK_Pos) |
CAN_T::TEST: LBack Mask
| #define CAN_TEST_LBACK_Pos (4) |
CAN_T::TEST: LBack Position
| #define CAN_TEST_Rx_Msk (0x1ul << CAN_TEST_Rx_Pos) |
CAN_T::TEST: Rx Mask
| #define CAN_TEST_Rx_Pos (7) |
CAN_T::TEST: Rx Position
| #define CAN_TEST_SILENT_Msk (0x1ul << CAN_TEST_SILENT_Pos) |
CAN_T::TEST: Silent Mask
| #define CAN_TEST_SILENT_Pos (3) |
CAN_T::TEST: Silent Position
| #define CAN_TEST_Tx_Msk (0x3ul << CAN_TEST_Tx_Pos) |
CAN_T::TEST: Tx Mask
| #define CAN_TEST_Tx_Pos (5) |
CAN_T::TEST: Tx Position
| #define CAN_TXREQ1_TXRQST16_1_Msk (0xfffful << CAN_TXREQ1_TXRQST16_1_Pos) |
CAN_T::TXREQ1: TxRqst16_1 Mask
| #define CAN_TXREQ1_TXRQST16_1_Pos (0) |
CAN_T::TXREQ1: TxRqst16_1 Position
| #define CAN_TXREQ2_TXRQST32_17_Msk (0xfffful << CAN_TXREQ2_TXRQST32_17_Pos) |
CAN_T::TXREQ2: TxRqst32_17 Mask
| #define CAN_TXREQ2_TXRQST32_17_Pos (0) |
CAN_T::TXREQ2: TxRqst32_17 Position
| #define CAN_WU_EN_WAKUP_EN_Msk (0x1ul << CAN_WU_EN_WAKUP_EN_Pos) |
CAN_T::WU_EN: WAKUP_EN Mask
| #define CAN_WU_EN_WAKUP_EN_Pos (0) |
CAN_T::WU_EN: WAKUP_EN Position
| #define CAN_WU_STATUS_WAKUP_STS_Msk (0x1ul << CAN_WU_STATUS_WAKUP_STS_Pos) |
CAN_T::WU_STATUS: WAKUP_STS Mask
| #define CAN_WU_STATUS_WAKUP_STS_Pos (0) |
CAN_T::WU_STATUS: WAKUP_STS Position
| #define CCAP_CMPADDR_CMPADDR_Msk (0xfffffffful << CCAP_CMPADDR_CMPADDR_Pos) |
CCAP_T::CMPADDR: CMPADDR Mask
Definition at line 471 of file ccap_reg.h.
| #define CCAP_CMPADDR_CMPADDR_Pos (0) |
CCAP_T::CMPADDR: CMPADDR Position
Definition at line 470 of file ccap_reg.h.
| #define CCAP_CTL_ADDRSW_Msk (0x1ul << CCAP_CTL_ADDRSW_Pos) |
CCAP_T::CTL: ADDRSW Mask
Definition at line 337 of file ccap_reg.h.
| #define CCAP_CTL_ADDRSW_Pos (3) |
CCAP_T::CTL: ADDRSW Position
Definition at line 336 of file ccap_reg.h.
| #define CCAP_CTL_CCAPEN_Msk (0x1ul << CCAP_CTL_CCAPEN_Pos) |
CCAP_T::CTL: CCAPEN Mask
Definition at line 334 of file ccap_reg.h.
| #define CCAP_CTL_CCAPEN_Pos (0) |
@addtogroup CCAP_CONST CCAP Bit Field Definition Constant Definitions for CCAP Controller
CCAP_T::CTL: CCAPEN Position
Definition at line 333 of file ccap_reg.h.
| #define CCAP_CTL_Luma_Y_One_Msk (0x1ul << CCAP_CTL_Luma_Y_One_Pos) |
CCAP_T::CTL: Luma_Y_One Mask
Definition at line 358 of file ccap_reg.h.
| #define CCAP_CTL_Luma_Y_One_Pos (19) |
CCAP_T::CTL: Luma_Y_One Position
Definition at line 357 of file ccap_reg.h.
| #define CCAP_CTL_MONO_Msk (0x1ul << CCAP_CTL_MONO_Pos) |
CCAP_T::CTL: MONO Mask
Definition at line 346 of file ccap_reg.h.
| #define CCAP_CTL_MONO_Pos (7) |
CCAP_T::CTL: MONO Position
Definition at line 345 of file ccap_reg.h.
| #define CCAP_CTL_MY4_SWAP_Msk (0x1ul << CCAP_CTL_MY4_SWAP_Pos) |
CCAP_T::CTL: MY4_SWAP Mask
Definition at line 352 of file ccap_reg.h.
| #define CCAP_CTL_MY4_SWAP_Pos (17) |
CCAP_T::CTL: MY4_SWAP Position
Definition at line 351 of file ccap_reg.h.
| #define CCAP_CTL_MY8_MY4_Msk (0x1ul << CCAP_CTL_MY8_MY4_Pos) |
CCAP_T::CTL: MY8_MY4 Mask
Definition at line 355 of file ccap_reg.h.
| #define CCAP_CTL_MY8_MY4_Pos (18) |
CCAP_T::CTL: MY8_MY4 Position
Definition at line 354 of file ccap_reg.h.
| #define CCAP_CTL_PKTEN_Msk (0x1ul << CCAP_CTL_PKTEN_Pos) |
CCAP_T::CTL: PKTEN Mask
Definition at line 343 of file ccap_reg.h.
| #define CCAP_CTL_PKTEN_Pos (6) |
CCAP_T::CTL: PKTEN Position
Definition at line 342 of file ccap_reg.h.
| #define CCAP_CTL_PLNEN_Msk (0x1ul << CCAP_CTL_PLNEN_Pos) |
CCAP_T::CTL: PLNEN Mask
Definition at line 340 of file ccap_reg.h.
| #define CCAP_CTL_PLNEN_Pos (5) |
CCAP_T::CTL: PLNEN Position
Definition at line 339 of file ccap_reg.h.
| #define CCAP_CTL_SHUTTER_Msk (0x1ul << CCAP_CTL_SHUTTER_Pos) |
CCAP_T::CTL: SHUTTER Mask
Definition at line 349 of file ccap_reg.h.
| #define CCAP_CTL_SHUTTER_Pos (16) |
CCAP_T::CTL: SHUTTER Position
Definition at line 348 of file ccap_reg.h.
| #define CCAP_CTL_UPDATE_Msk (0x1ul << CCAP_CTL_UPDATE_Pos) |
CCAP_T::CTL: UPDATE Mask
Definition at line 361 of file ccap_reg.h.
| #define CCAP_CTL_UPDATE_Pos (20) |
CCAP_T::CTL: UPDATE Position
Definition at line 360 of file ccap_reg.h.
| #define CCAP_CTL_VPRST_Msk (0x1ul << CCAP_CTL_VPRST_Pos) |
CCAP_T::CTL: VPRST Mask
Definition at line 364 of file ccap_reg.h.
| #define CCAP_CTL_VPRST_Pos (24) |
CCAP_T::CTL: VPRST Position
Definition at line 363 of file ccap_reg.h.
| #define CCAP_CWS_CWH_Msk (0x7fful << CCAP_CWS_CWH_Pos) |
CCAP_T::CWS: CIWH Mask
Definition at line 429 of file ccap_reg.h.
| #define CCAP_CWS_CWH_Pos (16) |
CCAP_T::CWS: CIWH Position
Definition at line 428 of file ccap_reg.h.
| #define CCAP_CWS_CWW_Msk (0xffful << CCAP_CWS_CWW_Pos) |
CCAP_T::CWS: CWW Mask
Definition at line 427 of file ccap_reg.h.
| #define CCAP_CWS_CWW_Pos (0) |
CCAP_T::CWS: CWW Position
Definition at line 426 of file ccap_reg.h.
| #define CCAP_CWSP_CWSADDRH_Msk (0xffful << CCAP_CWSP_CWSADDRH_Pos) |
CCAP_T::CWSP: CWSADDRH Mask
Definition at line 421 of file ccap_reg.h.
| #define CCAP_CWSP_CWSADDRH_Pos (0) |
CCAP_T::CWSP: CWSADDRH Position
Definition at line 420 of file ccap_reg.h.
| #define CCAP_CWSP_CWSADDRV_Msk (0x7fful << CCAP_CWSP_CWSADDRV_Pos) |
CCAP_T::CWSP: CWSADDRV Mask
Definition at line 424 of file ccap_reg.h.
| #define CCAP_CWSP_CWSADDRV_Pos (16) |
CCAP_T::CWSP: CWSADDRV Position
Definition at line 423 of file ccap_reg.h.
| #define CCAP_FIFOTH_OVF_Msk (0x1ul << CCAP_FIFOTH_OVF_Pos) |
CCAP_T::FIFOTH: OVF Mask
Definition at line 468 of file ccap_reg.h.
| #define CCAP_FIFOTH_OVF_Pos (31) |
CCAP_T::FIFOTH: OVF Position
Definition at line 467 of file ccap_reg.h.
| #define CCAP_FIFOTH_PKTFTH_Msk (0x1ful << CCAP_FIFOTH_PKTFTH_Pos) |
CCAP_T::FIFOTH: PKTFTH Mask
Definition at line 465 of file ccap_reg.h.
| #define CCAP_FIFOTH_PKTFTH_Pos (24) |
CCAP_T::FIFOTH: PKTFTH Position
Definition at line 464 of file ccap_reg.h.
| #define CCAP_FIFOTH_PLNUFTH_Msk (0xful << CCAP_FIFOTH_PLNUFTH_Pos) |
CCAP_T::FIFOTH: PLNUFTH Mask
Definition at line 459 of file ccap_reg.h.
| #define CCAP_FIFOTH_PLNUFTH_Pos (8) |
CCAP_T::FIFOTH: PLNUFTH Position
Definition at line 458 of file ccap_reg.h.
| #define CCAP_FIFOTH_PLNVFTH_Msk (0xful << CCAP_FIFOTH_PLNVFTH_Pos) |
CCAP_T::FIFOTH: PLNVFTH Mask
Definition at line 456 of file ccap_reg.h.
| #define CCAP_FIFOTH_PLNVFTH_Pos (0) |
CCAP_T::FIFOTH: PLNVFTH Position
Definition at line 455 of file ccap_reg.h.
| #define CCAP_FIFOTH_PLNYFTH_Msk (0x1ful << CCAP_FIFOTH_PLNYFTH_Pos) |
CCAP_T::FIFOTH: PLNYFTH Mask
Definition at line 462 of file ccap_reg.h.
| #define CCAP_FIFOTH_PLNYFTH_Pos (16) |
CCAP_T::FIFOTH: PLNYFTH Position
Definition at line 461 of file ccap_reg.h.
| #define CCAP_FRCTL_FRM_Msk (0x3ful << CCAP_FRCTL_FRM_Pos) |
CCAP_T::FRCTL: FRM Mask
Definition at line 444 of file ccap_reg.h.
| #define CCAP_FRCTL_FRM_Pos (0) |
CCAP_T::FRCTL: FRM Position
Definition at line 443 of file ccap_reg.h.
| #define CCAP_FRCTL_FRN_Msk (0x3ful << CCAP_FRCTL_FRN_Pos) |
CCAP_T::FRCTL: FRN Mask
Definition at line 447 of file ccap_reg.h.
| #define CCAP_FRCTL_FRN_Pos (8) |
CCAP_T::FRCTL: FRN Position
Definition at line 446 of file ccap_reg.h.
| #define CCAP_INT_ADDRMIEN_Msk (0x1ul << CCAP_INT_ADDRMIEN_Pos) |
CCAP_T::INT: ADDRMIEN Mask
Definition at line 418 of file ccap_reg.h.
| #define CCAP_INT_ADDRMIEN_Pos (19) |
CCAP_T::INT: ADDRMIEN Position
Definition at line 417 of file ccap_reg.h.
| #define CCAP_INT_ADDRMINTF_Msk (0x1ul << CCAP_INT_ADDRMINTF_Pos) |
CCAP_T::INT: ADDRMINTF Mask
Definition at line 406 of file ccap_reg.h.
| #define CCAP_INT_ADDRMINTF_Pos (3) |
CCAP_T::INT: ADDRMINTF Position
Definition at line 405 of file ccap_reg.h.
| #define CCAP_INT_MDINTF_Msk (0x1ul << CCAP_INT_MDINTF_Pos) |
CCAP_T::INT: MDINTF Mask
Definition at line 409 of file ccap_reg.h.
| #define CCAP_INT_MDINTF_Pos (4) |
CCAP_T::INT: MDINTF Position
Definition at line 408 of file ccap_reg.h.
| #define CCAP_INT_MEIEN_Msk (0x1ul << CCAP_INT_MEIEN_Pos) |
CCAP_T::INT: MEIEN Mask
Definition at line 415 of file ccap_reg.h.
| #define CCAP_INT_MEIEN_Pos (17) |
CCAP_T::INT: MEIEN Position
Definition at line 414 of file ccap_reg.h.
| #define CCAP_INT_MEINTF_Msk (0x1ul << CCAP_INT_MEINTF_Pos) |
CCAP_T::INT: MEINTF Mask
Definition at line 403 of file ccap_reg.h.
| #define CCAP_INT_MEINTF_Pos (1) |
CCAP_T::INT: MEINTF Position
Definition at line 402 of file ccap_reg.h.
| #define CCAP_INT_VIEN_Msk (0x1ul << CCAP_INT_VIEN_Pos) |
CCAP_T::INT: VIEN Mask
Definition at line 412 of file ccap_reg.h.
| #define CCAP_INT_VIEN_Pos (16) |
CCAP_T::INT: VIEN Position
Definition at line 411 of file ccap_reg.h.
| #define CCAP_INT_VINTF_Msk (0x1ul << CCAP_INT_VINTF_Pos) |
CCAP_T::INT: VINTF Mask
Definition at line 400 of file ccap_reg.h.
| #define CCAP_INT_VINTF_Pos (0) |
CCAP_T::INT: VINTF Position
Definition at line 399 of file ccap_reg.h.
| #define CCAP_PAR_COLORCTL_Msk (0x3ul << CCAP_PAR_COLORCTL_Pos) |
CCAP_T::PAR: COLORCTL Mask
Definition at line 394 of file ccap_reg.h.
| #define CCAP_PAR_COLORCTL_Pos (11) |
CCAP_T::PAR: COLORCTL Position
Definition at line 393 of file ccap_reg.h.
| #define CCAP_PAR_FBB_Msk (0x1ul << CCAP_PAR_FBB_Pos) |
CCAP_T::PAR: FBB Mask
Definition at line 397 of file ccap_reg.h.
| #define CCAP_PAR_FBB_Pos (18) |
CCAP_T::PAR: FBB Position
Definition at line 396 of file ccap_reg.h.
| #define CCAP_PAR_HSP_Msk (0x1ul << CCAP_PAR_HSP_Pos) |
CCAP_T::PAR: HSP Mask
Definition at line 388 of file ccap_reg.h.
| #define CCAP_PAR_HSP_Pos (9) |
CCAP_T::PAR: HSP Position
Definition at line 387 of file ccap_reg.h.
| #define CCAP_PAR_INDATORD_Msk (0x3ul << CCAP_PAR_INDATORD_Pos) |
CCAP_T::PAR: INDATORD Mask
Definition at line 373 of file ccap_reg.h.
| #define CCAP_PAR_INDATORD_Pos (2) |
CCAP_T::PAR: INDATORD Position
Definition at line 372 of file ccap_reg.h.
| #define CCAP_PAR_INFMT_Msk (0x1ul << CCAP_PAR_INFMT_Pos) |
CCAP_T::PAR: INFMT Mask
Definition at line 367 of file ccap_reg.h.
| #define CCAP_PAR_INFMT_Pos (0) |
CCAP_T::PAR: INFMT Position
Definition at line 366 of file ccap_reg.h.
| #define CCAP_PAR_OUTFMT_Msk (0x3ul << CCAP_PAR_OUTFMT_Pos) |
CCAP_T::PAR: OUTFMT Mask
Definition at line 376 of file ccap_reg.h.
| #define CCAP_PAR_OUTFMT_Pos (4) |
CCAP_T::PAR: OUTFMT Position
Definition at line 375 of file ccap_reg.h.
| #define CCAP_PAR_PCLKP_Msk (0x1ul << CCAP_PAR_PCLKP_Pos) |
CCAP_T::PAR: PCLKP Mask
Definition at line 385 of file ccap_reg.h.
| #define CCAP_PAR_PCLKP_Pos (8) |
CCAP_T::PAR: PCLKP Position
Definition at line 384 of file ccap_reg.h.
| #define CCAP_PAR_PLNFMT_Msk (0x1ul << CCAP_PAR_PLNFMT_Pos) |
CCAP_T::PAR: PLNFMT Mask
Definition at line 382 of file ccap_reg.h.
| #define CCAP_PAR_PLNFMT_Pos (7) |
CCAP_T::PAR: PLNFMT Position
Definition at line 381 of file ccap_reg.h.
| #define CCAP_PAR_RANGE_Msk (0x1ul << CCAP_PAR_RANGE_Pos) |
CCAP_T::PAR: RANGE Mask
Definition at line 379 of file ccap_reg.h.
| #define CCAP_PAR_RANGE_Pos (6) |
CCAP_T::PAR: RANGE Position
Definition at line 378 of file ccap_reg.h.
| #define CCAP_PAR_SENTYPE_Msk (0x1ul << CCAP_PAR_SENTYPE_Pos) |
CCAP_T::PAR: SENTYPE Mask
Definition at line 370 of file ccap_reg.h.
| #define CCAP_PAR_SENTYPE_Pos (1) |
CCAP_T::PAR: SENTYPE Position
Definition at line 369 of file ccap_reg.h.
| #define CCAP_PAR_VSP_Msk (0x1ul << CCAP_PAR_VSP_Pos) |
CCAP_T::PAR: VSP Mask
Definition at line 391 of file ccap_reg.h.
| #define CCAP_PAR_VSP_Pos (10) |
CCAP_T::PAR: VSP Position
Definition at line 390 of file ccap_reg.h.
| #define CCAP_PKTBA0_BASEADDR_Msk (0xfffffffful << CCAP_PKTBA0_BASEADDR_Pos) |
CCAP_T::PKTBA0: BASEADDR Mask
Definition at line 486 of file ccap_reg.h.
| #define CCAP_PKTBA0_BASEADDR_Pos (0) |
CCAP_T::PKTBA0: BASEADDR Position
Definition at line 485 of file ccap_reg.h.
| #define CCAP_PKTSL_PKTSHML_Msk (0xfful << CCAP_PKTSL_PKTSHML_Pos) |
CCAP_T::PKTSL: PKTSHML Mask
Definition at line 432 of file ccap_reg.h.
| #define CCAP_PKTSL_PKTSHML_Pos (0) |
CCAP_T::PKTSL: PKTSHML Position
Definition at line 431 of file ccap_reg.h.
| #define CCAP_PKTSL_PKTSHNL_Msk (0xfful << CCAP_PKTSL_PKTSHNL_Pos) |
CCAP_T::PKTSL: PKTSHNL Mask
Definition at line 435 of file ccap_reg.h.
| #define CCAP_PKTSL_PKTSHNL_Pos (8) |
CCAP_T::PKTSL: PKTSHNL Position
Definition at line 434 of file ccap_reg.h.
| #define CCAP_PKTSL_PKTSVML_Msk (0xfful << CCAP_PKTSL_PKTSVML_Pos) |
CCAP_T::PKTSL: PKTSVML Mask
Definition at line 438 of file ccap_reg.h.
| #define CCAP_PKTSL_PKTSVML_Pos (16) |
CCAP_T::PKTSL: PKTSVML Position
Definition at line 437 of file ccap_reg.h.
| #define CCAP_PKTSL_PKTSVNL_Msk (0xfful << CCAP_PKTSL_PKTSVNL_Pos) |
CCAP_T::PKTSL: PKTSVNL Mask
Definition at line 441 of file ccap_reg.h.
| #define CCAP_PKTSL_PKTSVNL_Pos (24) |
CCAP_T::PKTSL: PKTSVNL Position
Definition at line 440 of file ccap_reg.h.
| #define CCAP_PKTSM_PKTSHMH_Msk (0xfful << CCAP_PKTSM_PKTSHMH_Pos) |
CCAP_T::PKTSM: PKTSHMH Mask
Definition at line 474 of file ccap_reg.h.
| #define CCAP_PKTSM_PKTSHMH_Pos (0) |
CCAP_T::PKTSM: PKTSHMH Position
Definition at line 473 of file ccap_reg.h.
| #define CCAP_PKTSM_PKTSHNH_Msk (0xfful << CCAP_PKTSM_PKTSHNH_Pos) |
CCAP_T::PKTSM: PKTSHNH Mask
Definition at line 477 of file ccap_reg.h.
| #define CCAP_PKTSM_PKTSHNH_Pos (8) |
CCAP_T::PKTSM: PKTSHNH Position
Definition at line 476 of file ccap_reg.h.
| #define CCAP_PKTSM_PKTSVMH_Msk (0xfful << CCAP_PKTSM_PKTSVMH_Pos) |
CCAP_T::PKTSM: PKTSVMH Mask
Definition at line 480 of file ccap_reg.h.
| #define CCAP_PKTSM_PKTSVMH_Pos (16) |
CCAP_T::PKTSM: PKTSVMH Position
Definition at line 479 of file ccap_reg.h.
| #define CCAP_PKTSM_PKTSVNH_Msk (0xfful << CCAP_PKTSM_PKTSVNH_Pos) |
CCAP_T::PKTSM: PKTSVNH Mask
Definition at line 483 of file ccap_reg.h.
| #define CCAP_PKTSM_PKTSVNH_Pos (24) |
CCAP_T::PKTSM: PKTSVNH Position
Definition at line 482 of file ccap_reg.h.
| #define CCAP_STRIDE_PKTSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PKTSTRIDE_Pos) |
CCAP_T::STRIDE: PKTSTRIDE Mask
Definition at line 450 of file ccap_reg.h.
| #define CCAP_STRIDE_PKTSTRIDE_Pos (0) |
CCAP_T::STRIDE: PKTSTRIDE Position
Definition at line 449 of file ccap_reg.h.
| #define CCAP_STRIDE_PLNSTRIDE_Msk (0x3ffful << CCAP_STRIDE_PLNSTRIDE_Pos) |
CCAP_T::STRIDE: PLNSTRIDE Mask
Definition at line 453 of file ccap_reg.h.
| #define CCAP_STRIDE_PLNSTRIDE_Pos (16) |
CCAP_T::STRIDE: PLNSTRIDE Position
Definition at line 452 of file ccap_reg.h.
| #define CLK_AHBCLK_CCAPCKEN_Msk (0x1ul << CLK_AHBCLK_CCAPCKEN_Pos) |
CLK_T::AHBCLK: CCAPCKEN Mask
| #define CLK_AHBCLK_CCAPCKEN_Pos (8) |
CLK_T::AHBCLK: CCAPCKEN Position
| #define CLK_AHBCLK_CRCCKEN_Msk (0x1ul << CLK_AHBCLK_CRCCKEN_Pos) |
CLK_T::AHBCLK: CRCCKEN Mask
| #define CLK_AHBCLK_CRCCKEN_Pos (7) |
CLK_T::AHBCLK: CRCCKEN Position
| #define CLK_AHBCLK_CRPTCKEN_Msk (0x1ul << CLK_AHBCLK_CRPTCKEN_Pos) |
CLK_T::AHBCLK: CRPTCKEN Mask
| #define CLK_AHBCLK_CRPTCKEN_Pos (12) |
CLK_T::AHBCLK: CRPTCKEN Position
| #define CLK_AHBCLK_EBICKEN_Msk (0x1ul << CLK_AHBCLK_EBICKEN_Pos) |
CLK_T::AHBCLK: EBICKEN Mask
| #define CLK_AHBCLK_EBICKEN_Pos (3) |
CLK_T::AHBCLK: EBICKEN Position
| #define CLK_AHBCLK_EMACCKEN_Msk (0x1ul << CLK_AHBCLK_EMACCKEN_Pos) |
CLK_T::AHBCLK: EMACCKEN Mask
| #define CLK_AHBCLK_EMACCKEN_Pos (5) |
CLK_T::AHBCLK: EMACCKEN Position
| #define CLK_AHBCLK_FMCIDLE_Msk (0x1ul << CLK_AHBCLK_FMCIDLE_Pos) |
CLK_T::AHBCLK: FMCIDLE Mask
| #define CLK_AHBCLK_FMCIDLE_Pos (15) |
CLK_T::AHBCLK: FMCIDLE Position
| #define CLK_AHBCLK_ISPCKEN_Msk (0x1ul << CLK_AHBCLK_ISPCKEN_Pos) |
CLK_T::AHBCLK: ISPCKEN Mask
| #define CLK_AHBCLK_ISPCKEN_Pos (2) |
CLK_T::AHBCLK: ISPCKEN Position
| #define CLK_AHBCLK_PDMACKEN_Msk (0x1ul << CLK_AHBCLK_PDMACKEN_Pos) |
CLK_T::AHBCLK: PDMACKEN Mask
| #define CLK_AHBCLK_PDMACKEN_Pos (1) |
CLK_T::AHBCLK: PDMACKEN Position
| #define CLK_AHBCLK_SDH0CKEN_Msk (0x1ul << CLK_AHBCLK_SDH0CKEN_Pos) |
CLK_T::AHBCLK: SDH0CKEN Mask
| #define CLK_AHBCLK_SDH0CKEN_Pos (6) |
CLK_T::AHBCLK: SDH0CKEN Position
| #define CLK_AHBCLK_SDH1CKEN_Msk (0x1ul << CLK_AHBCLK_SDH1CKEN_Pos) |
CLK_T::AHBCLK: SDH1CKEN Mask
| #define CLK_AHBCLK_SDH1CKEN_Pos (17) |
CLK_T::AHBCLK: SDH1CKEN Position
| #define CLK_AHBCLK_SENCKEN_Msk (0x1ul << CLK_AHBCLK_SENCKEN_Pos) |
CLK_T::AHBCLK: SENCKEN Mask
| #define CLK_AHBCLK_SENCKEN_Pos (9) |
CLK_T::AHBCLK: SENCKEN Position
| #define CLK_AHBCLK_SPIMCKEN_Msk (0x1ul << CLK_AHBCLK_SPIMCKEN_Pos) |
CLK_T::AHBCLK: SPIMCKEN Mask
| #define CLK_AHBCLK_SPIMCKEN_Pos (14) |
CLK_T::AHBCLK: SPIMCKEN Position
| #define CLK_AHBCLK_USBHCKEN_Msk (0x1ul << CLK_AHBCLK_USBHCKEN_Pos) |
CLK_T::AHBCLK: USBHCKEN Mask
| #define CLK_AHBCLK_USBHCKEN_Pos (16) |
CLK_T::AHBCLK: USBHCKEN Position
| #define CLK_APBCLK0_ACMP01CKEN_Msk (0x1ul << CLK_APBCLK0_ACMP01CKEN_Pos) |
CLK_T::APBCLK0: ACMP01CKEN Mask
| #define CLK_APBCLK0_ACMP01CKEN_Pos (7) |
CLK_T::APBCLK0: ACMP01CKEN Position
| #define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) |
CLK_T::APBCLK0: CAN0CKEN Mask
| #define CLK_APBCLK0_CAN0CKEN_Pos (24) |
CLK_T::APBCLK0: CAN0CKEN Position
| #define CLK_APBCLK0_CAN1CKEN_Msk (0x1ul << CLK_APBCLK0_CAN1CKEN_Pos) |
CLK_T::APBCLK0: CAN1CKEN Mask
| #define CLK_APBCLK0_CAN1CKEN_Pos (25) |
CLK_T::APBCLK0: CAN1CKEN Position
| #define CLK_APBCLK0_CLKOCKEN_Msk (0x1ul << CLK_APBCLK0_CLKOCKEN_Pos) |
CLK_T::APBCLK0: CLKOCKEN Mask
| #define CLK_APBCLK0_CLKOCKEN_Pos (6) |
CLK_T::APBCLK0: CLKOCKEN Position
| #define CLK_APBCLK0_EADCCKEN_Msk (0x1ul << CLK_APBCLK0_EADCCKEN_Pos) |
CLK_T::APBCLK0: EADCCKEN Mask
| #define CLK_APBCLK0_EADCCKEN_Pos (28) |
CLK_T::APBCLK0: EADCCKEN Position
| #define CLK_APBCLK0_I2C0CKEN_Msk (0x1ul << CLK_APBCLK0_I2C0CKEN_Pos) |
CLK_T::APBCLK0: I2C0CKEN Mask
| #define CLK_APBCLK0_I2C0CKEN_Pos (8) |
CLK_T::APBCLK0: I2C0CKEN Position
| #define CLK_APBCLK0_I2C1CKEN_Msk (0x1ul << CLK_APBCLK0_I2C1CKEN_Pos) |
CLK_T::APBCLK0: I2C1CKEN Mask
| #define CLK_APBCLK0_I2C1CKEN_Pos (9) |
CLK_T::APBCLK0: I2C1CKEN Position
| #define CLK_APBCLK0_I2S0CKEN_Msk (0x1ul << CLK_APBCLK0_I2S0CKEN_Pos) |
CLK_T::APBCLK0: I2S0CKEN Mask
| #define CLK_APBCLK0_I2S0CKEN_Pos (29) |
CLK_T::APBCLK0: I2S0CKEN Position
| #define CLK_APBCLK0_OTGCKEN_Msk (0x1ul << CLK_APBCLK0_OTGCKEN_Pos) |
CLK_T::APBCLK0: OTGCKEN Mask
| #define CLK_APBCLK0_OTGCKEN_Pos (26) |
CLK_T::APBCLK0: OTGCKEN Position
| #define CLK_APBCLK0_QSPI0CKEN_Msk (0x1ul << CLK_APBCLK0_QSPI0CKEN_Pos) |
CLK_T::APBCLK0: QSPI0CKEN Mask
| #define CLK_APBCLK0_QSPI0CKEN_Pos (12) |
CLK_T::APBCLK0: QSPI0CKEN Position
| #define CLK_APBCLK0_RTCCKEN_Msk (0x1ul << CLK_APBCLK0_RTCCKEN_Pos) |
CLK_T::APBCLK0: RTCCKEN Mask
| #define CLK_APBCLK0_RTCCKEN_Pos (1) |
CLK_T::APBCLK0: RTCCKEN Position
| #define CLK_APBCLK0_SPI0CKEN_Msk (0x1ul << CLK_APBCLK0_SPI0CKEN_Pos) |
CLK_T::APBCLK0: SPI0CKEN Mask
| #define CLK_APBCLK0_SPI0CKEN_Pos (13) |
CLK_T::APBCLK0: SPI0CKEN Position
| #define CLK_APBCLK0_SPI1CKEN_Msk (0x1ul << CLK_APBCLK0_SPI1CKEN_Pos) |
CLK_T::APBCLK0: SPI1CKEN Mask
| #define CLK_APBCLK0_SPI1CKEN_Pos (14) |
CLK_T::APBCLK0: SPI1CKEN Position
| #define CLK_APBCLK0_SPI2CKEN_Msk (0x1ul << CLK_APBCLK0_SPI2CKEN_Pos) |
CLK_T::APBCLK0: SPI2CKEN Mask
| #define CLK_APBCLK0_SPI2CKEN_Pos (15) |
CLK_T::APBCLK0: SPI2CKEN Position
| #define CLK_APBCLK0_TMR0CKEN_Msk (0x1ul << CLK_APBCLK0_TMR0CKEN_Pos) |
CLK_T::APBCLK0: TMR0CKEN Mask
| #define CLK_APBCLK0_TMR0CKEN_Pos (2) |
CLK_T::APBCLK0: TMR0CKEN Position
| #define CLK_APBCLK0_TMR1CKEN_Msk (0x1ul << CLK_APBCLK0_TMR1CKEN_Pos) |
CLK_T::APBCLK0: TMR1CKEN Mask
| #define CLK_APBCLK0_TMR1CKEN_Pos (3) |
CLK_T::APBCLK0: TMR1CKEN Position
| #define CLK_APBCLK0_TMR2CKEN_Msk (0x1ul << CLK_APBCLK0_TMR2CKEN_Pos) |
CLK_T::APBCLK0: TMR2CKEN Mask
| #define CLK_APBCLK0_TMR2CKEN_Pos (4) |
CLK_T::APBCLK0: TMR2CKEN Position
| #define CLK_APBCLK0_TMR3CKEN_Msk (0x1ul << CLK_APBCLK0_TMR3CKEN_Pos) |
CLK_T::APBCLK0: TMR3CKEN Mask
| #define CLK_APBCLK0_TMR3CKEN_Pos (5) |
CLK_T::APBCLK0: TMR3CKEN Position
| #define CLK_APBCLK0_UART0CKEN_Msk (0x1ul << CLK_APBCLK0_UART0CKEN_Pos) |
CLK_T::APBCLK0: UART0CKEN Mask
| #define CLK_APBCLK0_UART0CKEN_Pos (16) |
CLK_T::APBCLK0: UART0CKEN Position
| #define CLK_APBCLK0_UART1CKEN_Msk (0x1ul << CLK_APBCLK0_UART1CKEN_Pos) |
CLK_T::APBCLK0: UART1CKEN Mask
| #define CLK_APBCLK0_UART1CKEN_Pos (17) |
CLK_T::APBCLK0: UART1CKEN Position
| #define CLK_APBCLK0_UART2CKEN_Msk (0x1ul << CLK_APBCLK0_UART2CKEN_Pos) |
CLK_T::APBCLK0: UART2CKEN Mask
| #define CLK_APBCLK0_UART2CKEN_Pos (18) |
CLK_T::APBCLK0: UART2CKEN Position
| #define CLK_APBCLK0_UART3CKEN_Msk (0x1ul << CLK_APBCLK0_UART3CKEN_Pos) |
CLK_T::APBCLK0: UART3CKEN Mask
| #define CLK_APBCLK0_UART3CKEN_Pos (19) |
CLK_T::APBCLK0: UART3CKEN Position
| #define CLK_APBCLK0_UART4CKEN_Msk (0x1ul << CLK_APBCLK0_UART4CKEN_Pos) |
CLK_T::APBCLK0: UART4CKEN Mask
| #define CLK_APBCLK0_UART4CKEN_Pos (20) |
CLK_T::APBCLK0: UART4CKEN Position
| #define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) |
CLK_T::APBCLK0: UART5CKEN Mask
| #define CLK_APBCLK0_UART5CKEN_Pos (21) |
CLK_T::APBCLK0: UART5CKEN Position
| #define CLK_APBCLK0_UART6CKEN_Msk (0x1ul << CLK_APBCLK0_UART6CKEN_Pos) |
CLK_T::APBCLK0: UART6CKEN Mask
| #define CLK_APBCLK0_UART6CKEN_Pos (22) |
CLK_T::APBCLK0: UART6CKEN Position
| #define CLK_APBCLK0_UART7CKEN_Msk (0x1ul << CLK_APBCLK0_UART7CKEN_Pos) |
CLK_T::APBCLK0: UART7CKEN Mask
| #define CLK_APBCLK0_UART7CKEN_Pos (23) |
CLK_T::APBCLK0: UART7CKEN Position
| #define CLK_APBCLK0_USBDCKEN_Msk (0x1ul << CLK_APBCLK0_USBDCKEN_Pos) |
CLK_T::APBCLK0: USBDCKEN Mask
| #define CLK_APBCLK0_USBDCKEN_Pos (27) |
CLK_T::APBCLK0: USBDCKEN Position
| #define CLK_APBCLK0_WDTCKEN_Msk (0x1ul << CLK_APBCLK0_WDTCKEN_Pos) |
CLK_T::APBCLK0: WDTCKEN Mask
| #define CLK_APBCLK0_WDTCKEN_Pos (0) |
CLK_T::APBCLK0: WDTCKEN Position
| #define CLK_APBCLK1_BPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM0CKEN_Pos) |
CLK_T::APBCLK1: BPWM0CKEN Mask
| #define CLK_APBCLK1_BPWM0CKEN_Pos (18) |
CLK_T::APBCLK1: BPWM0CKEN Position
| #define CLK_APBCLK1_BPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_BPWM1CKEN_Pos) |
CLK_T::APBCLK1: BPWM1CKEN Mask
| #define CLK_APBCLK1_BPWM1CKEN_Pos (19) |
CLK_T::APBCLK1: BPWM1CKEN Position
| #define CLK_APBCLK1_DACCKEN_Msk (0x1ul << CLK_APBCLK1_DACCKEN_Pos) |
CLK_T::APBCLK1: DACCKEN Mask
| #define CLK_APBCLK1_DACCKEN_Pos (12) |
CLK_T::APBCLK1: DACCKEN Position
| #define CLK_APBCLK1_EADC1CKEN_Msk (0x1ul << CLK_APBCLK1_EADC1CKEN_Pos) |
CLK_T::APBCLK1: EADC1CKEN Mask
| #define CLK_APBCLK1_EADC1CKEN_Pos (31) |
CLK_T::APBCLK1: EADC1CKEN Position
| #define CLK_APBCLK1_ECAP0CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP0CKEN_Pos) |
CLK_T::APBCLK1: ECAP0CKEN Mask
| #define CLK_APBCLK1_ECAP0CKEN_Pos (26) |
CLK_T::APBCLK1: ECAP0CKEN Position
| #define CLK_APBCLK1_ECAP1CKEN_Msk (0x1ul << CLK_APBCLK1_ECAP1CKEN_Pos) |
CLK_T::APBCLK1: ECAP1CKEN Mask
| #define CLK_APBCLK1_ECAP1CKEN_Pos (27) |
CLK_T::APBCLK1: ECAP1CKEN Position
| #define CLK_APBCLK1_EPWM0CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM0CKEN_Pos) |
CLK_T::APBCLK1: EPWM0CKEN Mask
| #define CLK_APBCLK1_EPWM0CKEN_Pos (16) |
CLK_T::APBCLK1: EPWM0CKEN Position
| #define CLK_APBCLK1_EPWM1CKEN_Msk (0x1ul << CLK_APBCLK1_EPWM1CKEN_Pos) |
CLK_T::APBCLK1: EPWM1CKEN Mask
| #define CLK_APBCLK1_EPWM1CKEN_Pos (17) |
CLK_T::APBCLK1: EPWM1CKEN Position
| #define CLK_APBCLK1_OPACKEN_Msk (0x1ul << CLK_APBCLK1_OPACKEN_Pos) |
CLK_T::APBCLK1: OPACKEN Mask
| #define CLK_APBCLK1_OPACKEN_Pos (30) |
CLK_T::APBCLK1: OPACKEN Position
| #define CLK_APBCLK1_QEI0CKEN_Msk (0x1ul << CLK_APBCLK1_QEI0CKEN_Pos) |
CLK_T::APBCLK1: QEI0CKEN Mask
| #define CLK_APBCLK1_QEI0CKEN_Pos (22) |
CLK_T::APBCLK1: QEI0CKEN Position
| #define CLK_APBCLK1_QEI1CKEN_Msk (0x1ul << CLK_APBCLK1_QEI1CKEN_Pos) |
CLK_T::APBCLK1: QEI1CKEN Mask
| #define CLK_APBCLK1_QEI1CKEN_Pos (23) |
CLK_T::APBCLK1: QEI1CKEN Position
| #define CLK_APBCLK1_QSPI1CKEN_Msk (0x1ul << CLK_APBCLK1_QSPI1CKEN_Pos) |
CLK_T::APBCLK1: QSPI1CKEN Mask
| #define CLK_APBCLK1_QSPI1CKEN_Pos (4) |
CLK_T::APBCLK1: QSPI1CKEN Position
| #define CLK_APBCLK1_SC0CKEN_Msk (0x1ul << CLK_APBCLK1_SC0CKEN_Pos) |
CLK_T::APBCLK1: SC0CKEN Mask
| #define CLK_APBCLK1_SC0CKEN_Pos (0) |
CLK_T::APBCLK1: SC0CKEN Position
| #define CLK_APBCLK1_SC1CKEN_Msk (0x1ul << CLK_APBCLK1_SC1CKEN_Pos) |
CLK_T::APBCLK1: SC1CKEN Mask
| #define CLK_APBCLK1_SC1CKEN_Pos (1) |
CLK_T::APBCLK1: SC1CKEN Position
| #define CLK_APBCLK1_SC2CKEN_Msk (0x1ul << CLK_APBCLK1_SC2CKEN_Pos) |
CLK_T::APBCLK1: SC2CKEN Mask
| #define CLK_APBCLK1_SC2CKEN_Pos (2) |
CLK_T::APBCLK1: SC2CKEN Position
| #define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) |
CLK_T::APBCLK1: SPI3CKEN Mask
| #define CLK_APBCLK1_SPI3CKEN_Pos (6) |
CLK_T::APBCLK1: SPI3CKEN Position
| #define CLK_APBCLK1_TRNGCKEN_Msk (0x1ul << CLK_APBCLK1_TRNGCKEN_Pos) |
CLK_T::APBCLK1: TRNGCKEN Mask
| #define CLK_APBCLK1_TRNGCKEN_Pos (25) |
CLK_T::APBCLK1: TRNGCKEN Position
| #define CLK_CDLOWB_LOWERBD_Msk (0x3fful << CLK_CDLOWB_LOWERBD_Pos) |
CLK_T::CDLOWB: LOWERBD Mask
| #define CLK_CDLOWB_LOWERBD_Pos (0) |
CLK_T::CDLOWB: LOWERBD Position
| #define CLK_CDUPB_UPERBD_Msk (0x3fful << CLK_CDUPB_UPERBD_Pos) |
CLK_T::CDUPB: UPERBD Mask
| #define CLK_CDUPB_UPERBD_Pos (0) |
CLK_T::CDUPB: UPERBD Position
| #define CLK_CLKDCTL_HXTFDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFDEN_Pos) |
CLK_T::CLKDCTL: HXTFDEN Mask
| #define CLK_CLKDCTL_HXTFDEN_Pos (4) |
CLK_T::CLKDCTL: HXTFDEN Position
| #define CLK_CLKDCTL_HXTFIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFIEN_Pos) |
CLK_T::CLKDCTL: HXTFIEN Mask
| #define CLK_CLKDCTL_HXTFIEN_Pos (5) |
CLK_T::CLKDCTL: HXTFIEN Position
| #define CLK_CLKDCTL_HXTFQDEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQDEN_Pos) |
CLK_T::CLKDCTL: HXTFQDEN Mask
| #define CLK_CLKDCTL_HXTFQDEN_Pos (16) |
CLK_T::CLKDCTL: HXTFQDEN Position
| #define CLK_CLKDCTL_HXTFQIEN_Msk (0x1ul << CLK_CLKDCTL_HXTFQIEN_Pos) |
CLK_T::CLKDCTL: HXTFQIEN Mask
| #define CLK_CLKDCTL_HXTFQIEN_Pos (17) |
CLK_T::CLKDCTL: HXTFQIEN Position
| #define CLK_CLKDCTL_LXTFDEN_Msk (0x1ul << CLK_CLKDCTL_LXTFDEN_Pos) |
CLK_T::CLKDCTL: LXTFDEN Mask
| #define CLK_CLKDCTL_LXTFDEN_Pos (12) |
CLK_T::CLKDCTL: LXTFDEN Position
| #define CLK_CLKDCTL_LXTFIEN_Msk (0x1ul << CLK_CLKDCTL_LXTFIEN_Pos) |
CLK_T::CLKDCTL: LXTFIEN Mask
| #define CLK_CLKDCTL_LXTFIEN_Pos (13) |
CLK_T::CLKDCTL: LXTFIEN Position
| #define CLK_CLKDIV0_EADCDIV_Msk (0xfful << CLK_CLKDIV0_EADCDIV_Pos) |
CLK_T::CLKDIV0: EADCDIV Mask
| #define CLK_CLKDIV0_EADCDIV_Pos (16) |
CLK_T::CLKDIV0: EADCDIV Position
| #define CLK_CLKDIV0_HCLKDIV_Msk (0xful << CLK_CLKDIV0_HCLKDIV_Pos) |
CLK_T::CLKDIV0: HCLKDIV Mask
| #define CLK_CLKDIV0_HCLKDIV_Pos (0) |
CLK_T::CLKDIV0: HCLKDIV Position
| #define CLK_CLKDIV0_SDH0DIV_Msk (0xfful << CLK_CLKDIV0_SDH0DIV_Pos) |
CLK_T::CLKDIV0: SDH0DIV Mask
| #define CLK_CLKDIV0_SDH0DIV_Pos (24) |
CLK_T::CLKDIV0: SDH0DIV Position
| #define CLK_CLKDIV0_UART0DIV_Msk (0xful << CLK_CLKDIV0_UART0DIV_Pos) |
CLK_T::CLKDIV0: UART0DIV Mask
| #define CLK_CLKDIV0_UART0DIV_Pos (8) |
CLK_T::CLKDIV0: UART0DIV Position
| #define CLK_CLKDIV0_UART1DIV_Msk (0xful << CLK_CLKDIV0_UART1DIV_Pos) |
CLK_T::CLKDIV0: UART1DIV Mask
| #define CLK_CLKDIV0_UART1DIV_Pos (12) |
CLK_T::CLKDIV0: UART1DIV Position
| #define CLK_CLKDIV0_USBDIV_Msk (0xful << CLK_CLKDIV0_USBDIV_Pos) |
CLK_T::CLKDIV0: USBDIV Mask
| #define CLK_CLKDIV0_USBDIV_Pos (4) |
CLK_T::CLKDIV0: USBDIV Position
| #define CLK_CLKDIV1_SC0DIV_Msk (0xfful << CLK_CLKDIV1_SC0DIV_Pos) |
CLK_T::CLKDIV1: SC0DIV Mask
| #define CLK_CLKDIV1_SC0DIV_Pos (0) |
CLK_T::CLKDIV1: SC0DIV Position
| #define CLK_CLKDIV1_SC1DIV_Msk (0xfful << CLK_CLKDIV1_SC1DIV_Pos) |
CLK_T::CLKDIV1: SC1DIV Mask
| #define CLK_CLKDIV1_SC1DIV_Pos (8) |
CLK_T::CLKDIV1: SC1DIV Position
| #define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) |
CLK_T::CLKDIV1: SC2DIV Mask
| #define CLK_CLKDIV1_SC2DIV_Pos (16) |
CLK_T::CLKDIV1: SC2DIV Position
| #define CLK_CLKDIV2_EADC1DIV_Msk (0xfful << CLK_CLKDIV2_EADC1DIV_Pos) |
CLK_T::CLKDIV2: EADC1DIV Mask
| #define CLK_CLKDIV2_EADC1DIV_Pos (24) |
CLK_T::CLKDIV2: EADC1DIV Position
| #define CLK_CLKDIV2_I2SDIV_Msk (0xful << CLK_CLKDIV2_I2SDIV_Pos) |
CLK_T::CLKDIV2: I2SDIV Mask
| #define CLK_CLKDIV2_I2SDIV_Pos (0) |
CLK_T::CLKDIV2: I2SDIV Position
| #define CLK_CLKDIV3_CCAPDIV_Msk (0xfful << CLK_CLKDIV3_CCAPDIV_Pos) |
CLK_T::CLKDIV3: CCAPDIV Mask
| #define CLK_CLKDIV3_CCAPDIV_Pos (0) |
CLK_T::CLKDIV3: CCAPDIV Position
| #define CLK_CLKDIV3_EMACDIV_Msk (0xfful << CLK_CLKDIV3_EMACDIV_Pos) |
CLK_T::CLKDIV3: EMACDIV Mask
| #define CLK_CLKDIV3_EMACDIV_Pos (16) |
CLK_T::CLKDIV3: EMACDIV Position
| #define CLK_CLKDIV3_SDH1DIV_Msk (0xfful << CLK_CLKDIV3_SDH1DIV_Pos) |
CLK_T::CLKDIV3: SDH1DIV Mask
| #define CLK_CLKDIV3_SDH1DIV_Pos (24) |
CLK_T::CLKDIV3: SDH1DIV Position
| #define CLK_CLKDIV3_VSENSEDIV_Msk (0xfful << CLK_CLKDIV3_VSENSEDIV_Pos) |
CLK_T::CLKDIV3: VSENSEDIV Mask
| #define CLK_CLKDIV3_VSENSEDIV_Pos (8) |
CLK_T::CLKDIV3: VSENSEDIV Position
| #define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) |
CLK_T::CLKDIV4: UART2DIV Mask
| #define CLK_CLKDIV4_UART2DIV_Pos (0) |
CLK_T::CLKDIV4: UART2DIV Position
| #define CLK_CLKDIV4_UART3DIV_Msk (0xful << CLK_CLKDIV4_UART3DIV_Pos) |
CLK_T::CLKDIV4: UART3DIV Mask
| #define CLK_CLKDIV4_UART3DIV_Pos (4) |
CLK_T::CLKDIV4: UART3DIV Position
| #define CLK_CLKDIV4_UART4DIV_Msk (0xful << CLK_CLKDIV4_UART4DIV_Pos) |
CLK_T::CLKDIV4: UART4DIV Mask
| #define CLK_CLKDIV4_UART4DIV_Pos (8) |
CLK_T::CLKDIV4: UART4DIV Position
| #define CLK_CLKDIV4_UART5DIV_Msk (0xful << CLK_CLKDIV4_UART5DIV_Pos) |
CLK_T::CLKDIV4: UART5DIV Mask
| #define CLK_CLKDIV4_UART5DIV_Pos (12) |
CLK_T::CLKDIV4: UART5DIV Position
| #define CLK_CLKDIV4_UART6DIV_Msk (0xful << CLK_CLKDIV4_UART6DIV_Pos) |
CLK_T::CLKDIV4: UART6DIV Mask
| #define CLK_CLKDIV4_UART6DIV_Pos (16) |
CLK_T::CLKDIV4: UART6DIV Position
| #define CLK_CLKDIV4_UART7DIV_Msk (0xful << CLK_CLKDIV4_UART7DIV_Pos) |
CLK_T::CLKDIV4: UART7DIV Mask
| #define CLK_CLKDIV4_UART7DIV_Pos (20) |
CLK_T::CLKDIV4: UART7DIV Position
| #define CLK_CLKDSTS_HXTFIF_Msk (0x1ul << CLK_CLKDSTS_HXTFIF_Pos) |
CLK_T::CLKDSTS: HXTFIF Mask
| #define CLK_CLKDSTS_HXTFIF_Pos (0) |
CLK_T::CLKDSTS: HXTFIF Position
| #define CLK_CLKDSTS_HXTFQIF_Msk (0x1ul << CLK_CLKDSTS_HXTFQIF_Pos) |
CLK_T::CLKDSTS: HXTFQIF Mask
| #define CLK_CLKDSTS_HXTFQIF_Pos (8) |
CLK_T::CLKDSTS: HXTFQIF Position
| #define CLK_CLKDSTS_LXTFIF_Msk (0x1ul << CLK_CLKDSTS_LXTFIF_Pos) |
CLK_T::CLKDSTS: LXTFIF Mask
| #define CLK_CLKDSTS_LXTFIF_Pos (1) |
CLK_T::CLKDSTS: LXTFIF Position
| #define CLK_CLKOCTL_CLK1HZEN_Msk (0x1ul << CLK_CLKOCTL_CLK1HZEN_Pos) |
CLK_T::CLKOCTL: CLK1HZEN Mask
| #define CLK_CLKOCTL_CLK1HZEN_Pos (6) |
CLK_T::CLKOCTL: CLK1HZEN Position
| #define CLK_CLKOCTL_CLKOEN_Msk (0x1ul << CLK_CLKOCTL_CLKOEN_Pos) |
CLK_T::CLKOCTL: CLKOEN Mask
| #define CLK_CLKOCTL_CLKOEN_Pos (4) |
CLK_T::CLKOCTL: CLKOEN Position
| #define CLK_CLKOCTL_DIV1EN_Msk (0x1ul << CLK_CLKOCTL_DIV1EN_Pos) |
CLK_T::CLKOCTL: DIV1EN Mask
| #define CLK_CLKOCTL_DIV1EN_Pos (5) |
CLK_T::CLKOCTL: DIV1EN Position
| #define CLK_CLKOCTL_FREQSEL_Msk (0xful << CLK_CLKOCTL_FREQSEL_Pos) |
CLK_T::CLKOCTL: FREQSEL Mask
| #define CLK_CLKOCTL_FREQSEL_Pos (0) |
CLK_T::CLKOCTL: FREQSEL Position
| #define CLK_CLKSEL0_CCAPSEL_Msk (0x3ul << CLK_CLKSEL0_CCAPSEL_Pos) |
CLK_T::CLKSEL0: CCAPSEL Mask
| #define CLK_CLKSEL0_CCAPSEL_Pos (16) |
CLK_T::CLKSEL0: CCAPSEL Position
| #define CLK_CLKSEL0_HCLKSEL_Msk (0x7ul << CLK_CLKSEL0_HCLKSEL_Pos) |
CLK_T::CLKSEL0: HCLKSEL Mask
| #define CLK_CLKSEL0_HCLKSEL_Pos (0) |
CLK_T::CLKSEL0: HCLKSEL Position
| #define CLK_CLKSEL0_SDH0SEL_Msk (0x3ul << CLK_CLKSEL0_SDH0SEL_Pos) |
CLK_T::CLKSEL0: SDH0SEL Mask
| #define CLK_CLKSEL0_SDH0SEL_Pos (20) |
CLK_T::CLKSEL0: SDH0SEL Position
| #define CLK_CLKSEL0_SDH1SEL_Msk (0x3ul << CLK_CLKSEL0_SDH1SEL_Pos) |
CLK_T::CLKSEL0: SDH1SEL Mask
| #define CLK_CLKSEL0_SDH1SEL_Pos (22) |
CLK_T::CLKSEL0: SDH1SEL Position
| #define CLK_CLKSEL0_STCLKSEL_Msk (0x7ul << CLK_CLKSEL0_STCLKSEL_Pos) |
CLK_T::CLKSEL0: STCLKSEL Mask
| #define CLK_CLKSEL0_STCLKSEL_Pos (3) |
CLK_T::CLKSEL0: STCLKSEL Position
| #define CLK_CLKSEL0_USBSEL_Msk (0x1ul << CLK_CLKSEL0_USBSEL_Pos) |
CLK_T::CLKSEL0: PCLK0SEL Mask
| #define CLK_CLKSEL0_USBSEL_Pos (8) |
CLK_T::CLKSEL0: PCLK0SEL Position
| #define CLK_CLKSEL1_CLKOSEL_Msk (0x3ul << CLK_CLKSEL1_CLKOSEL_Pos) |
CLK_T::CLKSEL1: CLKOSEL Mask
| #define CLK_CLKSEL1_CLKOSEL_Pos (28) |
CLK_T::CLKSEL1: CLKOSEL Position
| #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) |
CLK_T::CLKSEL1: TMR0SEL Mask
| #define CLK_CLKSEL1_TMR0SEL_Pos (8) |
CLK_T::CLKSEL1: TMR0SEL Position
| #define CLK_CLKSEL1_TMR1SEL_Msk (0x7ul << CLK_CLKSEL1_TMR1SEL_Pos) |
CLK_T::CLKSEL1: TMR1SEL Mask
| #define CLK_CLKSEL1_TMR1SEL_Pos (12) |
CLK_T::CLKSEL1: TMR1SEL Position
| #define CLK_CLKSEL1_TMR2SEL_Msk (0x7ul << CLK_CLKSEL1_TMR2SEL_Pos) |
CLK_T::CLKSEL1: TMR2SEL Mask
| #define CLK_CLKSEL1_TMR2SEL_Pos (16) |
CLK_T::CLKSEL1: TMR2SEL Position
| #define CLK_CLKSEL1_TMR3SEL_Msk (0x7ul << CLK_CLKSEL1_TMR3SEL_Pos) |
CLK_T::CLKSEL1: TMR3SEL Mask
| #define CLK_CLKSEL1_TMR3SEL_Pos (20) |
CLK_T::CLKSEL1: TMR3SEL Position
| #define CLK_CLKSEL1_UART0SEL_Msk (0x3ul << CLK_CLKSEL1_UART0SEL_Pos) |
CLK_T::CLKSEL1: UART0SEL Mask
| #define CLK_CLKSEL1_UART0SEL_Pos (24) |
CLK_T::CLKSEL1: UART0SEL Position
| #define CLK_CLKSEL1_UART1SEL_Msk (0x3ul << CLK_CLKSEL1_UART1SEL_Pos) |
CLK_T::CLKSEL1: UART1SEL Mask
| #define CLK_CLKSEL1_UART1SEL_Pos (26) |
CLK_T::CLKSEL1: UART1SEL Position
| #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) |
CLK_T::CLKSEL1: WDTSEL Mask
| #define CLK_CLKSEL1_WDTSEL_Pos (0) |
CLK_T::CLKSEL1: WDTSEL Position
| #define CLK_CLKSEL1_WWDTSEL_Msk (0x3ul << CLK_CLKSEL1_WWDTSEL_Pos) |
CLK_T::CLKSEL1: WWDTSEL Mask
| #define CLK_CLKSEL1_WWDTSEL_Pos (30) |
CLK_T::CLKSEL1: WWDTSEL Position
| #define CLK_CLKSEL2_BPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM0SEL_Pos) |
CLK_T::CLKSEL2: BPWM0SEL Mask
| #define CLK_CLKSEL2_BPWM0SEL_Pos (8) |
CLK_T::CLKSEL2: BPWM0SEL Position
| #define CLK_CLKSEL2_BPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_BPWM1SEL_Pos) |
CLK_T::CLKSEL2: BPWM1SEL Mask
| #define CLK_CLKSEL2_BPWM1SEL_Pos (9) |
CLK_T::CLKSEL2: BPWM1SEL Position
| #define CLK_CLKSEL2_EPWM0SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM0SEL_Pos) |
CLK_T::CLKSEL2: EPWM0SEL Mask
| #define CLK_CLKSEL2_EPWM0SEL_Pos (0) |
CLK_T::CLKSEL2: EPWM0SEL Position
| #define CLK_CLKSEL2_EPWM1SEL_Msk (0x1ul << CLK_CLKSEL2_EPWM1SEL_Pos) |
CLK_T::CLKSEL2: EPWM1SEL Mask
| #define CLK_CLKSEL2_EPWM1SEL_Pos (1) |
CLK_T::CLKSEL2: EPWM1SEL Position
| #define CLK_CLKSEL2_QSPI0SEL_Msk (0x3ul << CLK_CLKSEL2_QSPI0SEL_Pos) |
CLK_T::CLKSEL2: QSPI0SEL Mask
| #define CLK_CLKSEL2_QSPI0SEL_Pos (2) |
CLK_T::CLKSEL2: QSPI0SEL Position
| #define CLK_CLKSEL2_SPI0SEL_Msk (0x3ul << CLK_CLKSEL2_SPI0SEL_Pos) |
CLK_T::CLKSEL2: SPI0SEL Mask
| #define CLK_CLKSEL2_SPI0SEL_Pos (4) |
CLK_T::CLKSEL2: SPI0SEL Position
| #define CLK_CLKSEL2_SPI1SEL_Msk (0x3ul << CLK_CLKSEL2_SPI1SEL_Pos) |
CLK_T::CLKSEL2: SPI1SEL Mask
| #define CLK_CLKSEL2_SPI1SEL_Pos (6) |
CLK_T::CLKSEL2: SPI1SEL Position
| #define CLK_CLKSEL2_SPI2SEL_Msk (0x3ul << CLK_CLKSEL2_SPI2SEL_Pos) |
CLK_T::CLKSEL2: SPI2SEL Mask
| #define CLK_CLKSEL2_SPI2SEL_Pos (10) |
CLK_T::CLKSEL2: SPI2SEL Position
| #define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) |
CLK_T::CLKSEL2: SPI3SEL Mask
| #define CLK_CLKSEL2_SPI3SEL_Pos (12) |
CLK_T::CLKSEL2: SPI3SEL Position
| #define CLK_CLKSEL3_I2S0SEL_Msk (0x3ul << CLK_CLKSEL3_I2S0SEL_Pos) |
CLK_T::CLKSEL3: I2S0SEL Mask
| #define CLK_CLKSEL3_I2S0SEL_Pos (16) |
CLK_T::CLKSEL3: I2S0SEL Position
| #define CLK_CLKSEL3_QSPI1SEL_Msk (0x3ul << CLK_CLKSEL3_QSPI1SEL_Pos) |
CLK_T::CLKSEL3: QSPI1SEL Mask
| #define CLK_CLKSEL3_QSPI1SEL_Pos (12) |
CLK_T::CLKSEL3: QSPI1SEL Position
| #define CLK_CLKSEL3_RTCSEL_Msk (0x1ul << CLK_CLKSEL3_RTCSEL_Pos) |
CLK_T::CLKSEL3: RTCSEL Mask
| #define CLK_CLKSEL3_RTCSEL_Pos (8) |
CLK_T::CLKSEL3: RTCSEL Position
| #define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) |
CLK_T::CLKSEL3: SC0SEL Mask
| #define CLK_CLKSEL3_SC0SEL_Pos (0) |
CLK_T::CLKSEL3: SC0SEL Position
| #define CLK_CLKSEL3_SC1SEL_Msk (0x3ul << CLK_CLKSEL3_SC1SEL_Pos) |
CLK_T::CLKSEL3: SC1SEL Mask
| #define CLK_CLKSEL3_SC1SEL_Pos (2) |
CLK_T::CLKSEL3: SC1SEL Position
| #define CLK_CLKSEL3_SC2SEL_Msk (0x3ul << CLK_CLKSEL3_SC2SEL_Pos) |
CLK_T::CLKSEL3: SC2SEL Mask
| #define CLK_CLKSEL3_SC2SEL_Pos (4) |
CLK_T::CLKSEL3: SC2SEL Position
| #define CLK_CLKSEL3_UART2SEL_Msk (0x3ul << CLK_CLKSEL3_UART2SEL_Pos) |
CLK_T::CLKSEL3: UART2SEL Mask
| #define CLK_CLKSEL3_UART2SEL_Pos (24) |
CLK_T::CLKSEL3: UART2SEL Position
| #define CLK_CLKSEL3_UART3SEL_Msk (0x3ul << CLK_CLKSEL3_UART3SEL_Pos) |
CLK_T::CLKSEL3: UART3SEL Mask
| #define CLK_CLKSEL3_UART3SEL_Pos (26) |
CLK_T::CLKSEL3: UART3SEL Position
| #define CLK_CLKSEL3_UART4SEL_Msk (0x3ul << CLK_CLKSEL3_UART4SEL_Pos) |
CLK_T::CLKSEL3: UART4SEL Mask
| #define CLK_CLKSEL3_UART4SEL_Pos (28) |
CLK_T::CLKSEL3: UART4SEL Position
| #define CLK_CLKSEL3_UART5SEL_Msk (0x3ul << CLK_CLKSEL3_UART5SEL_Pos) |
CLK_T::CLKSEL3: UART5SEL Mask
| #define CLK_CLKSEL3_UART5SEL_Pos (30) |
CLK_T::CLKSEL3: UART5SEL Position
| #define CLK_CLKSEL3_UART6SEL_Msk (0x3ul << CLK_CLKSEL3_UART6SEL_Pos) |
CLK_T::CLKSEL3: UART6SEL Mask
| #define CLK_CLKSEL3_UART6SEL_Pos (20) |
CLK_T::CLKSEL3: UART6SEL Position
| #define CLK_CLKSEL3_UART7SEL_Msk (0x3ul << CLK_CLKSEL3_UART7SEL_Pos) |
CLK_T::CLKSEL3: UART7SEL Mask
| #define CLK_CLKSEL3_UART7SEL_Pos (22) |
CLK_T::CLKSEL3: UART7SEL Position
| #define CLK_IOPDCTL_IOHR_Msk (0x1ul << CLK_IOPDCTL_IOHR_Pos) |
CLK_T::IOPDCTL: IOHR Mask
| #define CLK_IOPDCTL_IOHR_Pos (0) |
CLK_T::IOPDCTL: IOHR Position
| #define CLK_LDOCTL_PDBIASEN_Msk (0x1ul << CLK_LDOCTL_PDBIASEN_Pos) |
CLK_T::LDOCTL: PDBIASEN Mask
| #define CLK_LDOCTL_PDBIASEN_Pos (18) |
CLK_T::LDOCTL: PDBIASEN Position
| #define CLK_PASWKCTL_DBEN_Msk (0x1ul << CLK_PASWKCTL_DBEN_Pos) |
CLK_T::PASWKCTL: DBEN Mask
| #define CLK_PASWKCTL_DBEN_Pos (8) |
CLK_T::PASWKCTL: DBEN Position
| #define CLK_PASWKCTL_PFWKEN_Msk (0x1ul << CLK_PASWKCTL_PFWKEN_Pos) |
CLK_T::PASWKCTL: PFWKEN Mask
| #define CLK_PASWKCTL_PFWKEN_Pos (2) |
CLK_T::PASWKCTL: PFWKEN Position
| #define CLK_PASWKCTL_PRWKEN_Msk (0x1ul << CLK_PASWKCTL_PRWKEN_Pos) |
CLK_T::PASWKCTL: PRWKEN Mask
| #define CLK_PASWKCTL_PRWKEN_Pos (1) |
CLK_T::PASWKCTL: PRWKEN Position
| #define CLK_PASWKCTL_WKEN_Msk (0x1ul << CLK_PASWKCTL_WKEN_Pos) |
CLK_T::PASWKCTL: WKEN Mask
| #define CLK_PASWKCTL_WKEN_Pos (0) |
CLK_T::PASWKCTL: WKEN Position
| #define CLK_PASWKCTL_WKPSEL_Msk (0xful << CLK_PASWKCTL_WKPSEL_Pos) |
CLK_T::PASWKCTL: WKPSEL Mask
| #define CLK_PASWKCTL_WKPSEL_Pos (4) |
CLK_T::PASWKCTL: WKPSEL Position
| #define CLK_PBSWKCTL_DBEN_Msk (0x1ul << CLK_PBSWKCTL_DBEN_Pos) |
CLK_T::PBSWKCTL: DBEN Mask
| #define CLK_PBSWKCTL_DBEN_Pos (8) |
CLK_T::PBSWKCTL: DBEN Position
| #define CLK_PBSWKCTL_PFWKEN_Msk (0x1ul << CLK_PBSWKCTL_PFWKEN_Pos) |
CLK_T::PBSWKCTL: PFWKEN Mask
| #define CLK_PBSWKCTL_PFWKEN_Pos (2) |
CLK_T::PBSWKCTL: PFWKEN Position
| #define CLK_PBSWKCTL_PRWKEN_Msk (0x1ul << CLK_PBSWKCTL_PRWKEN_Pos) |
CLK_T::PBSWKCTL: PRWKEN Mask
| #define CLK_PBSWKCTL_PRWKEN_Pos (1) |
CLK_T::PBSWKCTL: PRWKEN Position
| #define CLK_PBSWKCTL_WKEN_Msk (0x1ul << CLK_PBSWKCTL_WKEN_Pos) |
CLK_T::PBSWKCTL: WKEN Mask
| #define CLK_PBSWKCTL_WKEN_Pos (0) |
CLK_T::PBSWKCTL: WKEN Position
| #define CLK_PBSWKCTL_WKPSEL_Msk (0xful << CLK_PBSWKCTL_WKPSEL_Pos) |
CLK_T::PBSWKCTL: WKPSEL Mask
| #define CLK_PBSWKCTL_WKPSEL_Pos (4) |
CLK_T::PBSWKCTL: WKPSEL Position
| #define CLK_PCLKDIV_APB0DIV_Msk (0x7ul << CLK_PCLKDIV_APB0DIV_Pos) |
CLK_T::PCLKDIV: APB0DIV Mask
| #define CLK_PCLKDIV_APB0DIV_Pos (0) |
CLK_T::PCLKDIV: APB0DIV Position
| #define CLK_PCLKDIV_APB1DIV_Msk (0x7ul << CLK_PCLKDIV_APB1DIV_Pos) |
CLK_T::PCLKDIV: APB1DIV Mask
| #define CLK_PCLKDIV_APB1DIV_Pos (4) |
CLK_T::PCLKDIV: APB1DIV Position
| #define CLK_PCSWKCTL_DBEN_Msk (0x1ul << CLK_PCSWKCTL_DBEN_Pos) |
CLK_T::PCSWKCTL: DBEN Mask
| #define CLK_PCSWKCTL_DBEN_Pos (8) |
CLK_T::PCSWKCTL: DBEN Position
| #define CLK_PCSWKCTL_PFWKEN_Msk (0x1ul << CLK_PCSWKCTL_PFWKEN_Pos) |
CLK_T::PCSWKCTL: PFWKEN Mask
| #define CLK_PCSWKCTL_PFWKEN_Pos (2) |
CLK_T::PCSWKCTL: PFWKEN Position
| #define CLK_PCSWKCTL_PRWKEN_Msk (0x1ul << CLK_PCSWKCTL_PRWKEN_Pos) |
CLK_T::PCSWKCTL: PRWKEN Mask
| #define CLK_PCSWKCTL_PRWKEN_Pos (1) |
CLK_T::PCSWKCTL: PRWKEN Position
| #define CLK_PCSWKCTL_WKEN_Msk (0x1ul << CLK_PCSWKCTL_WKEN_Pos) |
CLK_T::PCSWKCTL: WKEN Mask
| #define CLK_PCSWKCTL_WKEN_Pos (0) |
CLK_T::PCSWKCTL: WKEN Position
| #define CLK_PCSWKCTL_WKPSEL_Msk (0xful << CLK_PCSWKCTL_WKPSEL_Pos) |
CLK_T::PCSWKCTL: WKPSEL Mask
| #define CLK_PCSWKCTL_WKPSEL_Pos (4) |
CLK_T::PCSWKCTL: WKPSEL Position
| #define CLK_PDSWKCTL_DBEN_Msk (0x1ul << CLK_PDSWKCTL_DBEN_Pos) |
CLK_T::PDSWKCTL: DBEN Mask
| #define CLK_PDSWKCTL_DBEN_Pos (8) |
CLK_T::PDSWKCTL: DBEN Position
| #define CLK_PDSWKCTL_PFWKEN_Msk (0x1ul << CLK_PDSWKCTL_PFWKEN_Pos) |
CLK_T::PDSWKCTL: PFWKEN Mask
| #define CLK_PDSWKCTL_PFWKEN_Pos (2) |
CLK_T::PDSWKCTL: PFWKEN Position
| #define CLK_PDSWKCTL_PRWKEN_Msk (0x1ul << CLK_PDSWKCTL_PRWKEN_Pos) |
CLK_T::PDSWKCTL: PRWKEN Mask
| #define CLK_PDSWKCTL_PRWKEN_Pos (1) |
CLK_T::PDSWKCTL: PRWKEN Position
| #define CLK_PDSWKCTL_WKEN_Msk (0x1ul << CLK_PDSWKCTL_WKEN_Pos) |
CLK_T::PDSWKCTL: WKEN Mask
| #define CLK_PDSWKCTL_WKEN_Pos (0) |
CLK_T::PDSWKCTL: WKEN Position
| #define CLK_PDSWKCTL_WKPSEL_Msk (0xful << CLK_PDSWKCTL_WKPSEL_Pos) |
CLK_T::PDSWKCTL: WKPSEL Mask
| #define CLK_PDSWKCTL_WKPSEL_Pos (4) |
CLK_T::PDSWKCTL: WKPSEL Position
| #define CLK_PLLCTL_BP_Msk (0x1ul << CLK_PLLCTL_BP_Pos) |
CLK_T::PLLCTL: BP Mask
| #define CLK_PLLCTL_BP_Pos (17) |
CLK_T::PLLCTL: BP Position
| #define CLK_PLLCTL_FBDIV_Msk (0x1fful << CLK_PLLCTL_FBDIV_Pos) |
CLK_T::PLLCTL: FBDIV Mask
| #define CLK_PLLCTL_FBDIV_Pos (0) |
CLK_T::PLLCTL: FBDIV Position
| #define CLK_PLLCTL_INDIV_Msk (0x1ful << CLK_PLLCTL_INDIV_Pos) |
CLK_T::PLLCTL: INDIV Mask
| #define CLK_PLLCTL_INDIV_Pos (9) |
CLK_T::PLLCTL: INDIV Position
| #define CLK_PLLCTL_OE_Msk (0x1ul << CLK_PLLCTL_OE_Pos) |
CLK_T::PLLCTL: OE Mask
| #define CLK_PLLCTL_OE_Pos (18) |
CLK_T::PLLCTL: OE Position
| #define CLK_PLLCTL_OUTDIV_Msk (0x3ul << CLK_PLLCTL_OUTDIV_Pos) |
CLK_T::PLLCTL: OUTDIV Mask
| #define CLK_PLLCTL_OUTDIV_Pos (14) |
CLK_T::PLLCTL: OUTDIV Position
| #define CLK_PLLCTL_PD_Msk (0x1ul << CLK_PLLCTL_PD_Pos) |
CLK_T::PLLCTL: PD Mask
| #define CLK_PLLCTL_PD_Pos (16) |
CLK_T::PLLCTL: PD Position
| #define CLK_PLLCTL_PLLSRC_Msk (0x1ul << CLK_PLLCTL_PLLSRC_Pos) |
CLK_T::PLLCTL: PLLSRC Mask
| #define CLK_PLLCTL_PLLSRC_Pos (19) |
CLK_T::PLLCTL: PLLSRC Position
| #define CLK_PLLCTL_STBSEL_Msk (0x1ul << CLK_PLLCTL_STBSEL_Pos) |
CLK_T::PLLCTL: STBSEL Mask
| #define CLK_PLLCTL_STBSEL_Pos (23) |
CLK_T::PLLCTL: STBSEL Position
| #define CLK_PMUCTL_ACMPSPWK_Msk (0x1ul << CLK_PMUCTL_ACMPSPWK_Pos) |
CLK_T::PMUCTL: ACMPSPWK Mask
| #define CLK_PMUCTL_ACMPSPWK_Pos (18) |
CLK_T::PMUCTL: ACMPSPWK Position
| #define CLK_PMUCTL_DPDHOLDEN_Msk (0x1ul << CLK_PMUCTL_DPDHOLDEN_Pos) |
CLK_T::PMUCTL: DPDHOLDEN Mask
| #define CLK_PMUCTL_DPDHOLDEN_Pos (3) |
CLK_T::PMUCTL: DPDHOLDEN Position
| #define CLK_PMUCTL_PDMSEL_Msk (0x7ul << CLK_PMUCTL_PDMSEL_Pos) |
CLK_T::PMUCTL: PDMSEL Mask
| #define CLK_PMUCTL_PDMSEL_Pos (0) |
CLK_T::PMUCTL: PDMSEL Position
| #define CLK_PMUCTL_RTCWKEN_Msk (0x1ul << CLK_PMUCTL_RTCWKEN_Pos) |
CLK_T::PMUCTL: RTCWKEN Mask
| #define CLK_PMUCTL_RTCWKEN_Pos (23) |
CLK_T::PMUCTL: RTCWKEN Position
| #define CLK_PMUCTL_SRETSEL_Msk (0x7ul << CLK_PMUCTL_SRETSEL_Pos) |
CLK_T::PMUCTL: SRETSEL Mask
| #define CLK_PMUCTL_SRETSEL_Pos (4) |
CLK_T::PMUCTL: SRETSEL Position
| #define CLK_PMUCTL_WKPINEN1_Msk (0x3ul << CLK_PMUCTL_WKPINEN1_Pos) |
CLK_T::PMUCTL: WKPINEN1 Mask
| #define CLK_PMUCTL_WKPINEN1_Pos (24) |
CLK_T::PMUCTL: WKPINEN1 Position
| #define CLK_PMUCTL_WKPINEN2_Msk (0x3ul << CLK_PMUCTL_WKPINEN2_Pos) |
CLK_T::PMUCTL: WKPINEN2 Mask
| #define CLK_PMUCTL_WKPINEN2_Pos (26) |
CLK_T::PMUCTL: WKPINEN2 Position
| #define CLK_PMUCTL_WKPINEN3_Msk (0x3ul << CLK_PMUCTL_WKPINEN3_Pos) |
CLK_T::PMUCTL: WKPINEN3 Mask
| #define CLK_PMUCTL_WKPINEN3_Pos (28) |
CLK_T::PMUCTL: WKPINEN3 Position
| #define CLK_PMUCTL_WKPINEN4_Msk (0x3ul << CLK_PMUCTL_WKPINEN4_Pos) |
CLK_T::PMUCTL: WKPINEN4 Mask
| #define CLK_PMUCTL_WKPINEN4_Pos (30) |
CLK_T::PMUCTL: WKPINEN4 Position
| #define CLK_PMUCTL_WKPINEN_Msk (0x3ul << CLK_PMUCTL_WKPINEN_Pos) |
CLK_T::PMUCTL: WKPINEN Mask
| #define CLK_PMUCTL_WKPINEN_Pos (16) |
CLK_T::PMUCTL: WKPINEN Position
| #define CLK_PMUCTL_WKTMREN_Msk (0x1ul << CLK_PMUCTL_WKTMREN_Pos) |
CLK_T::PMUCTL: WKTMREN Mask
| #define CLK_PMUCTL_WKTMREN_Pos (8) |
CLK_T::PMUCTL: WKTMREN Position
| #define CLK_PMUCTL_WKTMRIS_Msk (0xful << CLK_PMUCTL_WKTMRIS_Pos) |
CLK_T::PMUCTL: WKTMRIS Mask
| #define CLK_PMUCTL_WKTMRIS_Pos (9) |
CLK_T::PMUCTL: WKTMRIS Position
| #define CLK_PMUSTS_ACMPWK_Msk (0x1ul << CLK_PMUSTS_ACMPWK_Pos) |
CLK_T::PMUSTS: ACMPWK Mask
| #define CLK_PMUSTS_ACMPWK_Pos (14) |
CLK_T::PMUSTS: ACMPWK Position
| #define CLK_PMUSTS_BODWK_Msk (0x1ul << CLK_PMUSTS_BODWK_Pos) |
CLK_T::PMUSTS: BODWK Mask
| #define CLK_PMUSTS_BODWK_Pos (13) |
CLK_T::PMUSTS: BODWK Position
| #define CLK_PMUSTS_CLRWK_Msk (0x1ul << CLK_PMUSTS_CLRWK_Pos) |
CLK_T::PMUSTS: CLRWK Mask
| #define CLK_PMUSTS_CLRWK_Pos (31) |
CLK_T::PMUSTS: CLRWK Position
| #define CLK_PMUSTS_GPAWK_Msk (0x1ul << CLK_PMUSTS_GPAWK_Pos) |
CLK_T::PMUSTS: GPAWK Mask
| #define CLK_PMUSTS_GPAWK_Pos (8) |
CLK_T::PMUSTS: GPAWK Position
| #define CLK_PMUSTS_GPBWK_Msk (0x1ul << CLK_PMUSTS_GPBWK_Pos) |
CLK_T::PMUSTS: GPBWK Mask
| #define CLK_PMUSTS_GPBWK_Pos (9) |
CLK_T::PMUSTS: GPBWK Position
| #define CLK_PMUSTS_GPCWK_Msk (0x1ul << CLK_PMUSTS_GPCWK_Pos) |
CLK_T::PMUSTS: GPCWK Mask
| #define CLK_PMUSTS_GPCWK_Pos (10) |
CLK_T::PMUSTS: GPCWK Position
| #define CLK_PMUSTS_GPDWK_Msk (0x1ul << CLK_PMUSTS_GPDWK_Pos) |
CLK_T::PMUSTS: GPDWK Mask
| #define CLK_PMUSTS_GPDWK_Pos (11) |
CLK_T::PMUSTS: GPDWK Position
| #define CLK_PMUSTS_LVRWK_Msk (0x1ul << CLK_PMUSTS_LVRWK_Pos) |
CLK_T::PMUSTS: LVRWK Mask
| #define CLK_PMUSTS_LVRWK_Pos (12) |
CLK_T::PMUSTS: LVRWK Position
| #define CLK_PMUSTS_PINWK1_Msk (0x1ul << CLK_PMUSTS_PINWK1_Pos) |
CLK_T::PMUSTS: PINWK1 Mask
| #define CLK_PMUSTS_PINWK1_Pos (3) |
CLK_T::PMUSTS: PINWK1 Position
| #define CLK_PMUSTS_PINWK2_Msk (0x1ul << CLK_PMUSTS_PINWK2_Pos) |
CLK_T::PMUSTS: PINWK2 Mask
| #define CLK_PMUSTS_PINWK2_Pos (4) |
CLK_T::PMUSTS: PINWK2 Position
| #define CLK_PMUSTS_PINWK3_Msk (0x1ul << CLK_PMUSTS_PINWK3_Pos) |
CLK_T::PMUSTS: PINWK3 Mask
| #define CLK_PMUSTS_PINWK3_Pos (5) |
CLK_T::PMUSTS: PINWK3 Position
| #define CLK_PMUSTS_PINWK4_Msk (0x1ul << CLK_PMUSTS_PINWK4_Pos) |
CLK_T::PMUSTS: PINWK4 Mask
| #define CLK_PMUSTS_PINWK4_Pos (6) |
CLK_T::PMUSTS: PINWK4 Position
| #define CLK_PMUSTS_PINWK_Msk (0x1ul << CLK_PMUSTS_PINWK_Pos) |
CLK_T::PMUSTS: PINWK Mask
| #define CLK_PMUSTS_PINWK_Pos (0) |
CLK_T::PMUSTS: PINWK Position
| #define CLK_PMUSTS_RTCWK_Msk (0x1ul << CLK_PMUSTS_RTCWK_Pos) |
CLK_T::PMUSTS: RTCWK Mask
| #define CLK_PMUSTS_RTCWK_Pos (2) |
CLK_T::PMUSTS: RTCWK Position
| #define CLK_PMUSTS_TMRWK_Msk (0x1ul << CLK_PMUSTS_TMRWK_Pos) |
CLK_T::PMUSTS: TMRWK Mask
| #define CLK_PMUSTS_TMRWK_Pos (1) |
CLK_T::PMUSTS: TMRWK Position
| #define CLK_PWRCTL_HIRC48MEN_Msk (0x1ul << CLK_PWRCTL_HIRC48MEN_Pos) |
CLK_T::PWRCTL: HIRC48MEN Mask
| #define CLK_PWRCTL_HIRC48MEN_Pos (18) |
CLK_T::PWRCTL: HIRC48MEN Position
| #define CLK_PWRCTL_HIRCEN_Msk (0x1ul << CLK_PWRCTL_HIRCEN_Pos) |
CLK_T::PWRCTL: HIRCEN Mask
| #define CLK_PWRCTL_HIRCEN_Pos (2) |
CLK_T::PWRCTL: HIRCEN Position
| #define CLK_PWRCTL_HIRCSTBS_Msk (0x3ul << CLK_PWRCTL_HIRCSTBS_Pos) |
CLK_T::PWRCTL: HIRCSTBS Mask
| #define CLK_PWRCTL_HIRCSTBS_Pos (16) |
CLK_T::PWRCTL: HIRCSTBS Position
| #define CLK_PWRCTL_HXTEN_Msk (0x1ul << CLK_PWRCTL_HXTEN_Pos) |
CLK_T::PWRCTL: HXTEN Mask
| #define CLK_PWRCTL_HXTEN_Pos (0) |
@addtogroup CLK_CONST CLK Bit Field Definition Constant Definitions for CLK Controller
CLK_T::PWRCTL: HXTEN Position
| #define CLK_PWRCTL_HXTGAIN_Msk (0x3ul << CLK_PWRCTL_HXTGAIN_Pos) |
CLK_T::PWRCTL: HXTGAIN Mask
| #define CLK_PWRCTL_HXTGAIN_Pos (10) |
CLK_T::PWRCTL: HXTGAIN Position
| #define CLK_PWRCTL_HXTSELTYP_Msk (0x1ul << CLK_PWRCTL_HXTSELTYP_Pos) |
CLK_T::PWRCTL: HXTSELTYP Mask
| #define CLK_PWRCTL_HXTSELTYP_Pos (12) |
CLK_T::PWRCTL: HXTSELTYP Position
| #define CLK_PWRCTL_HXTTBEN_Msk (0x1ul << CLK_PWRCTL_HXTTBEN_Pos) |
CLK_T::PWRCTL: HXTTBEN Mask
| #define CLK_PWRCTL_HXTTBEN_Pos (13) |
CLK_T::PWRCTL: HXTTBEN Position
| #define CLK_PWRCTL_LIRCEN_Msk (0x1ul << CLK_PWRCTL_LIRCEN_Pos) |
CLK_T::PWRCTL: LIRCEN Mask
| #define CLK_PWRCTL_LIRCEN_Pos (3) |
CLK_T::PWRCTL: LIRCEN Position
| #define CLK_PWRCTL_LXTEN_Msk (0x1ul << CLK_PWRCTL_LXTEN_Pos) |
CLK_T::PWRCTL: LXTEN Mask
| #define CLK_PWRCTL_LXTEN_Pos (1) |
CLK_T::PWRCTL: LXTEN Position
| #define CLK_PWRCTL_PDEN_Msk (0x1ul << CLK_PWRCTL_PDEN_Pos) |
CLK_T::PWRCTL: PDEN Mask
| #define CLK_PWRCTL_PDEN_Pos (7) |
CLK_T::PWRCTL: PDEN Position
| #define CLK_PWRCTL_PDWKDLY_Msk (0x1ul << CLK_PWRCTL_PDWKDLY_Pos) |
CLK_T::PWRCTL: PDWKDLY Mask
| #define CLK_PWRCTL_PDWKDLY_Pos (4) |
CLK_T::PWRCTL: PDWKDLY Position
| #define CLK_PWRCTL_PDWKIEN_Msk (0x1ul << CLK_PWRCTL_PDWKIEN_Pos) |
CLK_T::PWRCTL: PDWKIEN Mask
| #define CLK_PWRCTL_PDWKIEN_Pos (5) |
CLK_T::PWRCTL: PDWKIEN Position
| #define CLK_PWRCTL_PDWKIF_Msk (0x1ul << CLK_PWRCTL_PDWKIF_Pos) |
CLK_T::PWRCTL: PDWKIF Mask
| #define CLK_PWRCTL_PDWKIF_Pos (6) |
CLK_T::PWRCTL: PDWKIF Position
| #define CLK_STATUS_CLKSFAIL_Msk (0x1ul << CLK_STATUS_CLKSFAIL_Pos) |
CLK_T::STATUS: CLKSFAIL Mask
| #define CLK_STATUS_CLKSFAIL_Pos (7) |
CLK_T::STATUS: CLKSFAIL Position
| #define CLK_STATUS_HIRC48MSTB_Msk (0x1ul << CLK_STATUS_HIRC48MSTB_Pos) |
CLK_T::STATUS: HIRC48MSTB Mask
| #define CLK_STATUS_HIRC48MSTB_Pos (6) |
CLK_T::STATUS: HIRC48MSTB Position
| #define CLK_STATUS_HIRCSTB_Msk (0x1ul << CLK_STATUS_HIRCSTB_Pos) |
CLK_T::STATUS: HIRCSTB Mask
| #define CLK_STATUS_HIRCSTB_Pos (4) |
CLK_T::STATUS: HIRCSTB Position
| #define CLK_STATUS_HXTSTB_Msk (0x1ul << CLK_STATUS_HXTSTB_Pos) |
CLK_T::STATUS: HXTSTB Mask
| #define CLK_STATUS_HXTSTB_Pos (0) |
CLK_T::STATUS: HXTSTB Position
| #define CLK_STATUS_LIRCSTB_Msk (0x1ul << CLK_STATUS_LIRCSTB_Pos) |
CLK_T::STATUS: LIRCSTB Mask
| #define CLK_STATUS_LIRCSTB_Pos (3) |
CLK_T::STATUS: LIRCSTB Position
| #define CLK_STATUS_LXTSTB_Msk (0x1ul << CLK_STATUS_LXTSTB_Pos) |
CLK_T::STATUS: LXTSTB Mask
| #define CLK_STATUS_LXTSTB_Pos (1) |
CLK_T::STATUS: LXTSTB Position
| #define CLK_STATUS_PLLSTB_Msk (0x1ul << CLK_STATUS_PLLSTB_Pos) |
CLK_T::STATUS: PLLSTB Mask
| #define CLK_STATUS_PLLSTB_Pos (2) |
CLK_T::STATUS: PLLSTB Position
| #define CLK_SWKDBCTL_SWKDBCLKSEL_Msk (0xful << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) |
CLK_T::SWKDBCTL: SWKDBCLKSEL Mask
| #define CLK_SWKDBCTL_SWKDBCLKSEL_Pos (0) |
CLK_T::SWKDBCTL: SWKDBCLKSEL Position
| #define CRC_CHECKSUM_CHECKSUM_Msk (0xfffffffful << CRC_CHECKSUM_CHECKSUM_Pos) |
CRC_T::CHECKSUM: CHECKSUM Mask
| #define CRC_CHECKSUM_CHECKSUM_Pos (0) |
CRC_T::CHECKSUM: CHECKSUM Position
| #define CRC_CTL_CHKSFMT_Msk (0x1ul << CRC_CTL_CHKSFMT_Pos) |
CRC_T::CTL: CHKSFMT Mask
| #define CRC_CTL_CHKSFMT_Pos (27) |
CRC_T::CTL: CHKSFMT Position
| #define CRC_CTL_CHKSINIT_Msk (0x1ul << CRC_CTL_CHKSINIT_Pos) |
CRC_T::CTL: CHKSINIT Mask
| #define CRC_CTL_CHKSINIT_Pos (1) |
CRC_T::CTL: CHKSINIT Position
| #define CRC_CTL_CHKSREV_Msk (0x1ul << CRC_CTL_CHKSREV_Pos) |
CRC_T::CTL: CHKSREV Mask
| #define CRC_CTL_CHKSREV_Pos (25) |
CRC_T::CTL: CHKSREV Position
| #define CRC_CTL_CRCEN_Msk (0x1ul << CRC_CTL_CRCEN_Pos) |
CRC_T::CTL: CRCEN Mask
| #define CRC_CTL_CRCEN_Pos (0) |
@addtogroup CRC_CONST CRC Bit Field Definition Constant Definitions for CRC Controller
CRC_T::CTL: CRCEN Position
| #define CRC_CTL_CRCMODE_Msk (0x3ul << CRC_CTL_CRCMODE_Pos) |
CRC_T::CTL: CRCMODE Mask
| #define CRC_CTL_CRCMODE_Pos (30) |
CRC_T::CTL: CRCMODE Position
| #define CRC_CTL_DATFMT_Msk (0x1ul << CRC_CTL_DATFMT_Pos) |
CRC_T::CTL: DATFMT Mask
| #define CRC_CTL_DATFMT_Pos (26) |
CRC_T::CTL: DATFMT Position
| #define CRC_CTL_DATLEN_Msk (0x3ul << CRC_CTL_DATLEN_Pos) |
CRC_T::CTL: DATLEN Mask
| #define CRC_CTL_DATLEN_Pos (28) |
CRC_T::CTL: DATLEN Position
| #define CRC_CTL_DATREV_Msk (0x1ul << CRC_CTL_DATREV_Pos) |
CRC_T::CTL: DATREV Mask
| #define CRC_CTL_DATREV_Pos (24) |
CRC_T::CTL: DATREV Position
| #define CRC_DAT_DATA_Msk (0xfffffffful << CRC_DAT_DATA_Pos) |
CRC_T::DAT: DATA Mask
| #define CRC_DAT_DATA_Pos (0) |
CRC_T::DAT: DATA Position
| #define CRC_SEED_SEED_Msk (0xfffffffful << CRC_SEED_SEED_Pos) |
CRC_T::SEED: SEED Mask
| #define CRC_SEED_SEED_Pos (0) |
CRC_T::SEED: SEED Position
| #define EADC_CALCTL_CALDONE_Msk (0x1ul << EADC_CALCTL_CALDONE_Pos) |
EADC_T::CALCTL: CALDONE Mask
Definition at line 1698 of file eadc_reg.h.
| #define EADC_CALCTL_CALDONE_Pos (2) |
EADC_T::CALCTL: CALDONE Position
Definition at line 1697 of file eadc_reg.h.
| #define EADC_CALCTL_CALSEL_Msk (0x1ul << EADC_CALCTL_CALSEL_Pos) |
EADC_T::CALCTL: CALSEL Mask
Definition at line 1701 of file eadc_reg.h.
| #define EADC_CALCTL_CALSEL_Pos (3) |
EADC_T::CALCTL: CALSEL Position
Definition at line 1700 of file eadc_reg.h.
| #define EADC_CALCTL_CALSTART_Msk (0x1ul << EADC_CALCTL_CALSTART_Pos) |
EADC_T::CALCTL: CALSTART Mask
Definition at line 1695 of file eadc_reg.h.
| #define EADC_CALCTL_CALSTART_Pos (1) |
EADC_T::CALCTL: CALSTART Position
Definition at line 1694 of file eadc_reg.h.
| #define EADC_CALDWRD_CALWORD_Msk (0x7ful << EADC_CALDWRD_CALWORD_Pos) |
EADC_T::CALDWRD: CALWORD Mask
Definition at line 1704 of file eadc_reg.h.
| #define EADC_CALDWRD_CALWORD_Pos (0) |
EADC_T::CALDWRD: CALWORD Position
Definition at line 1703 of file eadc_reg.h.
| #define EADC_CMP0_ADCMPEN_Msk (0x1ul << EADC_CMP0_ADCMPEN_Pos) |
EADC_T::CMP0: ADCMPEN Mask
Definition at line 1482 of file eadc_reg.h.
| #define EADC_CMP0_ADCMPEN_Pos (0) |
EADC_T::CMP0: ADCMPEN Position
Definition at line 1481 of file eadc_reg.h.
| #define EADC_CMP0_ADCMPIE_Msk (0x1ul << EADC_CMP0_ADCMPIE_Pos) |
EADC_T::CMP0: ADCMPIE Mask
Definition at line 1485 of file eadc_reg.h.
| #define EADC_CMP0_ADCMPIE_Pos (1) |
EADC_T::CMP0: ADCMPIE Position
Definition at line 1484 of file eadc_reg.h.
| #define EADC_CMP0_CMPCOND_Msk (0x1ul << EADC_CMP0_CMPCOND_Pos) |
EADC_T::CMP0: CMPCOND Mask
Definition at line 1488 of file eadc_reg.h.
| #define EADC_CMP0_CMPCOND_Pos (2) |
EADC_T::CMP0: CMPCOND Position
Definition at line 1487 of file eadc_reg.h.
| #define EADC_CMP0_CMPDAT_Msk (0xffful << EADC_CMP0_CMPDAT_Pos) |
EADC_T::CMP0: CMPDAT Mask
Definition at line 1500 of file eadc_reg.h.
| #define EADC_CMP0_CMPDAT_Pos (16) |
EADC_T::CMP0: CMPDAT Position
Definition at line 1499 of file eadc_reg.h.
| #define EADC_CMP0_CMPMCNT_Msk (0xful << EADC_CMP0_CMPMCNT_Pos) |
EADC_T::CMP0: CMPMCNT Mask
Definition at line 1494 of file eadc_reg.h.
| #define EADC_CMP0_CMPMCNT_Pos (8) |
EADC_T::CMP0: CMPMCNT Position
Definition at line 1493 of file eadc_reg.h.
| #define EADC_CMP0_CMPSPL_Msk (0x1ful << EADC_CMP0_CMPSPL_Pos) |
EADC_T::CMP0: CMPSPL Mask
Definition at line 1491 of file eadc_reg.h.
| #define EADC_CMP0_CMPSPL_Pos (3) |
EADC_T::CMP0: CMPSPL Position
Definition at line 1490 of file eadc_reg.h.
| #define EADC_CMP0_CMPWEN_Msk (0x1ul << EADC_CMP0_CMPWEN_Pos) |
EADC_T::CMP0: CMPWEN Mask
Definition at line 1497 of file eadc_reg.h.
| #define EADC_CMP0_CMPWEN_Pos (15) |
EADC_T::CMP0: CMPWEN Position
Definition at line 1496 of file eadc_reg.h.
| #define EADC_CMP1_ADCMPEN_Msk (0x1ul << EADC_CMP1_ADCMPEN_Pos) |
EADC_T::CMP1: ADCMPEN Mask
Definition at line 1503 of file eadc_reg.h.
| #define EADC_CMP1_ADCMPEN_Pos (0) |
EADC_T::CMP1: ADCMPEN Position
Definition at line 1502 of file eadc_reg.h.
| #define EADC_CMP1_ADCMPIE_Msk (0x1ul << EADC_CMP1_ADCMPIE_Pos) |
EADC_T::CMP1: ADCMPIE Mask
Definition at line 1506 of file eadc_reg.h.
| #define EADC_CMP1_ADCMPIE_Pos (1) |
EADC_T::CMP1: ADCMPIE Position
Definition at line 1505 of file eadc_reg.h.
| #define EADC_CMP1_CMPCOND_Msk (0x1ul << EADC_CMP1_CMPCOND_Pos) |
EADC_T::CMP1: CMPCOND Mask
Definition at line 1509 of file eadc_reg.h.
| #define EADC_CMP1_CMPCOND_Pos (2) |
EADC_T::CMP1: CMPCOND Position
Definition at line 1508 of file eadc_reg.h.
| #define EADC_CMP1_CMPDAT_Msk (0xffful << EADC_CMP1_CMPDAT_Pos) |
EADC_T::CMP1: CMPDAT Mask
Definition at line 1521 of file eadc_reg.h.
| #define EADC_CMP1_CMPDAT_Pos (16) |
EADC_T::CMP1: CMPDAT Position
Definition at line 1520 of file eadc_reg.h.
| #define EADC_CMP1_CMPMCNT_Msk (0xful << EADC_CMP1_CMPMCNT_Pos) |
EADC_T::CMP1: CMPMCNT Mask
Definition at line 1515 of file eadc_reg.h.
| #define EADC_CMP1_CMPMCNT_Pos (8) |
EADC_T::CMP1: CMPMCNT Position
Definition at line 1514 of file eadc_reg.h.
| #define EADC_CMP1_CMPSPL_Msk (0x1ful << EADC_CMP1_CMPSPL_Pos) |
EADC_T::CMP1: CMPSPL Mask
Definition at line 1512 of file eadc_reg.h.
| #define EADC_CMP1_CMPSPL_Pos (3) |
EADC_T::CMP1: CMPSPL Position
Definition at line 1511 of file eadc_reg.h.
| #define EADC_CMP1_CMPWEN_Msk (0x1ul << EADC_CMP1_CMPWEN_Pos) |
EADC_T::CMP1: CMPWEN Mask
Definition at line 1518 of file eadc_reg.h.
| #define EADC_CMP1_CMPWEN_Pos (15) |
EADC_T::CMP1: CMPWEN Position
Definition at line 1517 of file eadc_reg.h.
| #define EADC_CMP2_ADCMPEN_Msk (0x1ul << EADC_CMP2_ADCMPEN_Pos) |
EADC_T::CMP2: ADCMPEN Mask
Definition at line 1524 of file eadc_reg.h.
| #define EADC_CMP2_ADCMPEN_Pos (0) |
EADC_T::CMP2: ADCMPEN Position
Definition at line 1523 of file eadc_reg.h.
| #define EADC_CMP2_ADCMPIE_Msk (0x1ul << EADC_CMP2_ADCMPIE_Pos) |
EADC_T::CMP2: ADCMPIE Mask
Definition at line 1527 of file eadc_reg.h.
| #define EADC_CMP2_ADCMPIE_Pos (1) |
EADC_T::CMP2: ADCMPIE Position
Definition at line 1526 of file eadc_reg.h.
| #define EADC_CMP2_CMPCOND_Msk (0x1ul << EADC_CMP2_CMPCOND_Pos) |
EADC_T::CMP2: CMPCOND Mask
Definition at line 1530 of file eadc_reg.h.
| #define EADC_CMP2_CMPCOND_Pos (2) |
EADC_T::CMP2: CMPCOND Position
Definition at line 1529 of file eadc_reg.h.
| #define EADC_CMP2_CMPDAT_Msk (0xffful << EADC_CMP2_CMPDAT_Pos) |
EADC_T::CMP2: CMPDAT Mask
Definition at line 1542 of file eadc_reg.h.
| #define EADC_CMP2_CMPDAT_Pos (16) |
EADC_T::CMP2: CMPDAT Position
Definition at line 1541 of file eadc_reg.h.
| #define EADC_CMP2_CMPMCNT_Msk (0xful << EADC_CMP2_CMPMCNT_Pos) |
EADC_T::CMP2: CMPMCNT Mask
Definition at line 1536 of file eadc_reg.h.
| #define EADC_CMP2_CMPMCNT_Pos (8) |
EADC_T::CMP2: CMPMCNT Position
Definition at line 1535 of file eadc_reg.h.
| #define EADC_CMP2_CMPSPL_Msk (0x1ful << EADC_CMP2_CMPSPL_Pos) |
EADC_T::CMP2: CMPSPL Mask
Definition at line 1533 of file eadc_reg.h.
| #define EADC_CMP2_CMPSPL_Pos (3) |
EADC_T::CMP2: CMPSPL Position
Definition at line 1532 of file eadc_reg.h.
| #define EADC_CMP2_CMPWEN_Msk (0x1ul << EADC_CMP2_CMPWEN_Pos) |
EADC_T::CMP2: CMPWEN Mask
Definition at line 1539 of file eadc_reg.h.
| #define EADC_CMP2_CMPWEN_Pos (15) |
EADC_T::CMP2: CMPWEN Position
Definition at line 1538 of file eadc_reg.h.
| #define EADC_CMP3_ADCMPEN_Msk (0x1ul << EADC_CMP3_ADCMPEN_Pos) |
EADC_T::CMP3: ADCMPEN Mask
Definition at line 1545 of file eadc_reg.h.
| #define EADC_CMP3_ADCMPEN_Pos (0) |
EADC_T::CMP3: ADCMPEN Position
Definition at line 1544 of file eadc_reg.h.
| #define EADC_CMP3_ADCMPIE_Msk (0x1ul << EADC_CMP3_ADCMPIE_Pos) |
EADC_T::CMP3: ADCMPIE Mask
Definition at line 1548 of file eadc_reg.h.
| #define EADC_CMP3_ADCMPIE_Pos (1) |
EADC_T::CMP3: ADCMPIE Position
Definition at line 1547 of file eadc_reg.h.
| #define EADC_CMP3_CMPCOND_Msk (0x1ul << EADC_CMP3_CMPCOND_Pos) |
EADC_T::CMP3: CMPCOND Mask
Definition at line 1551 of file eadc_reg.h.
| #define EADC_CMP3_CMPCOND_Pos (2) |
EADC_T::CMP3: CMPCOND Position
Definition at line 1550 of file eadc_reg.h.
| #define EADC_CMP3_CMPDAT_Msk (0xffful << EADC_CMP3_CMPDAT_Pos) |
EADC_T::CMP3: CMPDAT Mask
Definition at line 1563 of file eadc_reg.h.
| #define EADC_CMP3_CMPDAT_Pos (16) |
EADC_T::CMP3: CMPDAT Position
Definition at line 1562 of file eadc_reg.h.
| #define EADC_CMP3_CMPMCNT_Msk (0xful << EADC_CMP3_CMPMCNT_Pos) |
EADC_T::CMP3: CMPMCNT Mask
Definition at line 1557 of file eadc_reg.h.
| #define EADC_CMP3_CMPMCNT_Pos (8) |
EADC_T::CMP3: CMPMCNT Position
Definition at line 1556 of file eadc_reg.h.
| #define EADC_CMP3_CMPSPL_Msk (0x1ful << EADC_CMP3_CMPSPL_Pos) |
EADC_T::CMP3: CMPSPL Mask
Definition at line 1554 of file eadc_reg.h.
| #define EADC_CMP3_CMPSPL_Pos (3) |
EADC_T::CMP3: CMPSPL Position
Definition at line 1553 of file eadc_reg.h.
| #define EADC_CMP3_CMPWEN_Msk (0x1ul << EADC_CMP3_CMPWEN_Pos) |
EADC_T::CMP3: CMPWEN Mask
Definition at line 1560 of file eadc_reg.h.
| #define EADC_CMP3_CMPWEN_Pos (15) |
EADC_T::CMP3: CMPWEN Position
Definition at line 1559 of file eadc_reg.h.
| #define EADC_CMP_ADCMPEN_Msk (0x1ul << EADC_CMP_ADCMPEN_Pos) |
EADC_T::CMP: ADCMPEN Mask
Definition at line 1461 of file eadc_reg.h.
| #define EADC_CMP_ADCMPEN_Pos (0) |
EADC_T::CMP: ADCMPEN Position
Definition at line 1460 of file eadc_reg.h.
| #define EADC_CMP_ADCMPIE_Msk (0x1ul << EADC_CMP_ADCMPIE_Pos) |
EADC_T::CMP: ADCMPIE Mask
Definition at line 1464 of file eadc_reg.h.
| #define EADC_CMP_ADCMPIE_Pos (1) |
EADC_T::CMP: ADCMPIE Position
Definition at line 1463 of file eadc_reg.h.
| #define EADC_CMP_CMPCOND_Msk (0x1ul << EADC_CMP_CMPCOND_Pos) |
EADC_T::CMP: CMPCOND Mask
Definition at line 1467 of file eadc_reg.h.
| #define EADC_CMP_CMPCOND_Pos (2) |
EADC_T::CMP: CMPCOND Position
Definition at line 1466 of file eadc_reg.h.
| #define EADC_CMP_CMPDAT_Msk (0xffful << EADC_CMP_CMPDAT_Pos) |
EADC_T::CMP: CMPDAT Mask
Definition at line 1479 of file eadc_reg.h.
| #define EADC_CMP_CMPDAT_Pos (16) |
EADC_T::CMP: CMPDAT Position
Definition at line 1478 of file eadc_reg.h.
| #define EADC_CMP_CMPMCNT_Msk (0xful << EADC_CMP_CMPMCNT_Pos) |
EADC_T::CMP: CMPMCNT Mask
Definition at line 1473 of file eadc_reg.h.
| #define EADC_CMP_CMPMCNT_Pos (8) |
EADC_T::CMP: CMPMCNT Position
Definition at line 1472 of file eadc_reg.h.
| #define EADC_CMP_CMPSPL_Msk (0x1ful << EADC_CMP_CMPSPL_Pos) |
EADC_T::CMP: CMPSPL Mask
Definition at line 1470 of file eadc_reg.h.
| #define EADC_CMP_CMPSPL_Pos (3) |
EADC_T::CMP: CMPSPL Position
Definition at line 1469 of file eadc_reg.h.
| #define EADC_CMP_CMPWEN_Msk (0x1ul << EADC_CMP_CMPWEN_Pos) |
EADC_T::CMP: CMPWEN Mask
Definition at line 1476 of file eadc_reg.h.
| #define EADC_CMP_CMPWEN_Pos (15) |
EADC_T::CMP: CMPWEN Position
Definition at line 1475 of file eadc_reg.h.
| #define EADC_CTL_ADCEN_Msk (0x1ul << EADC_CTL_ADCEN_Pos) |
EADC_T::CTL: ADCEN Mask
Definition at line 762 of file eadc_reg.h.
| #define EADC_CTL_ADCEN_Pos (0) |
EADC_T::CTL: ADCEN Position
Definition at line 761 of file eadc_reg.h.
| #define EADC_CTL_ADCIEN0_Msk (0x1ul << EADC_CTL_ADCIEN0_Pos) |
EADC_T::CTL: ADCIEN0 Mask
Definition at line 768 of file eadc_reg.h.
| #define EADC_CTL_ADCIEN0_Pos (2) |
EADC_T::CTL: ADCIEN0 Position
Definition at line 767 of file eadc_reg.h.
| #define EADC_CTL_ADCIEN1_Msk (0x1ul << EADC_CTL_ADCIEN1_Pos) |
EADC_T::CTL: ADCIEN1 Mask
Definition at line 771 of file eadc_reg.h.
| #define EADC_CTL_ADCIEN1_Pos (3) |
EADC_T::CTL: ADCIEN1 Position
Definition at line 770 of file eadc_reg.h.
| #define EADC_CTL_ADCIEN2_Msk (0x1ul << EADC_CTL_ADCIEN2_Pos) |
EADC_T::CTL: ADCIEN2 Mask
Definition at line 774 of file eadc_reg.h.
| #define EADC_CTL_ADCIEN2_Pos (4) |
EADC_T::CTL: ADCIEN2 Position
Definition at line 773 of file eadc_reg.h.
| #define EADC_CTL_ADCIEN3_Msk (0x1ul << EADC_CTL_ADCIEN3_Pos) |
EADC_T::CTL: ADCIEN3 Mask
Definition at line 777 of file eadc_reg.h.
| #define EADC_CTL_ADCIEN3_Pos (5) |
EADC_T::CTL: ADCIEN3 Position
Definition at line 776 of file eadc_reg.h.
| #define EADC_CTL_ADCRST_Msk (0x1ul << EADC_CTL_ADCRST_Pos) |
EADC_T::CTL: ADCRST Mask
Definition at line 765 of file eadc_reg.h.
| #define EADC_CTL_ADCRST_Pos (1) |
EADC_T::CTL: ADCRST Position
Definition at line 764 of file eadc_reg.h.
| #define EADC_CTL_DIFFEN_Msk (0x1ul << EADC_CTL_DIFFEN_Pos) |
EADC_T::CTL: DIFFEN Mask
Definition at line 783 of file eadc_reg.h.
| #define EADC_CTL_DIFFEN_Pos (8) |
EADC_T::CTL: DIFFEN Position
Definition at line 782 of file eadc_reg.h.
| #define EADC_CTL_DMOF_Msk (0x1ul << EADC_CTL_DMOF_Pos) |
EADC_T::CTL: DMOF Mask
Definition at line 786 of file eadc_reg.h.
| #define EADC_CTL_DMOF_Pos (9) |
EADC_T::CTL: DMOF Position
Definition at line 785 of file eadc_reg.h.
| #define EADC_CTL_PDMAEN_Msk (0x1ul << EADC_CTL_PDMAEN_Pos) |
EADC_T::CTL: PDMAEN Mask
Definition at line 789 of file eadc_reg.h.
| #define EADC_CTL_PDMAEN_Pos (11) |
EADC_T::CTL: PDMAEN Position
Definition at line 788 of file eadc_reg.h.
| #define EADC_CTL_RESSEL_Msk (0x3ul << EADC_CTL_RESSEL_Pos) |
EADC_T::CTL: RESSEL Mask
Definition at line 780 of file eadc_reg.h.
| #define EADC_CTL_RESSEL_Pos (6) |
EADC_T::CTL: RESSEL Position
Definition at line 779 of file eadc_reg.h.
| #define EADC_CURDAT_CURDAT_Msk (0x3fffful << EADC_CURDAT_CURDAT_Pos) |
EADC_T::CURDAT: CURDAT Mask
Definition at line 759 of file eadc_reg.h.
| #define EADC_CURDAT_CURDAT_Pos (0) |
EADC_T::CURDAT: CURDAT Position
Definition at line 758 of file eadc_reg.h.
| #define EADC_DAT0_OV_Msk (0x1ul << EADC_DAT0_OV_Pos) |
EADC_T::DAT0: OV Mask
Definition at line 591 of file eadc_reg.h.
| #define EADC_DAT0_OV_Pos (16) |
EADC_T::DAT0: OV Position
Definition at line 590 of file eadc_reg.h.
| #define EADC_DAT0_RESULT_Msk (0xfffful << EADC_DAT0_RESULT_Pos) |
EADC_T::DAT0: RESULT Mask
Definition at line 588 of file eadc_reg.h.
| #define EADC_DAT0_RESULT_Pos (0) |
EADC_T::DAT0: RESULT Position
Definition at line 587 of file eadc_reg.h.
| #define EADC_DAT0_VALID_Msk (0x1ul << EADC_DAT0_VALID_Pos) |
EADC_T::DAT0: VALID Mask
Definition at line 594 of file eadc_reg.h.
| #define EADC_DAT0_VALID_Pos (17) |
EADC_T::DAT0: VALID Position
Definition at line 593 of file eadc_reg.h.
| #define EADC_DAT10_OV_Msk (0x1ul << EADC_DAT10_OV_Pos) |
EADC_T::DAT10: OV Mask
Definition at line 681 of file eadc_reg.h.
| #define EADC_DAT10_OV_Pos (16) |
EADC_T::DAT10: OV Position
Definition at line 680 of file eadc_reg.h.
| #define EADC_DAT10_RESULT_Msk (0xfffful << EADC_DAT10_RESULT_Pos) |
EADC_T::DAT10: RESULT Mask
Definition at line 678 of file eadc_reg.h.
| #define EADC_DAT10_RESULT_Pos (0) |
EADC_T::DAT10: RESULT Position
Definition at line 677 of file eadc_reg.h.
| #define EADC_DAT10_VALID_Msk (0x1ul << EADC_DAT10_VALID_Pos) |
EADC_T::DAT10: VALID Mask
Definition at line 684 of file eadc_reg.h.
| #define EADC_DAT10_VALID_Pos (17) |
EADC_T::DAT10: VALID Position
Definition at line 683 of file eadc_reg.h.
| #define EADC_DAT11_OV_Msk (0x1ul << EADC_DAT11_OV_Pos) |
EADC_T::DAT11: OV Mask
Definition at line 690 of file eadc_reg.h.
| #define EADC_DAT11_OV_Pos (16) |
EADC_T::DAT11: OV Position
Definition at line 689 of file eadc_reg.h.
| #define EADC_DAT11_RESULT_Msk (0xfffful << EADC_DAT11_RESULT_Pos) |
EADC_T::DAT11: RESULT Mask
Definition at line 687 of file eadc_reg.h.
| #define EADC_DAT11_RESULT_Pos (0) |
EADC_T::DAT11: RESULT Position
Definition at line 686 of file eadc_reg.h.
| #define EADC_DAT11_VALID_Msk (0x1ul << EADC_DAT11_VALID_Pos) |
EADC_T::DAT11: VALID Mask
Definition at line 693 of file eadc_reg.h.
| #define EADC_DAT11_VALID_Pos (17) |
EADC_T::DAT11: VALID Position
Definition at line 692 of file eadc_reg.h.
| #define EADC_DAT12_OV_Msk (0x1ul << EADC_DAT12_OV_Pos) |
EADC_T::DAT12: OV Mask
Definition at line 699 of file eadc_reg.h.
| #define EADC_DAT12_OV_Pos (16) |
EADC_T::DAT12: OV Position
Definition at line 698 of file eadc_reg.h.
| #define EADC_DAT12_RESULT_Msk (0xfffful << EADC_DAT12_RESULT_Pos) |
EADC_T::DAT12: RESULT Mask
Definition at line 696 of file eadc_reg.h.
| #define EADC_DAT12_RESULT_Pos (0) |
EADC_T::DAT12: RESULT Position
Definition at line 695 of file eadc_reg.h.
| #define EADC_DAT12_VALID_Msk (0x1ul << EADC_DAT12_VALID_Pos) |
EADC_T::DAT12: VALID Mask
Definition at line 702 of file eadc_reg.h.
| #define EADC_DAT12_VALID_Pos (17) |
EADC_T::DAT12: VALID Position
Definition at line 701 of file eadc_reg.h.
| #define EADC_DAT13_OV_Msk (0x1ul << EADC_DAT13_OV_Pos) |
EADC_T::DAT13: OV Mask
Definition at line 708 of file eadc_reg.h.
| #define EADC_DAT13_OV_Pos (16) |
EADC_T::DAT13: OV Position
Definition at line 707 of file eadc_reg.h.
| #define EADC_DAT13_RESULT_Msk (0xfffful << EADC_DAT13_RESULT_Pos) |
EADC_T::DAT13: RESULT Mask
Definition at line 705 of file eadc_reg.h.
| #define EADC_DAT13_RESULT_Pos (0) |
EADC_T::DAT13: RESULT Position
Definition at line 704 of file eadc_reg.h.
| #define EADC_DAT13_VALID_Msk (0x1ul << EADC_DAT13_VALID_Pos) |
EADC_T::DAT13: VALID Mask
Definition at line 711 of file eadc_reg.h.
| #define EADC_DAT13_VALID_Pos (17) |
EADC_T::DAT13: VALID Position
Definition at line 710 of file eadc_reg.h.
| #define EADC_DAT14_OV_Msk (0x1ul << EADC_DAT14_OV_Pos) |
EADC_T::DAT14: OV Mask
Definition at line 717 of file eadc_reg.h.
| #define EADC_DAT14_OV_Pos (16) |
EADC_T::DAT14: OV Position
Definition at line 716 of file eadc_reg.h.
| #define EADC_DAT14_RESULT_Msk (0xfffful << EADC_DAT14_RESULT_Pos) |
EADC_T::DAT14: RESULT Mask
Definition at line 714 of file eadc_reg.h.
| #define EADC_DAT14_RESULT_Pos (0) |
EADC_T::DAT14: RESULT Position
Definition at line 713 of file eadc_reg.h.
| #define EADC_DAT14_VALID_Msk (0x1ul << EADC_DAT14_VALID_Pos) |
EADC_T::DAT14: VALID Mask
Definition at line 720 of file eadc_reg.h.
| #define EADC_DAT14_VALID_Pos (17) |
EADC_T::DAT14: VALID Position
Definition at line 719 of file eadc_reg.h.
| #define EADC_DAT15_OV_Msk (0x1ul << EADC_DAT15_OV_Pos) |
EADC_T::DAT15: OV Mask
Definition at line 726 of file eadc_reg.h.
| #define EADC_DAT15_OV_Pos (16) |
EADC_T::DAT15: OV Position
Definition at line 725 of file eadc_reg.h.
| #define EADC_DAT15_RESULT_Msk (0xfffful << EADC_DAT15_RESULT_Pos) |
EADC_T::DAT15: RESULT Mask
Definition at line 723 of file eadc_reg.h.
| #define EADC_DAT15_RESULT_Pos (0) |
EADC_T::DAT15: RESULT Position
Definition at line 722 of file eadc_reg.h.
| #define EADC_DAT15_VALID_Msk (0x1ul << EADC_DAT15_VALID_Pos) |
EADC_T::DAT15: VALID Mask
Definition at line 729 of file eadc_reg.h.
| #define EADC_DAT15_VALID_Pos (17) |
EADC_T::DAT15: VALID Position
Definition at line 728 of file eadc_reg.h.
| #define EADC_DAT16_OV_Msk (0x1ul << EADC_DAT16_OV_Pos) |
EADC_T::DAT16: OV Mask
Definition at line 735 of file eadc_reg.h.
| #define EADC_DAT16_OV_Pos (16) |
EADC_T::DAT16: OV Position
Definition at line 734 of file eadc_reg.h.
| #define EADC_DAT16_RESULT_Msk (0xfffful << EADC_DAT16_RESULT_Pos) |
EADC_T::DAT16: RESULT Mask
Definition at line 732 of file eadc_reg.h.
| #define EADC_DAT16_RESULT_Pos (0) |
EADC_T::DAT16: RESULT Position
Definition at line 731 of file eadc_reg.h.
| #define EADC_DAT16_VALID_Msk (0x1ul << EADC_DAT16_VALID_Pos) |
EADC_T::DAT16: VALID Mask
Definition at line 738 of file eadc_reg.h.
| #define EADC_DAT16_VALID_Pos (17) |
EADC_T::DAT16: VALID Position
Definition at line 737 of file eadc_reg.h.
| #define EADC_DAT17_OV_Msk (0x1ul << EADC_DAT17_OV_Pos) |
EADC_T::DAT17: OV Mask
Definition at line 744 of file eadc_reg.h.
| #define EADC_DAT17_OV_Pos (16) |
EADC_T::DAT17: OV Position
Definition at line 743 of file eadc_reg.h.
| #define EADC_DAT17_RESULT_Msk (0xfffful << EADC_DAT17_RESULT_Pos) |
EADC_T::DAT17: RESULT Mask
Definition at line 741 of file eadc_reg.h.
| #define EADC_DAT17_RESULT_Pos (0) |
EADC_T::DAT17: RESULT Position
Definition at line 740 of file eadc_reg.h.
| #define EADC_DAT17_VALID_Msk (0x1ul << EADC_DAT17_VALID_Pos) |
EADC_T::DAT17: VALID Mask
Definition at line 747 of file eadc_reg.h.
| #define EADC_DAT17_VALID_Pos (17) |
EADC_T::DAT17: VALID Position
Definition at line 746 of file eadc_reg.h.
| #define EADC_DAT18_OV_Msk (0x1ul << EADC_DAT18_OV_Pos) |
EADC_T::DAT18: OV Mask
Definition at line 753 of file eadc_reg.h.
| #define EADC_DAT18_OV_Pos (16) |
EADC_T::DAT18: OV Position
Definition at line 752 of file eadc_reg.h.
| #define EADC_DAT18_RESULT_Msk (0xfffful << EADC_DAT18_RESULT_Pos) |
EADC_T::DAT18: RESULT Mask
Definition at line 750 of file eadc_reg.h.
| #define EADC_DAT18_RESULT_Pos (0) |
EADC_T::DAT18: RESULT Position
Definition at line 749 of file eadc_reg.h.
| #define EADC_DAT18_VALID_Msk (0x1ul << EADC_DAT18_VALID_Pos) |
EADC_T::DAT18: VALID Mask
Definition at line 756 of file eadc_reg.h.
| #define EADC_DAT18_VALID_Pos (17) |
EADC_T::DAT18: VALID Position
Definition at line 755 of file eadc_reg.h.
| #define EADC_DAT1_OV_Msk (0x1ul << EADC_DAT1_OV_Pos) |
EADC_T::DAT1: OV Mask
Definition at line 600 of file eadc_reg.h.
| #define EADC_DAT1_OV_Pos (16) |
EADC_T::DAT1: OV Position
Definition at line 599 of file eadc_reg.h.
| #define EADC_DAT1_RESULT_Msk (0xfffful << EADC_DAT1_RESULT_Pos) |
EADC_T::DAT1: RESULT Mask
Definition at line 597 of file eadc_reg.h.
| #define EADC_DAT1_RESULT_Pos (0) |
EADC_T::DAT1: RESULT Position
Definition at line 596 of file eadc_reg.h.
| #define EADC_DAT1_VALID_Msk (0x1ul << EADC_DAT1_VALID_Pos) |
EADC_T::DAT1: VALID Mask
Definition at line 603 of file eadc_reg.h.
| #define EADC_DAT1_VALID_Pos (17) |
EADC_T::DAT1: VALID Position
Definition at line 602 of file eadc_reg.h.
| #define EADC_DAT2_OV_Msk (0x1ul << EADC_DAT2_OV_Pos) |
EADC_T::DAT2: OV Mask
Definition at line 609 of file eadc_reg.h.
| #define EADC_DAT2_OV_Pos (16) |
EADC_T::DAT2: OV Position
Definition at line 608 of file eadc_reg.h.
| #define EADC_DAT2_RESULT_Msk (0xfffful << EADC_DAT2_RESULT_Pos) |
EADC_T::DAT2: RESULT Mask
Definition at line 606 of file eadc_reg.h.
| #define EADC_DAT2_RESULT_Pos (0) |
EADC_T::DAT2: RESULT Position
Definition at line 605 of file eadc_reg.h.
| #define EADC_DAT2_VALID_Msk (0x1ul << EADC_DAT2_VALID_Pos) |
EADC_T::DAT2: VALID Mask
Definition at line 612 of file eadc_reg.h.
| #define EADC_DAT2_VALID_Pos (17) |
EADC_T::DAT2: VALID Position
Definition at line 611 of file eadc_reg.h.
| #define EADC_DAT3_OV_Msk (0x1ul << EADC_DAT3_OV_Pos) |
EADC_T::DAT3: OV Mask
Definition at line 618 of file eadc_reg.h.
| #define EADC_DAT3_OV_Pos (16) |
EADC_T::DAT3: OV Position
Definition at line 617 of file eadc_reg.h.
| #define EADC_DAT3_RESULT_Msk (0xfffful << EADC_DAT3_RESULT_Pos) |
EADC_T::DAT3: RESULT Mask
Definition at line 615 of file eadc_reg.h.
| #define EADC_DAT3_RESULT_Pos (0) |
EADC_T::DAT3: RESULT Position
Definition at line 614 of file eadc_reg.h.
| #define EADC_DAT3_VALID_Msk (0x1ul << EADC_DAT3_VALID_Pos) |
EADC_T::DAT3: VALID Mask
Definition at line 621 of file eadc_reg.h.
| #define EADC_DAT3_VALID_Pos (17) |
EADC_T::DAT3: VALID Position
Definition at line 620 of file eadc_reg.h.
| #define EADC_DAT4_OV_Msk (0x1ul << EADC_DAT4_OV_Pos) |
EADC_T::DAT4: OV Mask
Definition at line 627 of file eadc_reg.h.
| #define EADC_DAT4_OV_Pos (16) |
EADC_T::DAT4: OV Position
Definition at line 626 of file eadc_reg.h.
| #define EADC_DAT4_RESULT_Msk (0xfffful << EADC_DAT4_RESULT_Pos) |
EADC_T::DAT4: RESULT Mask
Definition at line 624 of file eadc_reg.h.
| #define EADC_DAT4_RESULT_Pos (0) |
EADC_T::DAT4: RESULT Position
Definition at line 623 of file eadc_reg.h.
| #define EADC_DAT4_VALID_Msk (0x1ul << EADC_DAT4_VALID_Pos) |
EADC_T::DAT4: VALID Mask
Definition at line 630 of file eadc_reg.h.
| #define EADC_DAT4_VALID_Pos (17) |
EADC_T::DAT4: VALID Position
Definition at line 629 of file eadc_reg.h.
| #define EADC_DAT5_OV_Msk (0x1ul << EADC_DAT5_OV_Pos) |
EADC_T::DAT5: OV Mask
Definition at line 636 of file eadc_reg.h.
| #define EADC_DAT5_OV_Pos (16) |
EADC_T::DAT5: OV Position
Definition at line 635 of file eadc_reg.h.
| #define EADC_DAT5_RESULT_Msk (0xfffful << EADC_DAT5_RESULT_Pos) |
EADC_T::DAT5: RESULT Mask
Definition at line 633 of file eadc_reg.h.
| #define EADC_DAT5_RESULT_Pos (0) |
EADC_T::DAT5: RESULT Position
Definition at line 632 of file eadc_reg.h.
| #define EADC_DAT5_VALID_Msk (0x1ul << EADC_DAT5_VALID_Pos) |
EADC_T::DAT5: VALID Mask
Definition at line 639 of file eadc_reg.h.
| #define EADC_DAT5_VALID_Pos (17) |
EADC_T::DAT5: VALID Position
Definition at line 638 of file eadc_reg.h.
| #define EADC_DAT6_OV_Msk (0x1ul << EADC_DAT6_OV_Pos) |
EADC_T::DAT6: OV Mask
Definition at line 645 of file eadc_reg.h.
| #define EADC_DAT6_OV_Pos (16) |
EADC_T::DAT6: OV Position
Definition at line 644 of file eadc_reg.h.
| #define EADC_DAT6_RESULT_Msk (0xfffful << EADC_DAT6_RESULT_Pos) |
EADC_T::DAT6: RESULT Mask
Definition at line 642 of file eadc_reg.h.
| #define EADC_DAT6_RESULT_Pos (0) |
EADC_T::DAT6: RESULT Position
Definition at line 641 of file eadc_reg.h.
| #define EADC_DAT6_VALID_Msk (0x1ul << EADC_DAT6_VALID_Pos) |
EADC_T::DAT6: VALID Mask
Definition at line 648 of file eadc_reg.h.
| #define EADC_DAT6_VALID_Pos (17) |
EADC_T::DAT6: VALID Position
Definition at line 647 of file eadc_reg.h.
| #define EADC_DAT7_OV_Msk (0x1ul << EADC_DAT7_OV_Pos) |
EADC_T::DAT7: OV Mask
Definition at line 654 of file eadc_reg.h.
| #define EADC_DAT7_OV_Pos (16) |
EADC_T::DAT7: OV Position
Definition at line 653 of file eadc_reg.h.
| #define EADC_DAT7_RESULT_Msk (0xfffful << EADC_DAT7_RESULT_Pos) |
EADC_T::DAT7: RESULT Mask
Definition at line 651 of file eadc_reg.h.
| #define EADC_DAT7_RESULT_Pos (0) |
EADC_T::DAT7: RESULT Position
Definition at line 650 of file eadc_reg.h.
| #define EADC_DAT7_VALID_Msk (0x1ul << EADC_DAT7_VALID_Pos) |
EADC_T::DAT7: VALID Mask
Definition at line 657 of file eadc_reg.h.
| #define EADC_DAT7_VALID_Pos (17) |
EADC_T::DAT7: VALID Position
Definition at line 656 of file eadc_reg.h.
| #define EADC_DAT8_OV_Msk (0x1ul << EADC_DAT8_OV_Pos) |
EADC_T::DAT8: OV Mask
Definition at line 663 of file eadc_reg.h.
| #define EADC_DAT8_OV_Pos (16) |
EADC_T::DAT8: OV Position
Definition at line 662 of file eadc_reg.h.
| #define EADC_DAT8_RESULT_Msk (0xfffful << EADC_DAT8_RESULT_Pos) |
EADC_T::DAT8: RESULT Mask
Definition at line 660 of file eadc_reg.h.
| #define EADC_DAT8_RESULT_Pos (0) |
EADC_T::DAT8: RESULT Position
Definition at line 659 of file eadc_reg.h.
| #define EADC_DAT8_VALID_Msk (0x1ul << EADC_DAT8_VALID_Pos) |
EADC_T::DAT8: VALID Mask
Definition at line 666 of file eadc_reg.h.
| #define EADC_DAT8_VALID_Pos (17) |
EADC_T::DAT8: VALID Position
Definition at line 665 of file eadc_reg.h.
| #define EADC_DAT9_OV_Msk (0x1ul << EADC_DAT9_OV_Pos) |
EADC_T::DAT9: OV Mask
Definition at line 672 of file eadc_reg.h.
| #define EADC_DAT9_OV_Pos (16) |
EADC_T::DAT9: OV Position
Definition at line 671 of file eadc_reg.h.
| #define EADC_DAT9_RESULT_Msk (0xfffful << EADC_DAT9_RESULT_Pos) |
EADC_T::DAT9: RESULT Mask
Definition at line 669 of file eadc_reg.h.
| #define EADC_DAT9_RESULT_Pos (0) |
EADC_T::DAT9: RESULT Position
Definition at line 668 of file eadc_reg.h.
| #define EADC_DAT9_VALID_Msk (0x1ul << EADC_DAT9_VALID_Pos) |
EADC_T::DAT9: VALID Mask
Definition at line 675 of file eadc_reg.h.
| #define EADC_DAT9_VALID_Pos (17) |
EADC_T::DAT9: VALID Position
Definition at line 674 of file eadc_reg.h.
| #define EADC_DAT_OV_Msk (0x1ul << EADC_DAT_OV_Pos) |
EADC_T::DAT: OV Mask
Definition at line 582 of file eadc_reg.h.
| #define EADC_DAT_OV_Pos (16) |
EADC_T::DAT: OV Position
Definition at line 581 of file eadc_reg.h.
| #define EADC_DAT_RESULT_Msk (0xfffful << EADC_DAT_RESULT_Pos) |
EADC_T::DAT: RESULT Mask
Definition at line 579 of file eadc_reg.h.
| #define EADC_DAT_RESULT_Pos (0) |
@addtogroup EADC_CONST EADC Bit Field Definition Constant Definitions for EADC Controller
EADC_T::DAT: RESULT Position
Definition at line 578 of file eadc_reg.h.
| #define EADC_DAT_VALID_Msk (0x1ul << EADC_DAT_VALID_Pos) |
EADC_T::DAT: VALID Mask
Definition at line 585 of file eadc_reg.h.
| #define EADC_DAT_VALID_Pos (17) |
EADC_T::DAT: VALID Position
Definition at line 584 of file eadc_reg.h.
| #define EADC_DDAT0_OV_Msk (0x1ul << EADC_DDAT0_OV_Pos) |
EADC_T::DDAT0: OV Mask
Definition at line 1650 of file eadc_reg.h.
| #define EADC_DDAT0_OV_Pos (16) |
EADC_T::DDAT0: OV Position
Definition at line 1649 of file eadc_reg.h.
| #define EADC_DDAT0_RESULT_Msk (0xfffful << EADC_DDAT0_RESULT_Pos) |
EADC_T::DDAT0: RESULT Mask
Definition at line 1647 of file eadc_reg.h.
| #define EADC_DDAT0_RESULT_Pos (0) |
EADC_T::DDAT0: RESULT Position
Definition at line 1646 of file eadc_reg.h.
| #define EADC_DDAT0_VALID_Msk (0x1ul << EADC_DDAT0_VALID_Pos) |
EADC_T::DDAT0: VALID Mask
Definition at line 1653 of file eadc_reg.h.
| #define EADC_DDAT0_VALID_Pos (17) |
EADC_T::DDAT0: VALID Position
Definition at line 1652 of file eadc_reg.h.
| #define EADC_DDAT1_OV_Msk (0x1ul << EADC_DDAT1_OV_Pos) |
EADC_T::DDAT1: OV Mask
Definition at line 1659 of file eadc_reg.h.
| #define EADC_DDAT1_OV_Pos (16) |
EADC_T::DDAT1: OV Position
Definition at line 1658 of file eadc_reg.h.
| #define EADC_DDAT1_RESULT_Msk (0xfffful << EADC_DDAT1_RESULT_Pos) |
EADC_T::DDAT1: RESULT Mask
Definition at line 1656 of file eadc_reg.h.
| #define EADC_DDAT1_RESULT_Pos (0) |
EADC_T::DDAT1: RESULT Position
Definition at line 1655 of file eadc_reg.h.
| #define EADC_DDAT1_VALID_Msk (0x1ul << EADC_DDAT1_VALID_Pos) |
EADC_T::DDAT1: VALID Mask
Definition at line 1662 of file eadc_reg.h.
| #define EADC_DDAT1_VALID_Pos (17) |
EADC_T::DDAT1: VALID Position
Definition at line 1661 of file eadc_reg.h.
| #define EADC_DDAT2_OV_Msk (0x1ul << EADC_DDAT2_OV_Pos) |
EADC_T::DDAT2: OV Mask
Definition at line 1668 of file eadc_reg.h.
| #define EADC_DDAT2_OV_Pos (16) |
EADC_T::DDAT2: OV Position
Definition at line 1667 of file eadc_reg.h.
| #define EADC_DDAT2_RESULT_Msk (0xfffful << EADC_DDAT2_RESULT_Pos) |
EADC_T::DDAT2: RESULT Mask
Definition at line 1665 of file eadc_reg.h.
| #define EADC_DDAT2_RESULT_Pos (0) |
EADC_T::DDAT2: RESULT Position
Definition at line 1664 of file eadc_reg.h.
| #define EADC_DDAT2_VALID_Msk (0x1ul << EADC_DDAT2_VALID_Pos) |
EADC_T::DDAT2: VALID Mask
Definition at line 1671 of file eadc_reg.h.
| #define EADC_DDAT2_VALID_Pos (17) |
EADC_T::DDAT2: VALID Position
Definition at line 1670 of file eadc_reg.h.
| #define EADC_DDAT3_OV_Msk (0x1ul << EADC_DDAT3_OV_Pos) |
EADC_T::DDAT3: OV Mask
Definition at line 1677 of file eadc_reg.h.
| #define EADC_DDAT3_OV_Pos (16) |
EADC_T::DDAT3: OV Position
Definition at line 1676 of file eadc_reg.h.
| #define EADC_DDAT3_RESULT_Msk (0xfffful << EADC_DDAT3_RESULT_Pos) |
EADC_T::DDAT3: RESULT Mask
Definition at line 1674 of file eadc_reg.h.
| #define EADC_DDAT3_RESULT_Pos (0) |
EADC_T::DDAT3: RESULT Position
Definition at line 1673 of file eadc_reg.h.
| #define EADC_DDAT3_VALID_Msk (0x1ul << EADC_DDAT3_VALID_Pos) |
EADC_T::DDAT3: VALID Mask
Definition at line 1680 of file eadc_reg.h.
| #define EADC_DDAT3_VALID_Pos (17) |
EADC_T::DDAT3: VALID Position
Definition at line 1679 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE0_Msk (0x1ul << EADC_INTSRC0_SPLIE0_Pos) |
EADC_T::INTSRC0: SPLIE0 Mask
Definition at line 1233 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE0_Pos (0) |
EADC_T::INTSRC0: SPLIE0 Position
Definition at line 1232 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE10_Msk (0x1ul << EADC_INTSRC0_SPLIE10_Pos) |
EADC_T::INTSRC0: SPLIE10 Mask
Definition at line 1263 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE10_Pos (10) |
EADC_T::INTSRC0: SPLIE10 Position
Definition at line 1262 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE11_Msk (0x1ul << EADC_INTSRC0_SPLIE11_Pos) |
EADC_T::INTSRC0: SPLIE11 Mask
Definition at line 1266 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE11_Pos (11) |
EADC_T::INTSRC0: SPLIE11 Position
Definition at line 1265 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE12_Msk (0x1ul << EADC_INTSRC0_SPLIE12_Pos) |
EADC_T::INTSRC0: SPLIE12 Mask
Definition at line 1269 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE12_Pos (12) |
EADC_T::INTSRC0: SPLIE12 Position
Definition at line 1268 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE13_Msk (0x1ul << EADC_INTSRC0_SPLIE13_Pos) |
EADC_T::INTSRC0: SPLIE13 Mask
Definition at line 1272 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE13_Pos (13) |
EADC_T::INTSRC0: SPLIE13 Position
Definition at line 1271 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE14_Msk (0x1ul << EADC_INTSRC0_SPLIE14_Pos) |
EADC_T::INTSRC0: SPLIE14 Mask
Definition at line 1275 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE14_Pos (14) |
EADC_T::INTSRC0: SPLIE14 Position
Definition at line 1274 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE15_Msk (0x1ul << EADC_INTSRC0_SPLIE15_Pos) |
EADC_T::INTSRC0: SPLIE15 Mask
Definition at line 1278 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE15_Pos (15) |
EADC_T::INTSRC0: SPLIE15 Position
Definition at line 1277 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE16_Msk (0x1ul << EADC_INTSRC0_SPLIE16_Pos) |
EADC_T::INTSRC0: SPLIE16 Mask
Definition at line 1281 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE16_Pos (16) |
EADC_T::INTSRC0: SPLIE16 Position
Definition at line 1280 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE17_Msk (0x1ul << EADC_INTSRC0_SPLIE17_Pos) |
EADC_T::INTSRC0: SPLIE17 Mask
Definition at line 1284 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE17_Pos (17) |
EADC_T::INTSRC0: SPLIE17 Position
Definition at line 1283 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE18_Msk (0x1ul << EADC_INTSRC0_SPLIE18_Pos) |
EADC_T::INTSRC0: SPLIE18 Mask
Definition at line 1287 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE18_Pos (18) |
EADC_T::INTSRC0: SPLIE18 Position
Definition at line 1286 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE1_Msk (0x1ul << EADC_INTSRC0_SPLIE1_Pos) |
EADC_T::INTSRC0: SPLIE1 Mask
Definition at line 1236 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE1_Pos (1) |
EADC_T::INTSRC0: SPLIE1 Position
Definition at line 1235 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE2_Msk (0x1ul << EADC_INTSRC0_SPLIE2_Pos) |
EADC_T::INTSRC0: SPLIE2 Mask
Definition at line 1239 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE2_Pos (2) |
EADC_T::INTSRC0: SPLIE2 Position
Definition at line 1238 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE3_Msk (0x1ul << EADC_INTSRC0_SPLIE3_Pos) |
EADC_T::INTSRC0: SPLIE3 Mask
Definition at line 1242 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE3_Pos (3) |
EADC_T::INTSRC0: SPLIE3 Position
Definition at line 1241 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE4_Msk (0x1ul << EADC_INTSRC0_SPLIE4_Pos) |
EADC_T::INTSRC0: SPLIE4 Mask
Definition at line 1245 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE4_Pos (4) |
EADC_T::INTSRC0: SPLIE4 Position
Definition at line 1244 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE5_Msk (0x1ul << EADC_INTSRC0_SPLIE5_Pos) |
EADC_T::INTSRC0: SPLIE5 Mask
Definition at line 1248 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE5_Pos (5) |
EADC_T::INTSRC0: SPLIE5 Position
Definition at line 1247 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE6_Msk (0x1ul << EADC_INTSRC0_SPLIE6_Pos) |
EADC_T::INTSRC0: SPLIE6 Mask
Definition at line 1251 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE6_Pos (6) |
EADC_T::INTSRC0: SPLIE6 Position
Definition at line 1250 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE7_Msk (0x1ul << EADC_INTSRC0_SPLIE7_Pos) |
EADC_T::INTSRC0: SPLIE7 Mask
Definition at line 1254 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE7_Pos (7) |
EADC_T::INTSRC0: SPLIE7 Position
Definition at line 1253 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE8_Msk (0x1ul << EADC_INTSRC0_SPLIE8_Pos) |
EADC_T::INTSRC0: SPLIE8 Mask
Definition at line 1257 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE8_Pos (8) |
EADC_T::INTSRC0: SPLIE8 Position
Definition at line 1256 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE9_Msk (0x1ul << EADC_INTSRC0_SPLIE9_Pos) |
EADC_T::INTSRC0: SPLIE9 Mask
Definition at line 1260 of file eadc_reg.h.
| #define EADC_INTSRC0_SPLIE9_Pos (9) |
EADC_T::INTSRC0: SPLIE9 Position
Definition at line 1259 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE0_Msk (0x1ul << EADC_INTSRC1_SPLIE0_Pos) |
EADC_T::INTSRC1: SPLIE0 Mask
Definition at line 1290 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE0_Pos (0) |
EADC_T::INTSRC1: SPLIE0 Position
Definition at line 1289 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE10_Msk (0x1ul << EADC_INTSRC1_SPLIE10_Pos) |
EADC_T::INTSRC1: SPLIE10 Mask
Definition at line 1320 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE10_Pos (10) |
EADC_T::INTSRC1: SPLIE10 Position
Definition at line 1319 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE11_Msk (0x1ul << EADC_INTSRC1_SPLIE11_Pos) |
EADC_T::INTSRC1: SPLIE11 Mask
Definition at line 1323 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE11_Pos (11) |
EADC_T::INTSRC1: SPLIE11 Position
Definition at line 1322 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE12_Msk (0x1ul << EADC_INTSRC1_SPLIE12_Pos) |
EADC_T::INTSRC1: SPLIE12 Mask
Definition at line 1326 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE12_Pos (12) |
EADC_T::INTSRC1: SPLIE12 Position
Definition at line 1325 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE13_Msk (0x1ul << EADC_INTSRC1_SPLIE13_Pos) |
EADC_T::INTSRC1: SPLIE13 Mask
Definition at line 1329 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE13_Pos (13) |
EADC_T::INTSRC1: SPLIE13 Position
Definition at line 1328 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE14_Msk (0x1ul << EADC_INTSRC1_SPLIE14_Pos) |
EADC_T::INTSRC1: SPLIE14 Mask
Definition at line 1332 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE14_Pos (14) |
EADC_T::INTSRC1: SPLIE14 Position
Definition at line 1331 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE15_Msk (0x1ul << EADC_INTSRC1_SPLIE15_Pos) |
EADC_T::INTSRC1: SPLIE15 Mask
Definition at line 1335 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE15_Pos (15) |
EADC_T::INTSRC1: SPLIE15 Position
Definition at line 1334 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE16_Msk (0x1ul << EADC_INTSRC1_SPLIE16_Pos) |
EADC_T::INTSRC1: SPLIE16 Mask
Definition at line 1338 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE16_Pos (16) |
EADC_T::INTSRC1: SPLIE16 Position
Definition at line 1337 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE17_Msk (0x1ul << EADC_INTSRC1_SPLIE17_Pos) |
EADC_T::INTSRC1: SPLIE17 Mask
Definition at line 1341 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE17_Pos (17) |
EADC_T::INTSRC1: SPLIE17 Position
Definition at line 1340 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE18_Msk (0x1ul << EADC_INTSRC1_SPLIE18_Pos) |
EADC_T::INTSRC1: SPLIE18 Mask
Definition at line 1344 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE18_Pos (18) |
EADC_T::INTSRC1: SPLIE18 Position
Definition at line 1343 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE1_Msk (0x1ul << EADC_INTSRC1_SPLIE1_Pos) |
EADC_T::INTSRC1: SPLIE1 Mask
Definition at line 1293 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE1_Pos (1) |
EADC_T::INTSRC1: SPLIE1 Position
Definition at line 1292 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE2_Msk (0x1ul << EADC_INTSRC1_SPLIE2_Pos) |
EADC_T::INTSRC1: SPLIE2 Mask
Definition at line 1296 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE2_Pos (2) |
EADC_T::INTSRC1: SPLIE2 Position
Definition at line 1295 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE3_Msk (0x1ul << EADC_INTSRC1_SPLIE3_Pos) |
EADC_T::INTSRC1: SPLIE3 Mask
Definition at line 1299 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE3_Pos (3) |
EADC_T::INTSRC1: SPLIE3 Position
Definition at line 1298 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE4_Msk (0x1ul << EADC_INTSRC1_SPLIE4_Pos) |
EADC_T::INTSRC1: SPLIE4 Mask
Definition at line 1302 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE4_Pos (4) |
EADC_T::INTSRC1: SPLIE4 Position
Definition at line 1301 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE5_Msk (0x1ul << EADC_INTSRC1_SPLIE5_Pos) |
EADC_T::INTSRC1: SPLIE5 Mask
Definition at line 1305 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE5_Pos (5) |
EADC_T::INTSRC1: SPLIE5 Position
Definition at line 1304 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE6_Msk (0x1ul << EADC_INTSRC1_SPLIE6_Pos) |
EADC_T::INTSRC1: SPLIE6 Mask
Definition at line 1308 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE6_Pos (6) |
EADC_T::INTSRC1: SPLIE6 Position
Definition at line 1307 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE7_Msk (0x1ul << EADC_INTSRC1_SPLIE7_Pos) |
EADC_T::INTSRC1: SPLIE7 Mask
Definition at line 1311 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE7_Pos (7) |
EADC_T::INTSRC1: SPLIE7 Position
Definition at line 1310 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE8_Msk (0x1ul << EADC_INTSRC1_SPLIE8_Pos) |
EADC_T::INTSRC1: SPLIE8 Mask
Definition at line 1314 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE8_Pos (8) |
EADC_T::INTSRC1: SPLIE8 Position
Definition at line 1313 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE9_Msk (0x1ul << EADC_INTSRC1_SPLIE9_Pos) |
EADC_T::INTSRC1: SPLIE9 Mask
Definition at line 1317 of file eadc_reg.h.
| #define EADC_INTSRC1_SPLIE9_Pos (9) |
EADC_T::INTSRC1: SPLIE9 Position
Definition at line 1316 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE0_Msk (0x1ul << EADC_INTSRC2_SPLIE0_Pos) |
EADC_T::INTSRC2: SPLIE0 Mask
Definition at line 1347 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE0_Pos (0) |
EADC_T::INTSRC2: SPLIE0 Position
Definition at line 1346 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE10_Msk (0x1ul << EADC_INTSRC2_SPLIE10_Pos) |
EADC_T::INTSRC2: SPLIE10 Mask
Definition at line 1377 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE10_Pos (10) |
EADC_T::INTSRC2: SPLIE10 Position
Definition at line 1376 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE11_Msk (0x1ul << EADC_INTSRC2_SPLIE11_Pos) |
EADC_T::INTSRC2: SPLIE11 Mask
Definition at line 1380 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE11_Pos (11) |
EADC_T::INTSRC2: SPLIE11 Position
Definition at line 1379 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE12_Msk (0x1ul << EADC_INTSRC2_SPLIE12_Pos) |
EADC_T::INTSRC2: SPLIE12 Mask
Definition at line 1383 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE12_Pos (12) |
EADC_T::INTSRC2: SPLIE12 Position
Definition at line 1382 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE13_Msk (0x1ul << EADC_INTSRC2_SPLIE13_Pos) |
EADC_T::INTSRC2: SPLIE13 Mask
Definition at line 1386 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE13_Pos (13) |
EADC_T::INTSRC2: SPLIE13 Position
Definition at line 1385 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE14_Msk (0x1ul << EADC_INTSRC2_SPLIE14_Pos) |
EADC_T::INTSRC2: SPLIE14 Mask
Definition at line 1389 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE14_Pos (14) |
EADC_T::INTSRC2: SPLIE14 Position
Definition at line 1388 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE15_Msk (0x1ul << EADC_INTSRC2_SPLIE15_Pos) |
EADC_T::INTSRC2: SPLIE15 Mask
Definition at line 1392 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE15_Pos (15) |
EADC_T::INTSRC2: SPLIE15 Position
Definition at line 1391 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE16_Msk (0x1ul << EADC_INTSRC2_SPLIE16_Pos) |
EADC_T::INTSRC2: SPLIE16 Mask
Definition at line 1395 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE16_Pos (16) |
EADC_T::INTSRC2: SPLIE16 Position
Definition at line 1394 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE17_Msk (0x1ul << EADC_INTSRC2_SPLIE17_Pos) |
EADC_T::INTSRC2: SPLIE17 Mask
Definition at line 1398 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE17_Pos (17) |
EADC_T::INTSRC2: SPLIE17 Position
Definition at line 1397 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE18_Msk (0x1ul << EADC_INTSRC2_SPLIE18_Pos) |
EADC_T::INTSRC2: SPLIE18 Mask
Definition at line 1401 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE18_Pos (18) |
EADC_T::INTSRC2: SPLIE18 Position
Definition at line 1400 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE1_Msk (0x1ul << EADC_INTSRC2_SPLIE1_Pos) |
EADC_T::INTSRC2: SPLIE1 Mask
Definition at line 1350 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE1_Pos (1) |
EADC_T::INTSRC2: SPLIE1 Position
Definition at line 1349 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE2_Msk (0x1ul << EADC_INTSRC2_SPLIE2_Pos) |
EADC_T::INTSRC2: SPLIE2 Mask
Definition at line 1353 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE2_Pos (2) |
EADC_T::INTSRC2: SPLIE2 Position
Definition at line 1352 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE3_Msk (0x1ul << EADC_INTSRC2_SPLIE3_Pos) |
EADC_T::INTSRC2: SPLIE3 Mask
Definition at line 1356 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE3_Pos (3) |
EADC_T::INTSRC2: SPLIE3 Position
Definition at line 1355 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE4_Msk (0x1ul << EADC_INTSRC2_SPLIE4_Pos) |
EADC_T::INTSRC2: SPLIE4 Mask
Definition at line 1359 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE4_Pos (4) |
EADC_T::INTSRC2: SPLIE4 Position
Definition at line 1358 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE5_Msk (0x1ul << EADC_INTSRC2_SPLIE5_Pos) |
EADC_T::INTSRC2: SPLIE5 Mask
Definition at line 1362 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE5_Pos (5) |
EADC_T::INTSRC2: SPLIE5 Position
Definition at line 1361 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE6_Msk (0x1ul << EADC_INTSRC2_SPLIE6_Pos) |
EADC_T::INTSRC2: SPLIE6 Mask
Definition at line 1365 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE6_Pos (6) |
EADC_T::INTSRC2: SPLIE6 Position
Definition at line 1364 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE7_Msk (0x1ul << EADC_INTSRC2_SPLIE7_Pos) |
EADC_T::INTSRC2: SPLIE7 Mask
Definition at line 1368 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE7_Pos (7) |
EADC_T::INTSRC2: SPLIE7 Position
Definition at line 1367 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE8_Msk (0x1ul << EADC_INTSRC2_SPLIE8_Pos) |
EADC_T::INTSRC2: SPLIE8 Mask
Definition at line 1371 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE8_Pos (8) |
EADC_T::INTSRC2: SPLIE8 Position
Definition at line 1370 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE9_Msk (0x1ul << EADC_INTSRC2_SPLIE9_Pos) |
EADC_T::INTSRC2: SPLIE9 Mask
Definition at line 1374 of file eadc_reg.h.
| #define EADC_INTSRC2_SPLIE9_Pos (9) |
EADC_T::INTSRC2: SPLIE9 Position
Definition at line 1373 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE0_Msk (0x1ul << EADC_INTSRC3_SPLIE0_Pos) |
EADC_T::INTSRC3: SPLIE0 Mask
Definition at line 1404 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE0_Pos (0) |
EADC_T::INTSRC3: SPLIE0 Position
Definition at line 1403 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE10_Msk (0x1ul << EADC_INTSRC3_SPLIE10_Pos) |
EADC_T::INTSRC3: SPLIE10 Mask
Definition at line 1434 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE10_Pos (10) |
EADC_T::INTSRC3: SPLIE10 Position
Definition at line 1433 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE11_Msk (0x1ul << EADC_INTSRC3_SPLIE11_Pos) |
EADC_T::INTSRC3: SPLIE11 Mask
Definition at line 1437 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE11_Pos (11) |
EADC_T::INTSRC3: SPLIE11 Position
Definition at line 1436 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE12_Msk (0x1ul << EADC_INTSRC3_SPLIE12_Pos) |
EADC_T::INTSRC3: SPLIE12 Mask
Definition at line 1440 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE12_Pos (12) |
EADC_T::INTSRC3: SPLIE12 Position
Definition at line 1439 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE13_Msk (0x1ul << EADC_INTSRC3_SPLIE13_Pos) |
EADC_T::INTSRC3: SPLIE13 Mask
Definition at line 1443 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE13_Pos (13) |
EADC_T::INTSRC3: SPLIE13 Position
Definition at line 1442 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE14_Msk (0x1ul << EADC_INTSRC3_SPLIE14_Pos) |
EADC_T::INTSRC3: SPLIE14 Mask
Definition at line 1446 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE14_Pos (14) |
EADC_T::INTSRC3: SPLIE14 Position
Definition at line 1445 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE15_Msk (0x1ul << EADC_INTSRC3_SPLIE15_Pos) |
EADC_T::INTSRC3: SPLIE15 Mask
Definition at line 1449 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE15_Pos (15) |
EADC_T::INTSRC3: SPLIE15 Position
Definition at line 1448 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE16_Msk (0x1ul << EADC_INTSRC3_SPLIE16_Pos) |
EADC_T::INTSRC3: SPLIE16 Mask
Definition at line 1452 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE16_Pos (16) |
EADC_T::INTSRC3: SPLIE16 Position
Definition at line 1451 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE17_Msk (0x1ul << EADC_INTSRC3_SPLIE17_Pos) |
EADC_T::INTSRC3: SPLIE17 Mask
Definition at line 1455 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE17_Pos (17) |
EADC_T::INTSRC3: SPLIE17 Position
Definition at line 1454 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE18_Msk (0x1ul << EADC_INTSRC3_SPLIE18_Pos) |
EADC_T::INTSRC3: SPLIE18 Mask
Definition at line 1458 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE18_Pos (18) |
EADC_T::INTSRC3: SPLIE18 Position
Definition at line 1457 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE1_Msk (0x1ul << EADC_INTSRC3_SPLIE1_Pos) |
EADC_T::INTSRC3: SPLIE1 Mask
Definition at line 1407 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE1_Pos (1) |
EADC_T::INTSRC3: SPLIE1 Position
Definition at line 1406 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE2_Msk (0x1ul << EADC_INTSRC3_SPLIE2_Pos) |
EADC_T::INTSRC3: SPLIE2 Mask
Definition at line 1410 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE2_Pos (2) |
EADC_T::INTSRC3: SPLIE2 Position
Definition at line 1409 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE3_Msk (0x1ul << EADC_INTSRC3_SPLIE3_Pos) |
EADC_T::INTSRC3: SPLIE3 Mask
Definition at line 1413 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE3_Pos (3) |
EADC_T::INTSRC3: SPLIE3 Position
Definition at line 1412 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE4_Msk (0x1ul << EADC_INTSRC3_SPLIE4_Pos) |
EADC_T::INTSRC3: SPLIE4 Mask
Definition at line 1416 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE4_Pos (4) |
EADC_T::INTSRC3: SPLIE4 Position
Definition at line 1415 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE5_Msk (0x1ul << EADC_INTSRC3_SPLIE5_Pos) |
EADC_T::INTSRC3: SPLIE5 Mask
Definition at line 1419 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE5_Pos (5) |
EADC_T::INTSRC3: SPLIE5 Position
Definition at line 1418 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE6_Msk (0x1ul << EADC_INTSRC3_SPLIE6_Pos) |
EADC_T::INTSRC3: SPLIE6 Mask
Definition at line 1422 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE6_Pos (6) |
EADC_T::INTSRC3: SPLIE6 Position
Definition at line 1421 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE7_Msk (0x1ul << EADC_INTSRC3_SPLIE7_Pos) |
EADC_T::INTSRC3: SPLIE7 Mask
Definition at line 1425 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE7_Pos (7) |
EADC_T::INTSRC3: SPLIE7 Position
Definition at line 1424 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE8_Msk (0x1ul << EADC_INTSRC3_SPLIE8_Pos) |
EADC_T::INTSRC3: SPLIE8 Mask
Definition at line 1428 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE8_Pos (8) |
EADC_T::INTSRC3: SPLIE8 Position
Definition at line 1427 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE9_Msk (0x1ul << EADC_INTSRC3_SPLIE9_Pos) |
EADC_T::INTSRC3: SPLIE9 Mask
Definition at line 1431 of file eadc_reg.h.
| #define EADC_INTSRC3_SPLIE9_Pos (9) |
EADC_T::INTSRC3: SPLIE9 Position
Definition at line 1430 of file eadc_reg.h.
| #define EADC_OVSTS_SPOVF_Msk (0x7fffful << EADC_OVSTS_SPOVF_Pos) |
EADC_T::OVSTS: SPOVF Mask
Definition at line 798 of file eadc_reg.h.
| #define EADC_OVSTS_SPOVF_Pos (0) |
EADC_T::OVSTS: SPOVF Position
Definition at line 797 of file eadc_reg.h.
| #define EADC_PENDSTS_STPF_Msk (0x7fffful << EADC_PENDSTS_STPF_Pos) |
EADC_T::PENDSTS: STPF Mask
Definition at line 795 of file eadc_reg.h.
| #define EADC_PENDSTS_STPF_Pos (0) |
EADC_T::PENDSTS: STPF Position
Definition at line 794 of file eadc_reg.h.
| #define EADC_PWRM_LDOSUT_Msk (0xffful << EADC_PWRM_LDOSUT_Pos) |
EADC_T::PWRM: LDOSUT Mask
Definition at line 1692 of file eadc_reg.h.
| #define EADC_PWRM_LDOSUT_Pos (8) |
EADC_T::PWRM: LDOSUT Position
Definition at line 1691 of file eadc_reg.h.
| #define EADC_PWRM_PWDMOD_Msk (0x3ul << EADC_PWRM_PWDMOD_Pos) |
EADC_T::PWRM: PWDMOD Mask
Definition at line 1689 of file eadc_reg.h.
| #define EADC_PWRM_PWDMOD_Pos (2) |
EADC_T::PWRM: PWDMOD Position
Definition at line 1688 of file eadc_reg.h.
| #define EADC_PWRM_PWUCALEN_Msk (0x1ul << EADC_PWRM_PWUCALEN_Pos) |
EADC_T::PWRM: PWUCALEN Mask
Definition at line 1686 of file eadc_reg.h.
| #define EADC_PWRM_PWUCALEN_Pos (1) |
EADC_T::PWRM: PWUCALEN Position
Definition at line 1685 of file eadc_reg.h.
| #define EADC_PWRM_PWUPRDY_Msk (0x1ul << EADC_PWRM_PWUPRDY_Pos) |
EADC_T::PWRM: PWUPRDY Mask
Definition at line 1683 of file eadc_reg.h.
| #define EADC_PWRM_PWUPRDY_Pos (0) |
EADC_T::PWRM: PWUPRDY Position
Definition at line 1682 of file eadc_reg.h.
| #define EADC_SCTL0_CHSEL_Msk (0xful << EADC_SCTL0_CHSEL_Pos) |
EADC_T::SCTL0: CHSEL Mask
Definition at line 828 of file eadc_reg.h.
| #define EADC_SCTL0_CHSEL_Pos (0) |
EADC_T::SCTL0: CHSEL Position
Definition at line 827 of file eadc_reg.h.
| #define EADC_SCTL0_DBMEN_Msk (0x1ul << EADC_SCTL0_DBMEN_Pos) |
EADC_T::SCTL0: DBMEN Mask
Definition at line 849 of file eadc_reg.h.
| #define EADC_SCTL0_DBMEN_Pos (23) |
EADC_T::SCTL0: DBMEN Position
Definition at line 848 of file eadc_reg.h.
| #define EADC_SCTL0_EXTFEN_Msk (0x1ul << EADC_SCTL0_EXTFEN_Pos) |
EADC_T::SCTL0: EXTFEN Mask
Definition at line 834 of file eadc_reg.h.
| #define EADC_SCTL0_EXTFEN_Pos (5) |
EADC_T::SCTL0: EXTFEN Position
Definition at line 833 of file eadc_reg.h.
| #define EADC_SCTL0_EXTREN_Msk (0x1ul << EADC_SCTL0_EXTREN_Pos) |
EADC_T::SCTL0: EXTREN Mask
Definition at line 831 of file eadc_reg.h.
| #define EADC_SCTL0_EXTREN_Pos (4) |
EADC_T::SCTL0: EXTREN Position
Definition at line 830 of file eadc_reg.h.
| #define EADC_SCTL0_EXTSMPT_Msk (0xfful << EADC_SCTL0_EXTSMPT_Pos) |
EADC_T::SCTL0: EXTSMPT Mask
Definition at line 852 of file eadc_reg.h.
| #define EADC_SCTL0_EXTSMPT_Pos (24) |
EADC_T::SCTL0: EXTSMPT Position
Definition at line 851 of file eadc_reg.h.
| #define EADC_SCTL0_INTPOS_Msk (0x1ul << EADC_SCTL0_INTPOS_Pos) |
EADC_T::SCTL0: INTPOS Mask
Definition at line 846 of file eadc_reg.h.
| #define EADC_SCTL0_INTPOS_Pos (22) |
EADC_T::SCTL0: INTPOS Position
Definition at line 845 of file eadc_reg.h.
| #define EADC_SCTL0_TRGDLYCNT_Msk (0xfful << EADC_SCTL0_TRGDLYCNT_Pos) |
EADC_T::SCTL0: TRGDLYCNT Mask
Definition at line 840 of file eadc_reg.h.
| #define EADC_SCTL0_TRGDLYCNT_Pos (8) |
EADC_T::SCTL0: TRGDLYCNT Position
Definition at line 839 of file eadc_reg.h.
| #define EADC_SCTL0_TRGDLYDIV_Msk (0x3ul << EADC_SCTL0_TRGDLYDIV_Pos) |
EADC_T::SCTL0: TRGDLYDIV Mask
Definition at line 837 of file eadc_reg.h.
| #define EADC_SCTL0_TRGDLYDIV_Pos (6) |
EADC_T::SCTL0: TRGDLYDIV Position
Definition at line 836 of file eadc_reg.h.
| #define EADC_SCTL0_TRGSEL_Msk (0x1ful << EADC_SCTL0_TRGSEL_Pos) |
EADC_T::SCTL0: TRGSEL Mask
Definition at line 843 of file eadc_reg.h.
| #define EADC_SCTL0_TRGSEL_Pos (16) |
EADC_T::SCTL0: TRGSEL Position
Definition at line 842 of file eadc_reg.h.
| #define EADC_SCTL10_CHSEL_Msk (0xful << EADC_SCTL10_CHSEL_Pos) |
EADC_T::SCTL10: CHSEL Mask
Definition at line 1080 of file eadc_reg.h.
| #define EADC_SCTL10_CHSEL_Pos (0) |
EADC_T::SCTL10: CHSEL Position
Definition at line 1079 of file eadc_reg.h.
| #define EADC_SCTL10_EXTFEN_Msk (0x1ul << EADC_SCTL10_EXTFEN_Pos) |
EADC_T::SCTL10: EXTFEN Mask
Definition at line 1086 of file eadc_reg.h.
| #define EADC_SCTL10_EXTFEN_Pos (5) |
EADC_T::SCTL10: EXTFEN Position
Definition at line 1085 of file eadc_reg.h.
| #define EADC_SCTL10_EXTREN_Msk (0x1ul << EADC_SCTL10_EXTREN_Pos) |
EADC_T::SCTL10: EXTREN Mask
Definition at line 1083 of file eadc_reg.h.
| #define EADC_SCTL10_EXTREN_Pos (4) |
EADC_T::SCTL10: EXTREN Position
Definition at line 1082 of file eadc_reg.h.
| #define EADC_SCTL10_EXTSMPT_Msk (0xfful << EADC_SCTL10_EXTSMPT_Pos) |
EADC_T::SCTL10: EXTSMPT Mask
Definition at line 1101 of file eadc_reg.h.
| #define EADC_SCTL10_EXTSMPT_Pos (24) |
EADC_T::SCTL10: EXTSMPT Position
Definition at line 1100 of file eadc_reg.h.
| #define EADC_SCTL10_INTPOS_Msk (0x1ul << EADC_SCTL10_INTPOS_Pos) |
EADC_T::SCTL10: INTPOS Mask
Definition at line 1098 of file eadc_reg.h.
| #define EADC_SCTL10_INTPOS_Pos (22) |
EADC_T::SCTL10: INTPOS Position
Definition at line 1097 of file eadc_reg.h.
| #define EADC_SCTL10_TRGDLYCNT_Msk (0xfful << EADC_SCTL10_TRGDLYCNT_Pos) |
EADC_T::SCTL10: TRGDLYCNT Mask
Definition at line 1092 of file eadc_reg.h.
| #define EADC_SCTL10_TRGDLYCNT_Pos (8) |
EADC_T::SCTL10: TRGDLYCNT Position
Definition at line 1091 of file eadc_reg.h.
| #define EADC_SCTL10_TRGDLYDIV_Msk (0x3ul << EADC_SCTL10_TRGDLYDIV_Pos) |
EADC_T::SCTL10: TRGDLYDIV Mask
Definition at line 1089 of file eadc_reg.h.
| #define EADC_SCTL10_TRGDLYDIV_Pos (6) |
EADC_T::SCTL10: TRGDLYDIV Position
Definition at line 1088 of file eadc_reg.h.
| #define EADC_SCTL10_TRGSEL_Msk (0x1ful << EADC_SCTL10_TRGSEL_Pos) |
EADC_T::SCTL10: TRGSEL Mask
Definition at line 1095 of file eadc_reg.h.
| #define EADC_SCTL10_TRGSEL_Pos (16) |
EADC_T::SCTL10: TRGSEL Position
Definition at line 1094 of file eadc_reg.h.
| #define EADC_SCTL11_CHSEL_Msk (0xful << EADC_SCTL11_CHSEL_Pos) |
EADC_T::SCTL11: CHSEL Mask
Definition at line 1104 of file eadc_reg.h.
| #define EADC_SCTL11_CHSEL_Pos (0) |
EADC_T::SCTL11: CHSEL Position
Definition at line 1103 of file eadc_reg.h.
| #define EADC_SCTL11_EXTFEN_Msk (0x1ul << EADC_SCTL11_EXTFEN_Pos) |
EADC_T::SCTL11: EXTFEN Mask
Definition at line 1110 of file eadc_reg.h.
| #define EADC_SCTL11_EXTFEN_Pos (5) |
EADC_T::SCTL11: EXTFEN Position
Definition at line 1109 of file eadc_reg.h.
| #define EADC_SCTL11_EXTREN_Msk (0x1ul << EADC_SCTL11_EXTREN_Pos) |
EADC_T::SCTL11: EXTREN Mask
Definition at line 1107 of file eadc_reg.h.
| #define EADC_SCTL11_EXTREN_Pos (4) |
EADC_T::SCTL11: EXTREN Position
Definition at line 1106 of file eadc_reg.h.
| #define EADC_SCTL11_EXTSMPT_Msk (0xfful << EADC_SCTL11_EXTSMPT_Pos) |
EADC_T::SCTL11: EXTSMPT Mask
Definition at line 1125 of file eadc_reg.h.
| #define EADC_SCTL11_EXTSMPT_Pos (24) |
EADC_T::SCTL11: EXTSMPT Position
Definition at line 1124 of file eadc_reg.h.
| #define EADC_SCTL11_INTPOS_Msk (0x1ul << EADC_SCTL11_INTPOS_Pos) |
EADC_T::SCTL11: INTPOS Mask
Definition at line 1122 of file eadc_reg.h.
| #define EADC_SCTL11_INTPOS_Pos (22) |
EADC_T::SCTL11: INTPOS Position
Definition at line 1121 of file eadc_reg.h.
| #define EADC_SCTL11_TRGDLYCNT_Msk (0xfful << EADC_SCTL11_TRGDLYCNT_Pos) |
EADC_T::SCTL11: TRGDLYCNT Mask
Definition at line 1116 of file eadc_reg.h.
| #define EADC_SCTL11_TRGDLYCNT_Pos (8) |
EADC_T::SCTL11: TRGDLYCNT Position
Definition at line 1115 of file eadc_reg.h.
| #define EADC_SCTL11_TRGDLYDIV_Msk (0x3ul << EADC_SCTL11_TRGDLYDIV_Pos) |
EADC_T::SCTL11: TRGDLYDIV Mask
Definition at line 1113 of file eadc_reg.h.
| #define EADC_SCTL11_TRGDLYDIV_Pos (6) |
EADC_T::SCTL11: TRGDLYDIV Position
Definition at line 1112 of file eadc_reg.h.
| #define EADC_SCTL11_TRGSEL_Msk (0x1ful << EADC_SCTL11_TRGSEL_Pos) |
EADC_T::SCTL11: TRGSEL Mask
Definition at line 1119 of file eadc_reg.h.
| #define EADC_SCTL11_TRGSEL_Pos (16) |
EADC_T::SCTL11: TRGSEL Position
Definition at line 1118 of file eadc_reg.h.
| #define EADC_SCTL12_CHSEL_Msk (0xful << EADC_SCTL12_CHSEL_Pos) |
EADC_T::SCTL12: CHSEL Mask
Definition at line 1128 of file eadc_reg.h.
| #define EADC_SCTL12_CHSEL_Pos (0) |
EADC_T::SCTL12: CHSEL Position
Definition at line 1127 of file eadc_reg.h.
| #define EADC_SCTL12_EXTFEN_Msk (0x1ul << EADC_SCTL12_EXTFEN_Pos) |
EADC_T::SCTL12: EXTFEN Mask
Definition at line 1134 of file eadc_reg.h.
| #define EADC_SCTL12_EXTFEN_Pos (5) |
EADC_T::SCTL12: EXTFEN Position
Definition at line 1133 of file eadc_reg.h.
| #define EADC_SCTL12_EXTREN_Msk (0x1ul << EADC_SCTL12_EXTREN_Pos) |
EADC_T::SCTL12: EXTREN Mask
Definition at line 1131 of file eadc_reg.h.
| #define EADC_SCTL12_EXTREN_Pos (4) |
EADC_T::SCTL12: EXTREN Position
Definition at line 1130 of file eadc_reg.h.
| #define EADC_SCTL12_EXTSMPT_Msk (0xfful << EADC_SCTL12_EXTSMPT_Pos) |
EADC_T::SCTL12: EXTSMPT Mask
Definition at line 1149 of file eadc_reg.h.
| #define EADC_SCTL12_EXTSMPT_Pos (24) |
EADC_T::SCTL12: EXTSMPT Position
Definition at line 1148 of file eadc_reg.h.
| #define EADC_SCTL12_INTPOS_Msk (0x1ul << EADC_SCTL12_INTPOS_Pos) |
EADC_T::SCTL12: INTPOS Mask
Definition at line 1146 of file eadc_reg.h.
| #define EADC_SCTL12_INTPOS_Pos (22) |
EADC_T::SCTL12: INTPOS Position
Definition at line 1145 of file eadc_reg.h.
| #define EADC_SCTL12_TRGDLYCNT_Msk (0xfful << EADC_SCTL12_TRGDLYCNT_Pos) |
EADC_T::SCTL12: TRGDLYCNT Mask
Definition at line 1140 of file eadc_reg.h.
| #define EADC_SCTL12_TRGDLYCNT_Pos (8) |
EADC_T::SCTL12: TRGDLYCNT Position
Definition at line 1139 of file eadc_reg.h.
| #define EADC_SCTL12_TRGDLYDIV_Msk (0x3ul << EADC_SCTL12_TRGDLYDIV_Pos) |
EADC_T::SCTL12: TRGDLYDIV Mask
Definition at line 1137 of file eadc_reg.h.
| #define EADC_SCTL12_TRGDLYDIV_Pos (6) |
EADC_T::SCTL12: TRGDLYDIV Position
Definition at line 1136 of file eadc_reg.h.
| #define EADC_SCTL12_TRGSEL_Msk (0x1ful << EADC_SCTL12_TRGSEL_Pos) |
EADC_T::SCTL12: TRGSEL Mask
Definition at line 1143 of file eadc_reg.h.
| #define EADC_SCTL12_TRGSEL_Pos (16) |
EADC_T::SCTL12: TRGSEL Position
Definition at line 1142 of file eadc_reg.h.
| #define EADC_SCTL13_CHSEL_Msk (0xful << EADC_SCTL13_CHSEL_Pos) |
EADC_T::SCTL13: CHSEL Mask
Definition at line 1152 of file eadc_reg.h.
| #define EADC_SCTL13_CHSEL_Pos (0) |
EADC_T::SCTL13: CHSEL Position
Definition at line 1151 of file eadc_reg.h.
| #define EADC_SCTL13_EXTFEN_Msk (0x1ul << EADC_SCTL13_EXTFEN_Pos) |
EADC_T::SCTL13: EXTFEN Mask
Definition at line 1158 of file eadc_reg.h.
| #define EADC_SCTL13_EXTFEN_Pos (5) |
EADC_T::SCTL13: EXTFEN Position
Definition at line 1157 of file eadc_reg.h.
| #define EADC_SCTL13_EXTREN_Msk (0x1ul << EADC_SCTL13_EXTREN_Pos) |
EADC_T::SCTL13: EXTREN Mask
Definition at line 1155 of file eadc_reg.h.
| #define EADC_SCTL13_EXTREN_Pos (4) |
EADC_T::SCTL13: EXTREN Position
Definition at line 1154 of file eadc_reg.h.
| #define EADC_SCTL13_EXTSMPT_Msk (0xfful << EADC_SCTL13_EXTSMPT_Pos) |
EADC_T::SCTL13: EXTSMPT Mask
Definition at line 1173 of file eadc_reg.h.
| #define EADC_SCTL13_EXTSMPT_Pos (24) |
EADC_T::SCTL13: EXTSMPT Position
Definition at line 1172 of file eadc_reg.h.
| #define EADC_SCTL13_INTPOS_Msk (0x1ul << EADC_SCTL13_INTPOS_Pos) |
EADC_T::SCTL13: INTPOS Mask
Definition at line 1170 of file eadc_reg.h.
| #define EADC_SCTL13_INTPOS_Pos (22) |
EADC_T::SCTL13: INTPOS Position
Definition at line 1169 of file eadc_reg.h.
| #define EADC_SCTL13_TRGDLYCNT_Msk (0xfful << EADC_SCTL13_TRGDLYCNT_Pos) |
EADC_T::SCTL13: TRGDLYCNT Mask
Definition at line 1164 of file eadc_reg.h.
| #define EADC_SCTL13_TRGDLYCNT_Pos (8) |
EADC_T::SCTL13: TRGDLYCNT Position
Definition at line 1163 of file eadc_reg.h.
| #define EADC_SCTL13_TRGDLYDIV_Msk (0x3ul << EADC_SCTL13_TRGDLYDIV_Pos) |
EADC_T::SCTL13: TRGDLYDIV Mask
Definition at line 1161 of file eadc_reg.h.
| #define EADC_SCTL13_TRGDLYDIV_Pos (6) |
EADC_T::SCTL13: TRGDLYDIV Position
Definition at line 1160 of file eadc_reg.h.
| #define EADC_SCTL13_TRGSEL_Msk (0x1ful << EADC_SCTL13_TRGSEL_Pos) |
EADC_T::SCTL13: TRGSEL Mask
Definition at line 1167 of file eadc_reg.h.
| #define EADC_SCTL13_TRGSEL_Pos (16) |
EADC_T::SCTL13: TRGSEL Position
Definition at line 1166 of file eadc_reg.h.
| #define EADC_SCTL14_CHSEL_Msk (0xful << EADC_SCTL14_CHSEL_Pos) |
EADC_T::SCTL14: CHSEL Mask
Definition at line 1176 of file eadc_reg.h.
| #define EADC_SCTL14_CHSEL_Pos (0) |
EADC_T::SCTL14: CHSEL Position
Definition at line 1175 of file eadc_reg.h.
| #define EADC_SCTL14_EXTFEN_Msk (0x1ul << EADC_SCTL14_EXTFEN_Pos) |
EADC_T::SCTL14: EXTFEN Mask
Definition at line 1182 of file eadc_reg.h.
| #define EADC_SCTL14_EXTFEN_Pos (5) |
EADC_T::SCTL14: EXTFEN Position
Definition at line 1181 of file eadc_reg.h.
| #define EADC_SCTL14_EXTREN_Msk (0x1ul << EADC_SCTL14_EXTREN_Pos) |
EADC_T::SCTL14: EXTREN Mask
Definition at line 1179 of file eadc_reg.h.
| #define EADC_SCTL14_EXTREN_Pos (4) |
EADC_T::SCTL14: EXTREN Position
Definition at line 1178 of file eadc_reg.h.
| #define EADC_SCTL14_EXTSMPT_Msk (0xfful << EADC_SCTL14_EXTSMPT_Pos) |
EADC_T::SCTL14: EXTSMPT Mask
Definition at line 1197 of file eadc_reg.h.
| #define EADC_SCTL14_EXTSMPT_Pos (24) |
EADC_T::SCTL14: EXTSMPT Position
Definition at line 1196 of file eadc_reg.h.
| #define EADC_SCTL14_INTPOS_Msk (0x1ul << EADC_SCTL14_INTPOS_Pos) |
EADC_T::SCTL14: INTPOS Mask
Definition at line 1194 of file eadc_reg.h.
| #define EADC_SCTL14_INTPOS_Pos (22) |
EADC_T::SCTL14: INTPOS Position
Definition at line 1193 of file eadc_reg.h.
| #define EADC_SCTL14_TRGDLYCNT_Msk (0xfful << EADC_SCTL14_TRGDLYCNT_Pos) |
EADC_T::SCTL14: TRGDLYCNT Mask
Definition at line 1188 of file eadc_reg.h.
| #define EADC_SCTL14_TRGDLYCNT_Pos (8) |
EADC_T::SCTL14: TRGDLYCNT Position
Definition at line 1187 of file eadc_reg.h.
| #define EADC_SCTL14_TRGDLYDIV_Msk (0x3ul << EADC_SCTL14_TRGDLYDIV_Pos) |
EADC_T::SCTL14: TRGDLYDIV Mask
Definition at line 1185 of file eadc_reg.h.
| #define EADC_SCTL14_TRGDLYDIV_Pos (6) |
EADC_T::SCTL14: TRGDLYDIV Position
Definition at line 1184 of file eadc_reg.h.
| #define EADC_SCTL14_TRGSEL_Msk (0x1ful << EADC_SCTL14_TRGSEL_Pos) |
EADC_T::SCTL14: TRGSEL Mask
Definition at line 1191 of file eadc_reg.h.
| #define EADC_SCTL14_TRGSEL_Pos (16) |
EADC_T::SCTL14: TRGSEL Position
Definition at line 1190 of file eadc_reg.h.
| #define EADC_SCTL15_CHSEL_Msk (0xful << EADC_SCTL15_CHSEL_Pos) |
EADC_T::SCTL15: CHSEL Mask
Definition at line 1200 of file eadc_reg.h.
| #define EADC_SCTL15_CHSEL_Pos (0) |
EADC_T::SCTL15: CHSEL Position
Definition at line 1199 of file eadc_reg.h.
| #define EADC_SCTL15_EXTFEN_Msk (0x1ul << EADC_SCTL15_EXTFEN_Pos) |
EADC_T::SCTL15: EXTFEN Mask
Definition at line 1206 of file eadc_reg.h.
| #define EADC_SCTL15_EXTFEN_Pos (5) |
EADC_T::SCTL15: EXTFEN Position
Definition at line 1205 of file eadc_reg.h.
| #define EADC_SCTL15_EXTREN_Msk (0x1ul << EADC_SCTL15_EXTREN_Pos) |
EADC_T::SCTL15: EXTREN Mask
Definition at line 1203 of file eadc_reg.h.
| #define EADC_SCTL15_EXTREN_Pos (4) |
EADC_T::SCTL15: EXTREN Position
Definition at line 1202 of file eadc_reg.h.
| #define EADC_SCTL15_EXTSMPT_Msk (0xfful << EADC_SCTL15_EXTSMPT_Pos) |
EADC_T::SCTL15: EXTSMPT Mask
Definition at line 1221 of file eadc_reg.h.
| #define EADC_SCTL15_EXTSMPT_Pos (24) |
EADC_T::SCTL15: EXTSMPT Position
Definition at line 1220 of file eadc_reg.h.
| #define EADC_SCTL15_INTPOS_Msk (0x1ul << EADC_SCTL15_INTPOS_Pos) |
EADC_T::SCTL15: INTPOS Mask
Definition at line 1218 of file eadc_reg.h.
| #define EADC_SCTL15_INTPOS_Pos (22) |
EADC_T::SCTL15: INTPOS Position
Definition at line 1217 of file eadc_reg.h.
| #define EADC_SCTL15_TRGDLYCNT_Msk (0xfful << EADC_SCTL15_TRGDLYCNT_Pos) |
EADC_T::SCTL15: TRGDLYCNT Mask
Definition at line 1212 of file eadc_reg.h.
| #define EADC_SCTL15_TRGDLYCNT_Pos (8) |
EADC_T::SCTL15: TRGDLYCNT Position
Definition at line 1211 of file eadc_reg.h.
| #define EADC_SCTL15_TRGDLYDIV_Msk (0x3ul << EADC_SCTL15_TRGDLYDIV_Pos) |
EADC_T::SCTL15: TRGDLYDIV Mask
Definition at line 1209 of file eadc_reg.h.
| #define EADC_SCTL15_TRGDLYDIV_Pos (6) |
EADC_T::SCTL15: TRGDLYDIV Position
Definition at line 1208 of file eadc_reg.h.
| #define EADC_SCTL15_TRGSEL_Msk (0x1ful << EADC_SCTL15_TRGSEL_Pos) |
EADC_T::SCTL15: TRGSEL Mask
Definition at line 1215 of file eadc_reg.h.
| #define EADC_SCTL15_TRGSEL_Pos (16) |
EADC_T::SCTL15: TRGSEL Position
Definition at line 1214 of file eadc_reg.h.
| #define EADC_SCTL16_EXTSMPT_Msk (0xfful << EADC_SCTL16_EXTSMPT_Pos) |
EADC_T::SCTL16: EXTSMPT Mask
Definition at line 1224 of file eadc_reg.h.
| #define EADC_SCTL16_EXTSMPT_Pos (24) |
EADC_T::SCTL16: EXTSMPT Position
Definition at line 1223 of file eadc_reg.h.
| #define EADC_SCTL17_EXTSMPT_Msk (0xfful << EADC_SCTL17_EXTSMPT_Pos) |
EADC_T::SCTL17: EXTSMPT Mask
Definition at line 1227 of file eadc_reg.h.
| #define EADC_SCTL17_EXTSMPT_Pos (24) |
EADC_T::SCTL17: EXTSMPT Position
Definition at line 1226 of file eadc_reg.h.
| #define EADC_SCTL18_EXTSMPT_Msk (0xfful << EADC_SCTL18_EXTSMPT_Pos) |
EADC_T::SCTL18: EXTSMPT Mask
Definition at line 1230 of file eadc_reg.h.
| #define EADC_SCTL18_EXTSMPT_Pos (24) |
EADC_T::SCTL18: EXTSMPT Position
Definition at line 1229 of file eadc_reg.h.
| #define EADC_SCTL1_CHSEL_Msk (0xful << EADC_SCTL1_CHSEL_Pos) |
EADC_T::SCTL1: CHSEL Mask
Definition at line 855 of file eadc_reg.h.
| #define EADC_SCTL1_CHSEL_Pos (0) |
EADC_T::SCTL1: CHSEL Position
Definition at line 854 of file eadc_reg.h.
| #define EADC_SCTL1_DBMEN_Msk (0x1ul << EADC_SCTL1_DBMEN_Pos) |
EADC_T::SCTL1: DBMEN Mask
Definition at line 876 of file eadc_reg.h.
| #define EADC_SCTL1_DBMEN_Pos (23) |
EADC_T::SCTL1: DBMEN Position
Definition at line 875 of file eadc_reg.h.
| #define EADC_SCTL1_EXTFEN_Msk (0x1ul << EADC_SCTL1_EXTFEN_Pos) |
EADC_T::SCTL1: EXTFEN Mask
Definition at line 861 of file eadc_reg.h.
| #define EADC_SCTL1_EXTFEN_Pos (5) |
EADC_T::SCTL1: EXTFEN Position
Definition at line 860 of file eadc_reg.h.
| #define EADC_SCTL1_EXTREN_Msk (0x1ul << EADC_SCTL1_EXTREN_Pos) |
EADC_T::SCTL1: EXTREN Mask
Definition at line 858 of file eadc_reg.h.
| #define EADC_SCTL1_EXTREN_Pos (4) |
EADC_T::SCTL1: EXTREN Position
Definition at line 857 of file eadc_reg.h.
| #define EADC_SCTL1_EXTSMPT_Msk (0xfful << EADC_SCTL1_EXTSMPT_Pos) |
EADC_T::SCTL1: EXTSMPT Mask
Definition at line 879 of file eadc_reg.h.
| #define EADC_SCTL1_EXTSMPT_Pos (24) |
EADC_T::SCTL1: EXTSMPT Position
Definition at line 878 of file eadc_reg.h.
| #define EADC_SCTL1_INTPOS_Msk (0x1ul << EADC_SCTL1_INTPOS_Pos) |
EADC_T::SCTL1: INTPOS Mask
Definition at line 873 of file eadc_reg.h.
| #define EADC_SCTL1_INTPOS_Pos (22) |
EADC_T::SCTL1: INTPOS Position
Definition at line 872 of file eadc_reg.h.
| #define EADC_SCTL1_TRGDLYCNT_Msk (0xfful << EADC_SCTL1_TRGDLYCNT_Pos) |
EADC_T::SCTL1: TRGDLYCNT Mask
Definition at line 867 of file eadc_reg.h.
| #define EADC_SCTL1_TRGDLYCNT_Pos (8) |
EADC_T::SCTL1: TRGDLYCNT Position
Definition at line 866 of file eadc_reg.h.
| #define EADC_SCTL1_TRGDLYDIV_Msk (0x3ul << EADC_SCTL1_TRGDLYDIV_Pos) |
EADC_T::SCTL1: TRGDLYDIV Mask
Definition at line 864 of file eadc_reg.h.
| #define EADC_SCTL1_TRGDLYDIV_Pos (6) |
EADC_T::SCTL1: TRGDLYDIV Position
Definition at line 863 of file eadc_reg.h.
| #define EADC_SCTL1_TRGSEL_Msk (0x1ful << EADC_SCTL1_TRGSEL_Pos) |
EADC_T::SCTL1: TRGSEL Mask
Definition at line 870 of file eadc_reg.h.
| #define EADC_SCTL1_TRGSEL_Pos (16) |
EADC_T::SCTL1: TRGSEL Position
Definition at line 869 of file eadc_reg.h.
| #define EADC_SCTL2_CHSEL_Msk (0xful << EADC_SCTL2_CHSEL_Pos) |
EADC_T::SCTL2: CHSEL Mask
Definition at line 882 of file eadc_reg.h.
| #define EADC_SCTL2_CHSEL_Pos (0) |
EADC_T::SCTL2: CHSEL Position
Definition at line 881 of file eadc_reg.h.
| #define EADC_SCTL2_DBMEN_Msk (0x1ul << EADC_SCTL2_DBMEN_Pos) |
EADC_T::SCTL2: DBMEN Mask
Definition at line 903 of file eadc_reg.h.
| #define EADC_SCTL2_DBMEN_Pos (23) |
EADC_T::SCTL2: DBMEN Position
Definition at line 902 of file eadc_reg.h.
| #define EADC_SCTL2_EXTFEN_Msk (0x1ul << EADC_SCTL2_EXTFEN_Pos) |
EADC_T::SCTL2: EXTFEN Mask
Definition at line 888 of file eadc_reg.h.
| #define EADC_SCTL2_EXTFEN_Pos (5) |
EADC_T::SCTL2: EXTFEN Position
Definition at line 887 of file eadc_reg.h.
| #define EADC_SCTL2_EXTREN_Msk (0x1ul << EADC_SCTL2_EXTREN_Pos) |
EADC_T::SCTL2: EXTREN Mask
Definition at line 885 of file eadc_reg.h.
| #define EADC_SCTL2_EXTREN_Pos (4) |
EADC_T::SCTL2: EXTREN Position
Definition at line 884 of file eadc_reg.h.
| #define EADC_SCTL2_EXTSMPT_Msk (0xfful << EADC_SCTL2_EXTSMPT_Pos) |
EADC_T::SCTL2: EXTSMPT Mask
Definition at line 906 of file eadc_reg.h.
| #define EADC_SCTL2_EXTSMPT_Pos (24) |
EADC_T::SCTL2: EXTSMPT Position
Definition at line 905 of file eadc_reg.h.
| #define EADC_SCTL2_INTPOS_Msk (0x1ul << EADC_SCTL2_INTPOS_Pos) |
EADC_T::SCTL2: INTPOS Mask
Definition at line 900 of file eadc_reg.h.
| #define EADC_SCTL2_INTPOS_Pos (22) |
EADC_T::SCTL2: INTPOS Position
Definition at line 899 of file eadc_reg.h.
| #define EADC_SCTL2_TRGDLYCNT_Msk (0xfful << EADC_SCTL2_TRGDLYCNT_Pos) |
EADC_T::SCTL2: TRGDLYCNT Mask
Definition at line 894 of file eadc_reg.h.
| #define EADC_SCTL2_TRGDLYCNT_Pos (8) |
EADC_T::SCTL2: TRGDLYCNT Position
Definition at line 893 of file eadc_reg.h.
| #define EADC_SCTL2_TRGDLYDIV_Msk (0x3ul << EADC_SCTL2_TRGDLYDIV_Pos) |
EADC_T::SCTL2: TRGDLYDIV Mask
Definition at line 891 of file eadc_reg.h.
| #define EADC_SCTL2_TRGDLYDIV_Pos (6) |
EADC_T::SCTL2: TRGDLYDIV Position
Definition at line 890 of file eadc_reg.h.
| #define EADC_SCTL2_TRGSEL_Msk (0x1ful << EADC_SCTL2_TRGSEL_Pos) |
EADC_T::SCTL2: TRGSEL Mask
Definition at line 897 of file eadc_reg.h.
| #define EADC_SCTL2_TRGSEL_Pos (16) |
EADC_T::SCTL2: TRGSEL Position
Definition at line 896 of file eadc_reg.h.
| #define EADC_SCTL3_CHSEL_Msk (0xful << EADC_SCTL3_CHSEL_Pos) |
EADC_T::SCTL3: CHSEL Mask
Definition at line 909 of file eadc_reg.h.
| #define EADC_SCTL3_CHSEL_Pos (0) |
EADC_T::SCTL3: CHSEL Position
Definition at line 908 of file eadc_reg.h.
| #define EADC_SCTL3_DBMEN_Msk (0x1ul << EADC_SCTL3_DBMEN_Pos) |
EADC_T::SCTL3: DBMEN Mask
Definition at line 930 of file eadc_reg.h.
| #define EADC_SCTL3_DBMEN_Pos (23) |
EADC_T::SCTL3: DBMEN Position
Definition at line 929 of file eadc_reg.h.
| #define EADC_SCTL3_EXTFEN_Msk (0x1ul << EADC_SCTL3_EXTFEN_Pos) |
EADC_T::SCTL3: EXTFEN Mask
Definition at line 915 of file eadc_reg.h.
| #define EADC_SCTL3_EXTFEN_Pos (5) |
EADC_T::SCTL3: EXTFEN Position
Definition at line 914 of file eadc_reg.h.
| #define EADC_SCTL3_EXTREN_Msk (0x1ul << EADC_SCTL3_EXTREN_Pos) |
EADC_T::SCTL3: EXTREN Mask
Definition at line 912 of file eadc_reg.h.
| #define EADC_SCTL3_EXTREN_Pos (4) |
EADC_T::SCTL3: EXTREN Position
Definition at line 911 of file eadc_reg.h.
| #define EADC_SCTL3_EXTSMPT_Msk (0xfful << EADC_SCTL3_EXTSMPT_Pos) |
EADC_T::SCTL3: EXTSMPT Mask
Definition at line 933 of file eadc_reg.h.
| #define EADC_SCTL3_EXTSMPT_Pos (24) |
EADC_T::SCTL3: EXTSMPT Position
Definition at line 932 of file eadc_reg.h.
| #define EADC_SCTL3_INTPOS_Msk (0x1ul << EADC_SCTL3_INTPOS_Pos) |
EADC_T::SCTL3: INTPOS Mask
Definition at line 927 of file eadc_reg.h.
| #define EADC_SCTL3_INTPOS_Pos (22) |
EADC_T::SCTL3: INTPOS Position
Definition at line 926 of file eadc_reg.h.
| #define EADC_SCTL3_TRGDLYCNT_Msk (0xfful << EADC_SCTL3_TRGDLYCNT_Pos) |
EADC_T::SCTL3: TRGDLYCNT Mask
Definition at line 921 of file eadc_reg.h.
| #define EADC_SCTL3_TRGDLYCNT_Pos (8) |
EADC_T::SCTL3: TRGDLYCNT Position
Definition at line 920 of file eadc_reg.h.
| #define EADC_SCTL3_TRGDLYDIV_Msk (0x3ul << EADC_SCTL3_TRGDLYDIV_Pos) |
EADC_T::SCTL3: TRGDLYDIV Mask
Definition at line 918 of file eadc_reg.h.
| #define EADC_SCTL3_TRGDLYDIV_Pos (6) |
EADC_T::SCTL3: TRGDLYDIV Position
Definition at line 917 of file eadc_reg.h.
| #define EADC_SCTL3_TRGSEL_Msk (0x1ful << EADC_SCTL3_TRGSEL_Pos) |
EADC_T::SCTL3: TRGSEL Mask
Definition at line 924 of file eadc_reg.h.
| #define EADC_SCTL3_TRGSEL_Pos (16) |
EADC_T::SCTL3: TRGSEL Position
Definition at line 923 of file eadc_reg.h.
| #define EADC_SCTL4_CHSEL_Msk (0xful << EADC_SCTL4_CHSEL_Pos) |
EADC_T::SCTL4: CHSEL Mask
Definition at line 936 of file eadc_reg.h.
| #define EADC_SCTL4_CHSEL_Pos (0) |
EADC_T::SCTL4: CHSEL Position
Definition at line 935 of file eadc_reg.h.
| #define EADC_SCTL4_EXTFEN_Msk (0x1ul << EADC_SCTL4_EXTFEN_Pos) |
EADC_T::SCTL4: EXTFEN Mask
Definition at line 942 of file eadc_reg.h.
| #define EADC_SCTL4_EXTFEN_Pos (5) |
EADC_T::SCTL4: EXTFEN Position
Definition at line 941 of file eadc_reg.h.
| #define EADC_SCTL4_EXTREN_Msk (0x1ul << EADC_SCTL4_EXTREN_Pos) |
EADC_T::SCTL4: EXTREN Mask
Definition at line 939 of file eadc_reg.h.
| #define EADC_SCTL4_EXTREN_Pos (4) |
EADC_T::SCTL4: EXTREN Position
Definition at line 938 of file eadc_reg.h.
| #define EADC_SCTL4_EXTSMPT_Msk (0xfful << EADC_SCTL4_EXTSMPT_Pos) |
EADC_T::SCTL4: EXTSMPT Mask
Definition at line 957 of file eadc_reg.h.
| #define EADC_SCTL4_EXTSMPT_Pos (24) |
EADC_T::SCTL4: EXTSMPT Position
Definition at line 956 of file eadc_reg.h.
| #define EADC_SCTL4_INTPOS_Msk (0x1ul << EADC_SCTL4_INTPOS_Pos) |
EADC_T::SCTL4: INTPOS Mask
Definition at line 954 of file eadc_reg.h.
| #define EADC_SCTL4_INTPOS_Pos (22) |
EADC_T::SCTL4: INTPOS Position
Definition at line 953 of file eadc_reg.h.
| #define EADC_SCTL4_TRGDLYCNT_Msk (0xfful << EADC_SCTL4_TRGDLYCNT_Pos) |
EADC_T::SCTL4: TRGDLYCNT Mask
Definition at line 948 of file eadc_reg.h.
| #define EADC_SCTL4_TRGDLYCNT_Pos (8) |
EADC_T::SCTL4: TRGDLYCNT Position
Definition at line 947 of file eadc_reg.h.
| #define EADC_SCTL4_TRGDLYDIV_Msk (0x3ul << EADC_SCTL4_TRGDLYDIV_Pos) |
EADC_T::SCTL4: TRGDLYDIV Mask
Definition at line 945 of file eadc_reg.h.
| #define EADC_SCTL4_TRGDLYDIV_Pos (6) |
EADC_T::SCTL4: TRGDLYDIV Position
Definition at line 944 of file eadc_reg.h.
| #define EADC_SCTL4_TRGSEL_Msk (0x1ful << EADC_SCTL4_TRGSEL_Pos) |
EADC_T::SCTL4: TRGSEL Mask
Definition at line 951 of file eadc_reg.h.
| #define EADC_SCTL4_TRGSEL_Pos (16) |
EADC_T::SCTL4: TRGSEL Position
Definition at line 950 of file eadc_reg.h.
| #define EADC_SCTL5_CHSEL_Msk (0xful << EADC_SCTL5_CHSEL_Pos) |
EADC_T::SCTL5: CHSEL Mask
Definition at line 960 of file eadc_reg.h.
| #define EADC_SCTL5_CHSEL_Pos (0) |
EADC_T::SCTL5: CHSEL Position
Definition at line 959 of file eadc_reg.h.
| #define EADC_SCTL5_EXTFEN_Msk (0x1ul << EADC_SCTL5_EXTFEN_Pos) |
EADC_T::SCTL5: EXTFEN Mask
Definition at line 966 of file eadc_reg.h.
| #define EADC_SCTL5_EXTFEN_Pos (5) |
EADC_T::SCTL5: EXTFEN Position
Definition at line 965 of file eadc_reg.h.
| #define EADC_SCTL5_EXTREN_Msk (0x1ul << EADC_SCTL5_EXTREN_Pos) |
EADC_T::SCTL5: EXTREN Mask
Definition at line 963 of file eadc_reg.h.
| #define EADC_SCTL5_EXTREN_Pos (4) |
EADC_T::SCTL5: EXTREN Position
Definition at line 962 of file eadc_reg.h.
| #define EADC_SCTL5_EXTSMPT_Msk (0xfful << EADC_SCTL5_EXTSMPT_Pos) |
EADC_T::SCTL5: EXTSMPT Mask
Definition at line 981 of file eadc_reg.h.
| #define EADC_SCTL5_EXTSMPT_Pos (24) |
EADC_T::SCTL5: EXTSMPT Position
Definition at line 980 of file eadc_reg.h.
| #define EADC_SCTL5_INTPOS_Msk (0x1ul << EADC_SCTL5_INTPOS_Pos) |
EADC_T::SCTL5: INTPOS Mask
Definition at line 978 of file eadc_reg.h.
| #define EADC_SCTL5_INTPOS_Pos (22) |
EADC_T::SCTL5: INTPOS Position
Definition at line 977 of file eadc_reg.h.
| #define EADC_SCTL5_TRGDLYCNT_Msk (0xfful << EADC_SCTL5_TRGDLYCNT_Pos) |
EADC_T::SCTL5: TRGDLYCNT Mask
Definition at line 972 of file eadc_reg.h.
| #define EADC_SCTL5_TRGDLYCNT_Pos (8) |
EADC_T::SCTL5: TRGDLYCNT Position
Definition at line 971 of file eadc_reg.h.
| #define EADC_SCTL5_TRGDLYDIV_Msk (0x3ul << EADC_SCTL5_TRGDLYDIV_Pos) |
EADC_T::SCTL5: TRGDLYDIV Mask
Definition at line 969 of file eadc_reg.h.
| #define EADC_SCTL5_TRGDLYDIV_Pos (6) |
EADC_T::SCTL5: TRGDLYDIV Position
Definition at line 968 of file eadc_reg.h.
| #define EADC_SCTL5_TRGSEL_Msk (0x1ful << EADC_SCTL5_TRGSEL_Pos) |
EADC_T::SCTL5: TRGSEL Mask
Definition at line 975 of file eadc_reg.h.
| #define EADC_SCTL5_TRGSEL_Pos (16) |
EADC_T::SCTL5: TRGSEL Position
Definition at line 974 of file eadc_reg.h.
| #define EADC_SCTL6_CHSEL_Msk (0xful << EADC_SCTL6_CHSEL_Pos) |
EADC_T::SCTL6: CHSEL Mask
Definition at line 984 of file eadc_reg.h.
| #define EADC_SCTL6_CHSEL_Pos (0) |
EADC_T::SCTL6: CHSEL Position
Definition at line 983 of file eadc_reg.h.
| #define EADC_SCTL6_EXTFEN_Msk (0x1ul << EADC_SCTL6_EXTFEN_Pos) |
EADC_T::SCTL6: EXTFEN Mask
Definition at line 990 of file eadc_reg.h.
| #define EADC_SCTL6_EXTFEN_Pos (5) |
EADC_T::SCTL6: EXTFEN Position
Definition at line 989 of file eadc_reg.h.
| #define EADC_SCTL6_EXTREN_Msk (0x1ul << EADC_SCTL6_EXTREN_Pos) |
EADC_T::SCTL6: EXTREN Mask
Definition at line 987 of file eadc_reg.h.
| #define EADC_SCTL6_EXTREN_Pos (4) |
EADC_T::SCTL6: EXTREN Position
Definition at line 986 of file eadc_reg.h.
| #define EADC_SCTL6_EXTSMPT_Msk (0xfful << EADC_SCTL6_EXTSMPT_Pos) |
EADC_T::SCTL6: EXTSMPT Mask
Definition at line 1005 of file eadc_reg.h.
| #define EADC_SCTL6_EXTSMPT_Pos (24) |
EADC_T::SCTL6: EXTSMPT Position
Definition at line 1004 of file eadc_reg.h.
| #define EADC_SCTL6_INTPOS_Msk (0x1ul << EADC_SCTL6_INTPOS_Pos) |
EADC_T::SCTL6: INTPOS Mask
Definition at line 1002 of file eadc_reg.h.
| #define EADC_SCTL6_INTPOS_Pos (22) |
EADC_T::SCTL6: INTPOS Position
Definition at line 1001 of file eadc_reg.h.
| #define EADC_SCTL6_TRGDLYCNT_Msk (0xfful << EADC_SCTL6_TRGDLYCNT_Pos) |
EADC_T::SCTL6: TRGDLYCNT Mask
Definition at line 996 of file eadc_reg.h.
| #define EADC_SCTL6_TRGDLYCNT_Pos (8) |
EADC_T::SCTL6: TRGDLYCNT Position
Definition at line 995 of file eadc_reg.h.
| #define EADC_SCTL6_TRGDLYDIV_Msk (0x3ul << EADC_SCTL6_TRGDLYDIV_Pos) |
EADC_T::SCTL6: TRGDLYDIV Mask
Definition at line 993 of file eadc_reg.h.
| #define EADC_SCTL6_TRGDLYDIV_Pos (6) |
EADC_T::SCTL6: TRGDLYDIV Position
Definition at line 992 of file eadc_reg.h.
| #define EADC_SCTL6_TRGSEL_Msk (0x1ful << EADC_SCTL6_TRGSEL_Pos) |
EADC_T::SCTL6: TRGSEL Mask
Definition at line 999 of file eadc_reg.h.
| #define EADC_SCTL6_TRGSEL_Pos (16) |
EADC_T::SCTL6: TRGSEL Position
Definition at line 998 of file eadc_reg.h.
| #define EADC_SCTL7_CHSEL_Msk (0xful << EADC_SCTL7_CHSEL_Pos) |
EADC_T::SCTL7: CHSEL Mask
Definition at line 1008 of file eadc_reg.h.
| #define EADC_SCTL7_CHSEL_Pos (0) |
EADC_T::SCTL7: CHSEL Position
Definition at line 1007 of file eadc_reg.h.
| #define EADC_SCTL7_EXTFEN_Msk (0x1ul << EADC_SCTL7_EXTFEN_Pos) |
EADC_T::SCTL7: EXTFEN Mask
Definition at line 1014 of file eadc_reg.h.
| #define EADC_SCTL7_EXTFEN_Pos (5) |
EADC_T::SCTL7: EXTFEN Position
Definition at line 1013 of file eadc_reg.h.
| #define EADC_SCTL7_EXTREN_Msk (0x1ul << EADC_SCTL7_EXTREN_Pos) |
EADC_T::SCTL7: EXTREN Mask
Definition at line 1011 of file eadc_reg.h.
| #define EADC_SCTL7_EXTREN_Pos (4) |
EADC_T::SCTL7: EXTREN Position
Definition at line 1010 of file eadc_reg.h.
| #define EADC_SCTL7_EXTSMPT_Msk (0xfful << EADC_SCTL7_EXTSMPT_Pos) |
EADC_T::SCTL7: EXTSMPT Mask
Definition at line 1029 of file eadc_reg.h.
| #define EADC_SCTL7_EXTSMPT_Pos (24) |
EADC_T::SCTL7: EXTSMPT Position
Definition at line 1028 of file eadc_reg.h.
| #define EADC_SCTL7_INTPOS_Msk (0x1ul << EADC_SCTL7_INTPOS_Pos) |
EADC_T::SCTL7: INTPOS Mask
Definition at line 1026 of file eadc_reg.h.
| #define EADC_SCTL7_INTPOS_Pos (22) |
EADC_T::SCTL7: INTPOS Position
Definition at line 1025 of file eadc_reg.h.
| #define EADC_SCTL7_TRGDLYCNT_Msk (0xfful << EADC_SCTL7_TRGDLYCNT_Pos) |
EADC_T::SCTL7: TRGDLYCNT Mask
Definition at line 1020 of file eadc_reg.h.
| #define EADC_SCTL7_TRGDLYCNT_Pos (8) |
EADC_T::SCTL7: TRGDLYCNT Position
Definition at line 1019 of file eadc_reg.h.
| #define EADC_SCTL7_TRGDLYDIV_Msk (0x3ul << EADC_SCTL7_TRGDLYDIV_Pos) |
EADC_T::SCTL7: TRGDLYDIV Mask
Definition at line 1017 of file eadc_reg.h.
| #define EADC_SCTL7_TRGDLYDIV_Pos (6) |
EADC_T::SCTL7: TRGDLYDIV Position
Definition at line 1016 of file eadc_reg.h.
| #define EADC_SCTL7_TRGSEL_Msk (0x1ful << EADC_SCTL7_TRGSEL_Pos) |
EADC_T::SCTL7: TRGSEL Mask
Definition at line 1023 of file eadc_reg.h.
| #define EADC_SCTL7_TRGSEL_Pos (16) |
EADC_T::SCTL7: TRGSEL Position
Definition at line 1022 of file eadc_reg.h.
| #define EADC_SCTL8_CHSEL_Msk (0xful << EADC_SCTL8_CHSEL_Pos) |
EADC_T::SCTL8: CHSEL Mask
Definition at line 1032 of file eadc_reg.h.
| #define EADC_SCTL8_CHSEL_Pos (0) |
EADC_T::SCTL8: CHSEL Position
Definition at line 1031 of file eadc_reg.h.
| #define EADC_SCTL8_EXTFEN_Msk (0x1ul << EADC_SCTL8_EXTFEN_Pos) |
EADC_T::SCTL8: EXTFEN Mask
Definition at line 1038 of file eadc_reg.h.
| #define EADC_SCTL8_EXTFEN_Pos (5) |
EADC_T::SCTL8: EXTFEN Position
Definition at line 1037 of file eadc_reg.h.
| #define EADC_SCTL8_EXTREN_Msk (0x1ul << EADC_SCTL8_EXTREN_Pos) |
EADC_T::SCTL8: EXTREN Mask
Definition at line 1035 of file eadc_reg.h.
| #define EADC_SCTL8_EXTREN_Pos (4) |
EADC_T::SCTL8: EXTREN Position
Definition at line 1034 of file eadc_reg.h.
| #define EADC_SCTL8_EXTSMPT_Msk (0xfful << EADC_SCTL8_EXTSMPT_Pos) |
EADC_T::SCTL8: EXTSMPT Mask
Definition at line 1053 of file eadc_reg.h.
| #define EADC_SCTL8_EXTSMPT_Pos (24) |
EADC_T::SCTL8: EXTSMPT Position
Definition at line 1052 of file eadc_reg.h.
| #define EADC_SCTL8_INTPOS_Msk (0x1ul << EADC_SCTL8_INTPOS_Pos) |
EADC_T::SCTL8: INTPOS Mask
Definition at line 1050 of file eadc_reg.h.
| #define EADC_SCTL8_INTPOS_Pos (22) |
EADC_T::SCTL8: INTPOS Position
Definition at line 1049 of file eadc_reg.h.
| #define EADC_SCTL8_TRGDLYCNT_Msk (0xfful << EADC_SCTL8_TRGDLYCNT_Pos) |
EADC_T::SCTL8: TRGDLYCNT Mask
Definition at line 1044 of file eadc_reg.h.
| #define EADC_SCTL8_TRGDLYCNT_Pos (8) |
EADC_T::SCTL8: TRGDLYCNT Position
Definition at line 1043 of file eadc_reg.h.
| #define EADC_SCTL8_TRGDLYDIV_Msk (0x3ul << EADC_SCTL8_TRGDLYDIV_Pos) |
EADC_T::SCTL8: TRGDLYDIV Mask
Definition at line 1041 of file eadc_reg.h.
| #define EADC_SCTL8_TRGDLYDIV_Pos (6) |
EADC_T::SCTL8: TRGDLYDIV Position
Definition at line 1040 of file eadc_reg.h.
| #define EADC_SCTL8_TRGSEL_Msk (0x1ful << EADC_SCTL8_TRGSEL_Pos) |
EADC_T::SCTL8: TRGSEL Mask
Definition at line 1047 of file eadc_reg.h.
| #define EADC_SCTL8_TRGSEL_Pos (16) |
EADC_T::SCTL8: TRGSEL Position
Definition at line 1046 of file eadc_reg.h.
| #define EADC_SCTL9_CHSEL_Msk (0xful << EADC_SCTL9_CHSEL_Pos) |
EADC_T::SCTL9: CHSEL Mask
Definition at line 1056 of file eadc_reg.h.
| #define EADC_SCTL9_CHSEL_Pos (0) |
EADC_T::SCTL9: CHSEL Position
Definition at line 1055 of file eadc_reg.h.
| #define EADC_SCTL9_EXTFEN_Msk (0x1ul << EADC_SCTL9_EXTFEN_Pos) |
EADC_T::SCTL9: EXTFEN Mask
Definition at line 1062 of file eadc_reg.h.
| #define EADC_SCTL9_EXTFEN_Pos (5) |
EADC_T::SCTL9: EXTFEN Position
Definition at line 1061 of file eadc_reg.h.
| #define EADC_SCTL9_EXTREN_Msk (0x1ul << EADC_SCTL9_EXTREN_Pos) |
EADC_T::SCTL9: EXTREN Mask
Definition at line 1059 of file eadc_reg.h.
| #define EADC_SCTL9_EXTREN_Pos (4) |
EADC_T::SCTL9: EXTREN Position
Definition at line 1058 of file eadc_reg.h.
| #define EADC_SCTL9_EXTSMPT_Msk (0xfful << EADC_SCTL9_EXTSMPT_Pos) |
EADC_T::SCTL9: EXTSMPT Mask
Definition at line 1077 of file eadc_reg.h.
| #define EADC_SCTL9_EXTSMPT_Pos (24) |
EADC_T::SCTL9: EXTSMPT Position
Definition at line 1076 of file eadc_reg.h.
| #define EADC_SCTL9_INTPOS_Msk (0x1ul << EADC_SCTL9_INTPOS_Pos) |
EADC_T::SCTL9: INTPOS Mask
Definition at line 1074 of file eadc_reg.h.
| #define EADC_SCTL9_INTPOS_Pos (22) |
EADC_T::SCTL9: INTPOS Position
Definition at line 1073 of file eadc_reg.h.
| #define EADC_SCTL9_TRGDLYCNT_Msk (0xfful << EADC_SCTL9_TRGDLYCNT_Pos) |
EADC_T::SCTL9: TRGDLYCNT Mask
Definition at line 1068 of file eadc_reg.h.
| #define EADC_SCTL9_TRGDLYCNT_Pos (8) |
EADC_T::SCTL9: TRGDLYCNT Position
Definition at line 1067 of file eadc_reg.h.
| #define EADC_SCTL9_TRGDLYDIV_Msk (0x3ul << EADC_SCTL9_TRGDLYDIV_Pos) |
EADC_T::SCTL9: TRGDLYDIV Mask
Definition at line 1065 of file eadc_reg.h.
| #define EADC_SCTL9_TRGDLYDIV_Pos (6) |
EADC_T::SCTL9: TRGDLYDIV Position
Definition at line 1064 of file eadc_reg.h.
| #define EADC_SCTL9_TRGSEL_Msk (0x1ful << EADC_SCTL9_TRGSEL_Pos) |
EADC_T::SCTL9: TRGSEL Mask
Definition at line 1071 of file eadc_reg.h.
| #define EADC_SCTL9_TRGSEL_Pos (16) |
EADC_T::SCTL9: TRGSEL Position
Definition at line 1070 of file eadc_reg.h.
| #define EADC_SCTL_CHSEL_Msk (0xful << EADC_SCTL_CHSEL_Pos) |
EADC_T::SCTL: CHSEL Mask
Definition at line 801 of file eadc_reg.h.
| #define EADC_SCTL_CHSEL_Pos (0) |
EADC_T::SCTL: CHSEL Position
Definition at line 800 of file eadc_reg.h.
| #define EADC_SCTL_DBMEN_Msk (0x1ul << EADC_SCTL_DBMEN_Pos) |
EADC_T::SCTL: DBMEN Mask
Definition at line 822 of file eadc_reg.h.
| #define EADC_SCTL_DBMEN_Pos (23) |
EADC_T::SCTL: DBMEN Position
Definition at line 821 of file eadc_reg.h.
| #define EADC_SCTL_EXTFEN_Msk (0x1ul << EADC_SCTL_EXTFEN_Pos) |
EADC_T::SCTL: EXTFEN Mask
Definition at line 807 of file eadc_reg.h.
| #define EADC_SCTL_EXTFEN_Pos (5) |
EADC_T::SCTL: EXTFEN Position
Definition at line 806 of file eadc_reg.h.
| #define EADC_SCTL_EXTREN_Msk (0x1ul << EADC_SCTL_EXTREN_Pos) |
EADC_T::SCTL: EXTREN Mask
Definition at line 804 of file eadc_reg.h.
| #define EADC_SCTL_EXTREN_Pos (4) |
EADC_T::SCTL: EXTREN Position
Definition at line 803 of file eadc_reg.h.
| #define EADC_SCTL_EXTSMPT_Msk (0xfful << EADC_SCTL_EXTSMPT_Pos) |
EADC_T::SCTL: EXTSMPT Mask
Definition at line 825 of file eadc_reg.h.
| #define EADC_SCTL_EXTSMPT_Pos (24) |
EADC_T::SCTL: EXTSMPT Position
Definition at line 824 of file eadc_reg.h.
| #define EADC_SCTL_INTPOS_Msk (0x1ul << EADC_SCTL_INTPOS_Pos) |
EADC_T::SCTL: INTPOS Mask
Definition at line 819 of file eadc_reg.h.
| #define EADC_SCTL_INTPOS_Pos (22) |
EADC_T::SCTL: INTPOS Position
Definition at line 818 of file eadc_reg.h.
| #define EADC_SCTL_TRGDLYCNT_Msk (0xfful << EADC_SCTL_TRGDLYCNT_Pos) |
EADC_T::SCTL: TRGDLYCNT Mask
Definition at line 813 of file eadc_reg.h.
| #define EADC_SCTL_TRGDLYCNT_Pos (8) |
EADC_T::SCTL: TRGDLYCNT Position
Definition at line 812 of file eadc_reg.h.
| #define EADC_SCTL_TRGDLYDIV_Msk (0x3ul << EADC_SCTL_TRGDLYDIV_Pos) |
EADC_T::SCTL: TRGDLYDIV Mask
Definition at line 810 of file eadc_reg.h.
| #define EADC_SCTL_TRGDLYDIV_Pos (6) |
EADC_T::SCTL: TRGDLYDIV Position
Definition at line 809 of file eadc_reg.h.
| #define EADC_SCTL_TRGSEL_Msk (0x1ful << EADC_SCTL_TRGSEL_Pos) |
EADC_T::SCTL: TRGSEL Mask
Definition at line 816 of file eadc_reg.h.
| #define EADC_SCTL_TRGSEL_Pos (16) |
EADC_T::SCTL: TRGSEL Position
Definition at line 815 of file eadc_reg.h.
| #define EADC_STATUS0_OV_Msk (0xfffful << EADC_STATUS0_OV_Pos) |
EADC_T::STATUS0: OV Mask
Definition at line 1569 of file eadc_reg.h.
| #define EADC_STATUS0_OV_Pos (16) |
EADC_T::STATUS0: OV Position
Definition at line 1568 of file eadc_reg.h.
| #define EADC_STATUS0_VALID_Msk (0xfffful << EADC_STATUS0_VALID_Pos) |
EADC_T::STATUS0: VALID Mask
Definition at line 1566 of file eadc_reg.h.
| #define EADC_STATUS0_VALID_Pos (0) |
EADC_T::STATUS0: VALID Position
Definition at line 1565 of file eadc_reg.h.
| #define EADC_STATUS1_OV_Msk (0x7ul << EADC_STATUS1_OV_Pos) |
EADC_T::STATUS1: OV Mask
Definition at line 1575 of file eadc_reg.h.
| #define EADC_STATUS1_OV_Pos (16) |
EADC_T::STATUS1: OV Position
Definition at line 1574 of file eadc_reg.h.
| #define EADC_STATUS1_VALID_Msk (0x7ul << EADC_STATUS1_VALID_Pos) |
EADC_T::STATUS1: VALID Mask
Definition at line 1572 of file eadc_reg.h.
| #define EADC_STATUS1_VALID_Pos (0) |
EADC_T::STATUS1: VALID Position
Definition at line 1571 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPF0_Msk (0x1ul << EADC_STATUS2_ADCMPF0_Pos) |
EADC_T::STATUS2: ADCMPF0 Mask
Definition at line 1590 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPF0_Pos (4) |
EADC_T::STATUS2: ADCMPF0 Position
Definition at line 1589 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPF1_Msk (0x1ul << EADC_STATUS2_ADCMPF1_Pos) |
EADC_T::STATUS2: ADCMPF1 Mask
Definition at line 1593 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPF1_Pos (5) |
EADC_T::STATUS2: ADCMPF1 Position
Definition at line 1592 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPF2_Msk (0x1ul << EADC_STATUS2_ADCMPF2_Pos) |
EADC_T::STATUS2: ADCMPF2 Mask
Definition at line 1596 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPF2_Pos (6) |
EADC_T::STATUS2: ADCMPF2 Position
Definition at line 1595 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPF3_Msk (0x1ul << EADC_STATUS2_ADCMPF3_Pos) |
EADC_T::STATUS2: ADCMPF3 Mask
Definition at line 1599 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPF3_Pos (7) |
EADC_T::STATUS2: ADCMPF3 Position
Definition at line 1598 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPO0_Msk (0x1ul << EADC_STATUS2_ADCMPO0_Pos) |
EADC_T::STATUS2: ADCMPO0 Mask
Definition at line 1614 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPO0_Pos (12) |
EADC_T::STATUS2: ADCMPO0 Position
Definition at line 1613 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPO1_Msk (0x1ul << EADC_STATUS2_ADCMPO1_Pos) |
EADC_T::STATUS2: ADCMPO1 Mask
Definition at line 1617 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPO1_Pos (13) |
EADC_T::STATUS2: ADCMPO1 Position
Definition at line 1616 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPO2_Msk (0x1ul << EADC_STATUS2_ADCMPO2_Pos) |
EADC_T::STATUS2: ADCMPO2 Mask
Definition at line 1620 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPO2_Pos (14) |
EADC_T::STATUS2: ADCMPO2 Position
Definition at line 1619 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPO3_Msk (0x1ul << EADC_STATUS2_ADCMPO3_Pos) |
EADC_T::STATUS2: ADCMPO3 Mask
Definition at line 1623 of file eadc_reg.h.
| #define EADC_STATUS2_ADCMPO3_Pos (15) |
EADC_T::STATUS2: ADCMPO3 Position
Definition at line 1622 of file eadc_reg.h.
| #define EADC_STATUS2_ADIF0_Msk (0x1ul << EADC_STATUS2_ADIF0_Pos) |
EADC_T::STATUS2: ADIF0 Mask
Definition at line 1578 of file eadc_reg.h.
| #define EADC_STATUS2_ADIF0_Pos (0) |
EADC_T::STATUS2: ADIF0 Position
Definition at line 1577 of file eadc_reg.h.
| #define EADC_STATUS2_ADIF1_Msk (0x1ul << EADC_STATUS2_ADIF1_Pos) |
EADC_T::STATUS2: ADIF1 Mask
Definition at line 1581 of file eadc_reg.h.
| #define EADC_STATUS2_ADIF1_Pos (1) |
EADC_T::STATUS2: ADIF1 Position
Definition at line 1580 of file eadc_reg.h.
| #define EADC_STATUS2_ADIF2_Msk (0x1ul << EADC_STATUS2_ADIF2_Pos) |
EADC_T::STATUS2: ADIF2 Mask
Definition at line 1584 of file eadc_reg.h.
| #define EADC_STATUS2_ADIF2_Pos (2) |
EADC_T::STATUS2: ADIF2 Position
Definition at line 1583 of file eadc_reg.h.
| #define EADC_STATUS2_ADIF3_Msk (0x1ul << EADC_STATUS2_ADIF3_Pos) |
EADC_T::STATUS2: ADIF3 Mask
Definition at line 1587 of file eadc_reg.h.
| #define EADC_STATUS2_ADIF3_Pos (3) |
EADC_T::STATUS2: ADIF3 Position
Definition at line 1586 of file eadc_reg.h.
| #define EADC_STATUS2_ADOVIF0_Msk (0x1ul << EADC_STATUS2_ADOVIF0_Pos) |
EADC_T::STATUS2: ADOVIF0 Mask
Definition at line 1602 of file eadc_reg.h.
| #define EADC_STATUS2_ADOVIF0_Pos (8) |
EADC_T::STATUS2: ADOVIF0 Position
Definition at line 1601 of file eadc_reg.h.
| #define EADC_STATUS2_ADOVIF1_Msk (0x1ul << EADC_STATUS2_ADOVIF1_Pos) |
EADC_T::STATUS2: ADOVIF1 Mask
Definition at line 1605 of file eadc_reg.h.
| #define EADC_STATUS2_ADOVIF1_Pos (9) |
EADC_T::STATUS2: ADOVIF1 Position
Definition at line 1604 of file eadc_reg.h.
| #define EADC_STATUS2_ADOVIF2_Msk (0x1ul << EADC_STATUS2_ADOVIF2_Pos) |
EADC_T::STATUS2: ADOVIF2 Mask
Definition at line 1608 of file eadc_reg.h.
| #define EADC_STATUS2_ADOVIF2_Pos (10) |
EADC_T::STATUS2: ADOVIF2 Position
Definition at line 1607 of file eadc_reg.h.
| #define EADC_STATUS2_ADOVIF3_Msk (0x1ul << EADC_STATUS2_ADOVIF3_Pos) |
EADC_T::STATUS2: ADOVIF3 Mask
Definition at line 1611 of file eadc_reg.h.
| #define EADC_STATUS2_ADOVIF3_Pos (11) |
EADC_T::STATUS2: ADOVIF3 Position
Definition at line 1610 of file eadc_reg.h.
| #define EADC_STATUS2_ADOVIF_Msk (0x1ul << EADC_STATUS2_ADOVIF_Pos) |
EADC_T::STATUS2: ADOVIF Mask
Definition at line 1632 of file eadc_reg.h.
| #define EADC_STATUS2_ADOVIF_Pos (24) |
EADC_T::STATUS2: ADOVIF Position
Definition at line 1631 of file eadc_reg.h.
| #define EADC_STATUS2_AOV_Msk (0x1ul << EADC_STATUS2_AOV_Pos) |
EADC_T::STATUS2: AOV Mask
Definition at line 1641 of file eadc_reg.h.
| #define EADC_STATUS2_AOV_Pos (27) |
EADC_T::STATUS2: AOV Position
Definition at line 1640 of file eadc_reg.h.
| #define EADC_STATUS2_AVALID_Msk (0x1ul << EADC_STATUS2_AVALID_Pos) |
EADC_T::STATUS2: AVALID Mask
Definition at line 1638 of file eadc_reg.h.
| #define EADC_STATUS2_AVALID_Pos (26) |
EADC_T::STATUS2: AVALID Position
Definition at line 1637 of file eadc_reg.h.
| #define EADC_STATUS2_BUSY_Msk (0x1ul << EADC_STATUS2_BUSY_Pos) |
EADC_T::STATUS2: BUSY Mask
Definition at line 1629 of file eadc_reg.h.
| #define EADC_STATUS2_BUSY_Pos (23) |
EADC_T::STATUS2: BUSY Position
Definition at line 1628 of file eadc_reg.h.
| #define EADC_STATUS2_CHANNEL_Msk (0x1ful << EADC_STATUS2_CHANNEL_Pos) |
EADC_T::STATUS2: CHANNEL Mask
Definition at line 1626 of file eadc_reg.h.
| #define EADC_STATUS2_CHANNEL_Pos (16) |
EADC_T::STATUS2: CHANNEL Position
Definition at line 1625 of file eadc_reg.h.
| #define EADC_STATUS2_STOVF_Msk (0x1ul << EADC_STATUS2_STOVF_Pos) |
EADC_T::STATUS2: STOVF Mask
Definition at line 1635 of file eadc_reg.h.
| #define EADC_STATUS2_STOVF_Pos (25) |
EADC_T::STATUS2: STOVF Position
Definition at line 1634 of file eadc_reg.h.
| #define EADC_STATUS3_CURSPL_Msk (0x1ful << EADC_STATUS3_CURSPL_Pos) |
EADC_T::STATUS3: CURSPL Mask
Definition at line 1644 of file eadc_reg.h.
| #define EADC_STATUS3_CURSPL_Pos (0) |
EADC_T::STATUS3: CURSPL Position
Definition at line 1643 of file eadc_reg.h.
| #define EADC_SWTRG_SWTRG_Msk (0x7fffful << EADC_SWTRG_SWTRG_Pos) |
EADC_T::SWTRG: SWTRG Mask
Definition at line 792 of file eadc_reg.h.
| #define EADC_SWTRG_SWTRG_Pos (0) |
EADC_T::SWTRG: SWTRG Position
Definition at line 791 of file eadc_reg.h.
| #define EBI_CTL0_ADSEPEN_Msk (0x1ul << EBI_CTL0_ADSEPEN_Pos) |
EBI_T::CTL0: ADSEPEN Mask
| #define EBI_CTL0_ADSEPEN_Pos (3) |
EBI_T::CTL0: ADSEPEN Position
| #define EBI_CTL0_CACCESS_Msk (0x1ul << EBI_CTL0_CACCESS_Pos) |
EBI_T::CTL0: CACCESS Mask
| #define EBI_CTL0_CACCESS_Pos (4) |
EBI_T::CTL0: CACCESS Position
| #define EBI_CTL0_CSPOLINV_Msk (0x1ul << EBI_CTL0_CSPOLINV_Pos) |
EBI_T::CTL0: CSPOLINV Mask
| #define EBI_CTL0_CSPOLINV_Pos (2) |
EBI_T::CTL0: CSPOLINV Position
| #define EBI_CTL0_DW16_Msk (0x1ul << EBI_CTL0_DW16_Pos) |
EBI_T::CTL0: DW16 Mask
| #define EBI_CTL0_DW16_Pos (1) |
EBI_T::CTL0: DW16 Position
| #define EBI_CTL0_EN_Msk (0x1ul << EBI_CTL0_EN_Pos) |
EBI_T::CTL0: EN Mask
| #define EBI_CTL0_EN_Pos (0) |
EBI_T::CTL0: EN Position
| #define EBI_CTL0_MCLKDIV_Msk (0x7ul << EBI_CTL0_MCLKDIV_Pos) |
EBI_T::CTL0: MCLKDIV Mask
| #define EBI_CTL0_MCLKDIV_Pos (8) |
EBI_T::CTL0: MCLKDIV Position
| #define EBI_CTL0_TALE_Msk (0x7ul << EBI_CTL0_TALE_Pos) |
EBI_T::CTL0: TALE Mask
| #define EBI_CTL0_TALE_Pos (16) |
EBI_T::CTL0: TALE Position
| #define EBI_CTL0_WBUFEN_Msk (0x1ul << EBI_CTL0_WBUFEN_Pos) |
EBI_T::CTL0: WBUFEN Mask
| #define EBI_CTL0_WBUFEN_Pos (24) |
EBI_T::CTL0: WBUFEN Position
| #define EBI_CTL1_ADSEPEN_Msk (0x1ul << EBI_CTL1_ADSEPEN_Pos) |
EBI_T::CTL1: ADSEPEN Mask
| #define EBI_CTL1_ADSEPEN_Pos (3) |
EBI_T::CTL1: ADSEPEN Position
| #define EBI_CTL1_CACCESS_Msk (0x1ul << EBI_CTL1_CACCESS_Pos) |
EBI_T::CTL1: CACCESS Mask
| #define EBI_CTL1_CACCESS_Pos (4) |
EBI_T::CTL1: CACCESS Position
| #define EBI_CTL1_CSPOLINV_Msk (0x1ul << EBI_CTL1_CSPOLINV_Pos) |
EBI_T::CTL1: CSPOLINV Mask
| #define EBI_CTL1_CSPOLINV_Pos (2) |
EBI_T::CTL1: CSPOLINV Position
| #define EBI_CTL1_DW16_Msk (0x1ul << EBI_CTL1_DW16_Pos) |
EBI_T::CTL1: DW16 Mask
| #define EBI_CTL1_DW16_Pos (1) |
EBI_T::CTL1: DW16 Position
| #define EBI_CTL1_EN_Msk (0x1ul << EBI_CTL1_EN_Pos) |
EBI_T::CTL1: EN Mask
| #define EBI_CTL1_EN_Pos (0) |
EBI_T::CTL1: EN Position
| #define EBI_CTL1_MCLKDIV_Msk (0x7ul << EBI_CTL1_MCLKDIV_Pos) |
EBI_T::CTL1: MCLKDIV Mask
| #define EBI_CTL1_MCLKDIV_Pos (8) |
EBI_T::CTL1: MCLKDIV Position
| #define EBI_CTL1_TALE_Msk (0x7ul << EBI_CTL1_TALE_Pos) |
EBI_T::CTL1: TALE Mask
| #define EBI_CTL1_TALE_Pos (16) |
EBI_T::CTL1: TALE Position
| #define EBI_CTL1_WBUFEN_Msk (0x1ul << EBI_CTL1_WBUFEN_Pos) |
EBI_T::CTL1: WBUFEN Mask
| #define EBI_CTL1_WBUFEN_Pos (24) |
EBI_T::CTL1: WBUFEN Position
| #define EBI_CTL2_ADSEPEN_Msk (0x1ul << EBI_CTL2_ADSEPEN_Pos) |
EBI_T::CTL2: ADSEPEN Mask
| #define EBI_CTL2_ADSEPEN_Pos (3) |
EBI_T::CTL2: ADSEPEN Position
| #define EBI_CTL2_CACCESS_Msk (0x1ul << EBI_CTL2_CACCESS_Pos) |
EBI_T::CTL2: CACCESS Mask
| #define EBI_CTL2_CACCESS_Pos (4) |
EBI_T::CTL2: CACCESS Position
| #define EBI_CTL2_CSPOLINV_Msk (0x1ul << EBI_CTL2_CSPOLINV_Pos) |
EBI_T::CTL2: CSPOLINV Mask
| #define EBI_CTL2_CSPOLINV_Pos (2) |
EBI_T::CTL2: CSPOLINV Position
| #define EBI_CTL2_DW16_Msk (0x1ul << EBI_CTL2_DW16_Pos) |
EBI_T::CTL2: DW16 Mask
| #define EBI_CTL2_DW16_Pos (1) |
EBI_T::CTL2: DW16 Position
| #define EBI_CTL2_EN_Msk (0x1ul << EBI_CTL2_EN_Pos) |
EBI_T::CTL2: EN Mask
| #define EBI_CTL2_EN_Pos (0) |
EBI_T::CTL2: EN Position
| #define EBI_CTL2_MCLKDIV_Msk (0x7ul << EBI_CTL2_MCLKDIV_Pos) |
EBI_T::CTL2: MCLKDIV Mask
| #define EBI_CTL2_MCLKDIV_Pos (8) |
EBI_T::CTL2: MCLKDIV Position
| #define EBI_CTL2_TALE_Msk (0x7ul << EBI_CTL2_TALE_Pos) |
EBI_T::CTL2: TALE Mask
| #define EBI_CTL2_TALE_Pos (16) |
EBI_T::CTL2: TALE Position
| #define EBI_CTL2_WBUFEN_Msk (0x1ul << EBI_CTL2_WBUFEN_Pos) |
EBI_T::CTL2: WBUFEN Mask
| #define EBI_CTL2_WBUFEN_Pos (24) |
EBI_T::CTL2: WBUFEN Position
| #define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) |
| #define EBI_CTL_ADSEPEN_Pos (3) |
| #define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) |
| #define EBI_CTL_CACCESS_Pos (4) |
| #define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) |
| #define EBI_CTL_CSPOLINV_Pos (2) |
| #define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) |
| #define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) |
| #define EBI_CTL_EN_Pos (0) |
| #define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) |
| #define EBI_CTL_MCLKDIV_Pos (8) |
| #define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) |
| #define EBI_CTL_WBUFEN_Msk (0x1ul << EBI_CTL_WBUFEN_Pos) |
| #define EBI_CTL_WBUFEN_Pos (24) |
| #define EBI_TCTL0_R2R_Msk (0xful << EBI_TCTL0_R2R_Pos) |
EBI_T::TCTL0: R2R Mask
| #define EBI_TCTL0_R2R_Pos (24) |
EBI_T::TCTL0: R2R Position
| #define EBI_TCTL0_RAHDOFF_Msk (0x1ul << EBI_TCTL0_RAHDOFF_Pos) |
EBI_T::TCTL0: RAHDOFF Mask
| #define EBI_TCTL0_RAHDOFF_Pos (22) |
EBI_T::TCTL0: RAHDOFF Position
| #define EBI_TCTL0_TACC_Msk (0x1ful << EBI_TCTL0_TACC_Pos) |
EBI_T::TCTL0: TACC Mask
| #define EBI_TCTL0_TACC_Pos (3) |
EBI_T::TCTL0: TACC Position
| #define EBI_TCTL0_TAHD_Msk (0x7ul << EBI_TCTL0_TAHD_Pos) |
EBI_T::TCTL0: TAHD Mask
| #define EBI_TCTL0_TAHD_Pos (8) |
EBI_T::TCTL0: TAHD Position
| #define EBI_TCTL0_W2X_Msk (0xful << EBI_TCTL0_W2X_Pos) |
EBI_T::TCTL0: W2X Mask
| #define EBI_TCTL0_W2X_Pos (12) |
EBI_T::TCTL0: W2X Position
| #define EBI_TCTL0_WAHDOFF_Msk (0x1ul << EBI_TCTL0_WAHDOFF_Pos) |
EBI_T::TCTL0: WAHDOFF Mask
| #define EBI_TCTL0_WAHDOFF_Pos (23) |
EBI_T::TCTL0: WAHDOFF Position
| #define EBI_TCTL1_R2R_Msk (0xful << EBI_TCTL1_R2R_Pos) |
EBI_T::TCTL1: R2R Mask
| #define EBI_TCTL1_R2R_Pos (24) |
EBI_T::TCTL1: R2R Position
| #define EBI_TCTL1_RAHDOFF_Msk (0x1ul << EBI_TCTL1_RAHDOFF_Pos) |
EBI_T::TCTL1: RAHDOFF Mask
| #define EBI_TCTL1_RAHDOFF_Pos (22) |
EBI_T::TCTL1: RAHDOFF Position
| #define EBI_TCTL1_TACC_Msk (0x1ful << EBI_TCTL1_TACC_Pos) |
EBI_T::TCTL1: TACC Mask
| #define EBI_TCTL1_TACC_Pos (3) |
EBI_T::TCTL1: TACC Position
| #define EBI_TCTL1_TAHD_Msk (0x7ul << EBI_TCTL1_TAHD_Pos) |
EBI_T::TCTL1: TAHD Mask
| #define EBI_TCTL1_TAHD_Pos (8) |
EBI_T::TCTL1: TAHD Position
| #define EBI_TCTL1_W2X_Msk (0xful << EBI_TCTL1_W2X_Pos) |
EBI_T::TCTL1: W2X Mask
| #define EBI_TCTL1_W2X_Pos (12) |
EBI_T::TCTL1: W2X Position
| #define EBI_TCTL1_WAHDOFF_Msk (0x1ul << EBI_TCTL1_WAHDOFF_Pos) |
EBI_T::TCTL1: WAHDOFF Mask
| #define EBI_TCTL1_WAHDOFF_Pos (23) |
EBI_T::TCTL1: WAHDOFF Position
| #define EBI_TCTL2_R2R_Msk (0xful << EBI_TCTL2_R2R_Pos) |
EBI_T::TCTL2: R2R Mask
| #define EBI_TCTL2_R2R_Pos (24) |
EBI_T::TCTL2: R2R Position
| #define EBI_TCTL2_RAHDOFF_Msk (0x1ul << EBI_TCTL2_RAHDOFF_Pos) |
EBI_T::TCTL2: RAHDOFF Mask
| #define EBI_TCTL2_RAHDOFF_Pos (22) |
EBI_T::TCTL2: RAHDOFF Position
| #define EBI_TCTL2_TACC_Msk (0x1ful << EBI_TCTL2_TACC_Pos) |
EBI_T::TCTL2: TACC Mask
| #define EBI_TCTL2_TACC_Pos (3) |
EBI_T::TCTL2: TACC Position
| #define EBI_TCTL2_TAHD_Msk (0x7ul << EBI_TCTL2_TAHD_Pos) |
EBI_T::TCTL2: TAHD Mask
| #define EBI_TCTL2_TAHD_Pos (8) |
EBI_T::TCTL2: TAHD Position
| #define EBI_TCTL2_W2X_Msk (0xful << EBI_TCTL2_W2X_Pos) |
EBI_T::TCTL2: W2X Mask
| #define EBI_TCTL2_W2X_Pos (12) |
EBI_T::TCTL2: W2X Position
| #define EBI_TCTL2_WAHDOFF_Msk (0x1ul << EBI_TCTL2_WAHDOFF_Pos) |
EBI_T::TCTL2: WAHDOFF Mask
| #define EBI_TCTL2_WAHDOFF_Pos (23) |
EBI_T::TCTL2: WAHDOFF Position
| #define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) |
| #define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) |
| #define EBI_TCTL_RAHDOFF_Pos (22) |
| #define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) |
| #define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) |
| #define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) |
| #define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) |
| #define EBI_TCTL_WAHDOFF_Pos (23) |
| #define ECAP_CNT_CNT_Msk (0xfffffful << ECAP_CNT_CNT_Pos) |
ECAP_T::CNT: CNT Mask
Definition at line 257 of file ecap_reg.h.
| #define ECAP_CNT_CNT_Pos (0) |
@addtogroup ECAP_CONST ECAP Bit Field Definition Constant Definitions for ECAP Controller
ECAP_T::CNT: CNT Position
Definition at line 256 of file ecap_reg.h.
| #define ECAP_CNTCMP_CNTCMP_Msk (0xfffffful << ECAP_CNTCMP_CNTCMP_Pos) |
ECAP_T::CNTCMP: CNTCMP Mask
Definition at line 269 of file ecap_reg.h.
| #define ECAP_CNTCMP_CNTCMP_Pos (0) |
ECAP_T::CNTCMP: CNTCMP Position
Definition at line 268 of file ecap_reg.h.
| #define ECAP_CTL0_CAPEN_Msk (0x1ul << ECAP_CTL0_CAPEN_Pos) |
ECAP_T::CTL0: CAPEN Mask
Definition at line 320 of file ecap_reg.h.
| #define ECAP_CTL0_CAPEN_Pos (29) |
ECAP_T::CTL0: CAPEN Position
Definition at line 319 of file ecap_reg.h.
| #define ECAP_CTL0_CAPIEN0_Msk (0x1ul << ECAP_CTL0_CAPIEN0_Pos) |
ECAP_T::CTL0: CAPIEN0 Mask
Definition at line 296 of file ecap_reg.h.
| #define ECAP_CTL0_CAPIEN0_Pos (16) |
ECAP_T::CTL0: CAPIEN0 Position
Definition at line 295 of file ecap_reg.h.
| #define ECAP_CTL0_CAPIEN1_Msk (0x1ul << ECAP_CTL0_CAPIEN1_Pos) |
ECAP_T::CTL0: CAPIEN1 Mask
Definition at line 299 of file ecap_reg.h.
| #define ECAP_CTL0_CAPIEN1_Pos (17) |
ECAP_T::CTL0: CAPIEN1 Position
Definition at line 298 of file ecap_reg.h.
| #define ECAP_CTL0_CAPIEN2_Msk (0x1ul << ECAP_CTL0_CAPIEN2_Pos) |
ECAP_T::CTL0: CAPIEN2 Mask
Definition at line 302 of file ecap_reg.h.
| #define ECAP_CTL0_CAPIEN2_Pos (18) |
ECAP_T::CTL0: CAPIEN2 Position
Definition at line 301 of file ecap_reg.h.
| #define ECAP_CTL0_CAPNFDIS_Msk (0x1ul << ECAP_CTL0_CAPNFDIS_Pos) |
ECAP_T::CTL0: CAPNFDIS Mask
Definition at line 275 of file ecap_reg.h.
| #define ECAP_CTL0_CAPNFDIS_Pos (3) |
ECAP_T::CTL0: CAPNFDIS Position
Definition at line 274 of file ecap_reg.h.
| #define ECAP_CTL0_CAPSEL0_Msk (0x3ul << ECAP_CTL0_CAPSEL0_Pos) |
ECAP_T::CTL0: CAPSEL0 Mask
Definition at line 287 of file ecap_reg.h.
| #define ECAP_CTL0_CAPSEL0_Pos (8) |
ECAP_T::CTL0: CAPSEL0 Position
Definition at line 286 of file ecap_reg.h.
| #define ECAP_CTL0_CAPSEL1_Msk (0x3ul << ECAP_CTL0_CAPSEL1_Pos) |
ECAP_T::CTL0: CAPSEL1 Mask
Definition at line 290 of file ecap_reg.h.
| #define ECAP_CTL0_CAPSEL1_Pos (10) |
ECAP_T::CTL0: CAPSEL1 Position
Definition at line 289 of file ecap_reg.h.
| #define ECAP_CTL0_CAPSEL2_Msk (0x3ul << ECAP_CTL0_CAPSEL2_Pos) |
ECAP_T::CTL0: CAPSEL2 Mask
Definition at line 293 of file ecap_reg.h.
| #define ECAP_CTL0_CAPSEL2_Pos (12) |
ECAP_T::CTL0: CAPSEL2 Position
Definition at line 292 of file ecap_reg.h.
| #define ECAP_CTL0_CMPCLREN_Msk (0x1ul << ECAP_CTL0_CMPCLREN_Pos) |
ECAP_T::CTL0: CMPCLREN Mask
Definition at line 314 of file ecap_reg.h.
| #define ECAP_CTL0_CMPCLREN_Pos (25) |
ECAP_T::CTL0: CMPCLREN Position
Definition at line 313 of file ecap_reg.h.
| #define ECAP_CTL0_CMPEN_Msk (0x1ul << ECAP_CTL0_CMPEN_Pos) |
ECAP_T::CTL0: CMPEN Mask
Definition at line 317 of file ecap_reg.h.
| #define ECAP_CTL0_CMPEN_Pos (28) |
ECAP_T::CTL0: CMPEN Position
Definition at line 316 of file ecap_reg.h.
| #define ECAP_CTL0_CMPIEN_Msk (0x1ul << ECAP_CTL0_CMPIEN_Pos) |
ECAP_T::CTL0: CMPIEN Mask
Definition at line 308 of file ecap_reg.h.
| #define ECAP_CTL0_CMPIEN_Pos (21) |
ECAP_T::CTL0: CMPIEN Position
Definition at line 307 of file ecap_reg.h.
| #define ECAP_CTL0_CNTEN_Msk (0x1ul << ECAP_CTL0_CNTEN_Pos) |
ECAP_T::CTL0: CNTEN Mask
Definition at line 311 of file ecap_reg.h.
| #define ECAP_CTL0_CNTEN_Pos (24) |
ECAP_T::CTL0: CNTEN Position
Definition at line 310 of file ecap_reg.h.
| #define ECAP_CTL0_IC0EN_Msk (0x1ul << ECAP_CTL0_IC0EN_Pos) |
ECAP_T::CTL0: IC0EN Mask
Definition at line 278 of file ecap_reg.h.
| #define ECAP_CTL0_IC0EN_Pos (4) |
ECAP_T::CTL0: IC0EN Position
Definition at line 277 of file ecap_reg.h.
| #define ECAP_CTL0_IC1EN_Msk (0x1ul << ECAP_CTL0_IC1EN_Pos) |
ECAP_T::CTL0: IC1EN Mask
Definition at line 281 of file ecap_reg.h.
| #define ECAP_CTL0_IC1EN_Pos (5) |
ECAP_T::CTL0: IC1EN Position
Definition at line 280 of file ecap_reg.h.
| #define ECAP_CTL0_IC2EN_Msk (0x1ul << ECAP_CTL0_IC2EN_Pos) |
ECAP_T::CTL0: IC2EN Mask
Definition at line 284 of file ecap_reg.h.
| #define ECAP_CTL0_IC2EN_Pos (6) |
ECAP_T::CTL0: IC2EN Position
Definition at line 283 of file ecap_reg.h.
| #define ECAP_CTL0_NFCLKSEL_Msk (0x7ul << ECAP_CTL0_NFCLKSEL_Pos) |
ECAP_T::CTL0: NFCLKSEL Mask
Definition at line 272 of file ecap_reg.h.
| #define ECAP_CTL0_NFCLKSEL_Pos (0) |
ECAP_T::CTL0: NFCLKSEL Position
Definition at line 271 of file ecap_reg.h.
| #define ECAP_CTL0_OVIEN_Msk (0x1ul << ECAP_CTL0_OVIEN_Pos) |
ECAP_T::CTL0: OVIEN Mask
Definition at line 305 of file ecap_reg.h.
| #define ECAP_CTL0_OVIEN_Pos (20) |
ECAP_T::CTL0: OVIEN Position
Definition at line 304 of file ecap_reg.h.
| #define ECAP_CTL1_CAP0CLREN_Msk (0x1ul << ECAP_CTL1_CAP0CLREN_Pos) |
ECAP_T::CTL1: CAP0CLREN Mask
Definition at line 350 of file ecap_reg.h.
| #define ECAP_CTL1_CAP0CLREN_Pos (20) |
ECAP_T::CTL1: CAP0CLREN Position
Definition at line 349 of file ecap_reg.h.
| #define ECAP_CTL1_CAP0RLDEN_Msk (0x1ul << ECAP_CTL1_CAP0RLDEN_Pos) |
ECAP_T::CTL1: CAP0RLDEN Mask
Definition at line 332 of file ecap_reg.h.
| #define ECAP_CTL1_CAP0RLDEN_Pos (8) |
ECAP_T::CTL1: CAP0RLDEN Position
Definition at line 331 of file ecap_reg.h.
| #define ECAP_CTL1_CAP1CLREN_Msk (0x1ul << ECAP_CTL1_CAP1CLREN_Pos) |
ECAP_T::CTL1: CAP1CLREN Mask
Definition at line 353 of file ecap_reg.h.
| #define ECAP_CTL1_CAP1CLREN_Pos (21) |
ECAP_T::CTL1: CAP1CLREN Position
Definition at line 352 of file ecap_reg.h.
| #define ECAP_CTL1_CAP1RLDEN_Msk (0x1ul << ECAP_CTL1_CAP1RLDEN_Pos) |
ECAP_T::CTL1: CAP1RLDEN Mask
Definition at line 335 of file ecap_reg.h.
| #define ECAP_CTL1_CAP1RLDEN_Pos (9) |
ECAP_T::CTL1: CAP1RLDEN Position
Definition at line 334 of file ecap_reg.h.
| #define ECAP_CTL1_CAP2CLREN_Msk (0x1ul << ECAP_CTL1_CAP2CLREN_Pos) |
ECAP_T::CTL1: CAP2CLREN Mask
Definition at line 356 of file ecap_reg.h.
| #define ECAP_CTL1_CAP2CLREN_Pos (22) |
ECAP_T::CTL1: CAP2CLREN Position
Definition at line 355 of file ecap_reg.h.
| #define ECAP_CTL1_CAP2RLDEN_Msk (0x1ul << ECAP_CTL1_CAP2RLDEN_Pos) |
ECAP_T::CTL1: CAP2RLDEN Mask
Definition at line 338 of file ecap_reg.h.
| #define ECAP_CTL1_CAP2RLDEN_Pos (10) |
ECAP_T::CTL1: CAP2RLDEN Position
Definition at line 337 of file ecap_reg.h.
| #define ECAP_CTL1_CLKSEL_Msk (0x7ul << ECAP_CTL1_CLKSEL_Pos) |
ECAP_T::CTL1: CLKSEL Mask
Definition at line 344 of file ecap_reg.h.
| #define ECAP_CTL1_CLKSEL_Pos (12) |
ECAP_T::CTL1: CLKSEL Position
Definition at line 343 of file ecap_reg.h.
| #define ECAP_CTL1_CNTSRCSEL_Msk (0x3ul << ECAP_CTL1_CNTSRCSEL_Pos) |
ECAP_T::CTL1: CNTSRCSEL Mask
Definition at line 347 of file ecap_reg.h.
| #define ECAP_CTL1_CNTSRCSEL_Pos (16) |
ECAP_T::CTL1: CNTSRCSEL Position
Definition at line 346 of file ecap_reg.h.
| #define ECAP_CTL1_EDGESEL0_Msk (0x3ul << ECAP_CTL1_EDGESEL0_Pos) |
ECAP_T::CTL1: EDGESEL0 Mask
Definition at line 323 of file ecap_reg.h.
| #define ECAP_CTL1_EDGESEL0_Pos (0) |
ECAP_T::CTL1: EDGESEL0 Position
Definition at line 322 of file ecap_reg.h.
| #define ECAP_CTL1_EDGESEL1_Msk (0x3ul << ECAP_CTL1_EDGESEL1_Pos) |
ECAP_T::CTL1: EDGESEL1 Mask
Definition at line 326 of file ecap_reg.h.
| #define ECAP_CTL1_EDGESEL1_Pos (2) |
ECAP_T::CTL1: EDGESEL1 Position
Definition at line 325 of file ecap_reg.h.
| #define ECAP_CTL1_EDGESEL2_Msk (0x3ul << ECAP_CTL1_EDGESEL2_Pos) |
ECAP_T::CTL1: EDGESEL2 Mask
Definition at line 329 of file ecap_reg.h.
| #define ECAP_CTL1_EDGESEL2_Pos (4) |
ECAP_T::CTL1: EDGESEL2 Position
Definition at line 328 of file ecap_reg.h.
| #define ECAP_CTL1_OVRLDEN_Msk (0x1ul << ECAP_CTL1_OVRLDEN_Pos) |
ECAP_T::CTL1: OVRLDEN Mask
Definition at line 341 of file ecap_reg.h.
| #define ECAP_CTL1_OVRLDEN_Pos (11) |
ECAP_T::CTL1: OVRLDEN Position
Definition at line 340 of file ecap_reg.h.
| #define ECAP_HLD0_HOLD_Msk (0xfffffful << ECAP_HLD0_HOLD_Pos) |
ECAP_T::HLD0: HOLD Mask
Definition at line 260 of file ecap_reg.h.
| #define ECAP_HLD0_HOLD_Pos (0) |
ECAP_T::HLD0: HOLD Position
Definition at line 259 of file ecap_reg.h.
| #define ECAP_HLD1_HOLD_Msk (0xfffffful << ECAP_HLD1_HOLD_Pos) |
ECAP_T::HLD1: HOLD Mask
Definition at line 263 of file ecap_reg.h.
| #define ECAP_HLD1_HOLD_Pos (0) |
ECAP_T::HLD1: HOLD Position
Definition at line 262 of file ecap_reg.h.
| #define ECAP_HLD2_HOLD_Msk (0xfffffful << ECAP_HLD2_HOLD_Pos) |
ECAP_T::HLD2: HOLD Mask
Definition at line 266 of file ecap_reg.h.
| #define ECAP_HLD2_HOLD_Pos (0) |
ECAP_T::HLD2: HOLD Position
Definition at line 265 of file ecap_reg.h.
| #define ECAP_STATUS_CAP0_Msk (0x1ul << ECAP_STATUS_CAP0_Pos) |
ECAP_T::STATUS: CAP0 Mask
Definition at line 374 of file ecap_reg.h.
| #define ECAP_STATUS_CAP0_Pos (8) |
ECAP_T::STATUS: CAP0 Position
Definition at line 373 of file ecap_reg.h.
| #define ECAP_STATUS_CAP1_Msk (0x1ul << ECAP_STATUS_CAP1_Pos) |
ECAP_T::STATUS: CAP1 Mask
Definition at line 377 of file ecap_reg.h.
| #define ECAP_STATUS_CAP1_Pos (9) |
ECAP_T::STATUS: CAP1 Position
Definition at line 376 of file ecap_reg.h.
| #define ECAP_STATUS_CAP2_Msk (0x1ul << ECAP_STATUS_CAP2_Pos) |
ECAP_T::STATUS: CAP2 Mask
Definition at line 380 of file ecap_reg.h.
| #define ECAP_STATUS_CAP2_Pos (10) |
ECAP_T::STATUS: CAP2 Position
Definition at line 379 of file ecap_reg.h.
| #define ECAP_STATUS_CAPCMPF_Msk (0x1ul << ECAP_STATUS_CAPCMPF_Pos) |
ECAP_T::STATUS: CAPCMPF Mask
Definition at line 368 of file ecap_reg.h.
| #define ECAP_STATUS_CAPCMPF_Pos (4) |
ECAP_T::STATUS: CAPCMPF Position
Definition at line 367 of file ecap_reg.h.
| #define ECAP_STATUS_CAPOVF_Msk (0x1ul << ECAP_STATUS_CAPOVF_Pos) |
ECAP_T::STATUS: CAPOVF Mask
Definition at line 371 of file ecap_reg.h.
| #define ECAP_STATUS_CAPOVF_Pos (5) |
ECAP_T::STATUS: CAPOVF Position
Definition at line 370 of file ecap_reg.h.
| #define ECAP_STATUS_CAPTF0_Msk (0x1ul << ECAP_STATUS_CAPTF0_Pos) |
ECAP_T::STATUS: CAPTF0 Mask
Definition at line 359 of file ecap_reg.h.
| #define ECAP_STATUS_CAPTF0_Pos (0) |
ECAP_T::STATUS: CAPTF0 Position
Definition at line 358 of file ecap_reg.h.
| #define ECAP_STATUS_CAPTF1_Msk (0x1ul << ECAP_STATUS_CAPTF1_Pos) |
ECAP_T::STATUS: CAPTF1 Mask
Definition at line 362 of file ecap_reg.h.
| #define ECAP_STATUS_CAPTF1_Pos (1) |
ECAP_T::STATUS: CAPTF1 Position
Definition at line 361 of file ecap_reg.h.
| #define ECAP_STATUS_CAPTF2_Msk (0x1ul << ECAP_STATUS_CAPTF2_Pos) |
ECAP_T::STATUS: CAPTF2 Mask
Definition at line 365 of file ecap_reg.h.
| #define ECAP_STATUS_CAPTF2_Pos (2) |
ECAP_T::STATUS: CAPTF2 Position
Definition at line 364 of file ecap_reg.h.
| #define EPWM_AINTEN_IFAIEN0_Msk (0x1ul << EPWM_AINTEN_IFAIEN0_Pos) |
EPWM_T::AINTEN: IFAIEN0 Mask
Definition at line 3395 of file epwm_reg.h.
| #define EPWM_AINTEN_IFAIEN0_Pos (0) |
EPWM_T::AINTEN: IFAIEN0 Position
Definition at line 3394 of file epwm_reg.h.
| #define EPWM_AINTEN_IFAIEN1_Msk (0x1ul << EPWM_AINTEN_IFAIEN1_Pos) |
EPWM_T::AINTEN: IFAIEN1 Mask
Definition at line 3398 of file epwm_reg.h.
| #define EPWM_AINTEN_IFAIEN1_Pos (1) |
EPWM_T::AINTEN: IFAIEN1 Position
Definition at line 3397 of file epwm_reg.h.
| #define EPWM_AINTEN_IFAIEN2_Msk (0x1ul << EPWM_AINTEN_IFAIEN2_Pos) |
EPWM_T::AINTEN: IFAIEN2 Mask
Definition at line 3401 of file epwm_reg.h.
| #define EPWM_AINTEN_IFAIEN2_Pos (2) |
EPWM_T::AINTEN: IFAIEN2 Position
Definition at line 3400 of file epwm_reg.h.
| #define EPWM_AINTEN_IFAIEN3_Msk (0x1ul << EPWM_AINTEN_IFAIEN3_Pos) |
EPWM_T::AINTEN: IFAIEN3 Mask
Definition at line 3404 of file epwm_reg.h.
| #define EPWM_AINTEN_IFAIEN3_Pos (3) |
EPWM_T::AINTEN: IFAIEN3 Position
Definition at line 3403 of file epwm_reg.h.
| #define EPWM_AINTEN_IFAIEN4_Msk (0x1ul << EPWM_AINTEN_IFAIEN4_Pos) |
EPWM_T::AINTEN: IFAIEN4 Mask
Definition at line 3407 of file epwm_reg.h.
| #define EPWM_AINTEN_IFAIEN4_Pos (4) |
EPWM_T::AINTEN: IFAIEN4 Position
Definition at line 3406 of file epwm_reg.h.
| #define EPWM_AINTEN_IFAIEN5_Msk (0x1ul << EPWM_AINTEN_IFAIEN5_Pos) |
EPWM_T::AINTEN: IFAIEN5 Mask
Definition at line 3410 of file epwm_reg.h.
| #define EPWM_AINTEN_IFAIEN5_Pos (5) |
EPWM_T::AINTEN: IFAIEN5 Position
Definition at line 3409 of file epwm_reg.h.
| #define EPWM_AINTSTS_IFAIF0_Msk (0x1ul << EPWM_AINTSTS_IFAIF0_Pos) |
EPWM_T::AINTSTS: IFAIF0 Mask
Definition at line 3377 of file epwm_reg.h.
| #define EPWM_AINTSTS_IFAIF0_Pos (0) |
EPWM_T::AINTSTS: IFAIF0 Position
Definition at line 3376 of file epwm_reg.h.
| #define EPWM_AINTSTS_IFAIF1_Msk (0x1ul << EPWM_AINTSTS_IFAIF1_Pos) |
EPWM_T::AINTSTS: IFAIF1 Mask
Definition at line 3380 of file epwm_reg.h.
| #define EPWM_AINTSTS_IFAIF1_Pos (1) |
EPWM_T::AINTSTS: IFAIF1 Position
Definition at line 3379 of file epwm_reg.h.
| #define EPWM_AINTSTS_IFAIF2_Msk (0x1ul << EPWM_AINTSTS_IFAIF2_Pos) |
EPWM_T::AINTSTS: IFAIF2 Mask
Definition at line 3383 of file epwm_reg.h.
| #define EPWM_AINTSTS_IFAIF2_Pos (2) |
EPWM_T::AINTSTS: IFAIF2 Position
Definition at line 3382 of file epwm_reg.h.
| #define EPWM_AINTSTS_IFAIF3_Msk (0x1ul << EPWM_AINTSTS_IFAIF3_Pos) |
EPWM_T::AINTSTS: IFAIF3 Mask
Definition at line 3386 of file epwm_reg.h.
| #define EPWM_AINTSTS_IFAIF3_Pos (3) |
EPWM_T::AINTSTS: IFAIF3 Position
Definition at line 3385 of file epwm_reg.h.
| #define EPWM_AINTSTS_IFAIF4_Msk (0x1ul << EPWM_AINTSTS_IFAIF4_Pos) |
EPWM_T::AINTSTS: IFAIF4 Mask
Definition at line 3389 of file epwm_reg.h.
| #define EPWM_AINTSTS_IFAIF4_Pos (4) |
EPWM_T::AINTSTS: IFAIF4 Position
Definition at line 3388 of file epwm_reg.h.
| #define EPWM_AINTSTS_IFAIF5_Msk (0x1ul << EPWM_AINTSTS_IFAIF5_Pos) |
EPWM_T::AINTSTS: IFAIF5 Mask
Definition at line 3392 of file epwm_reg.h.
| #define EPWM_AINTSTS_IFAIF5_Pos (5) |
EPWM_T::AINTSTS: IFAIF5 Position
Definition at line 3391 of file epwm_reg.h.
| #define EPWM_APDMACTL_APDMAEN0_Msk (0x1ul << EPWM_APDMACTL_APDMAEN0_Pos) |
EPWM_T::APDMACTL: APDMAEN0 Mask
Definition at line 3413 of file epwm_reg.h.
| #define EPWM_APDMACTL_APDMAEN0_Pos (0) |
EPWM_T::APDMACTL: APDMAEN0 Position
Definition at line 3412 of file epwm_reg.h.
| #define EPWM_APDMACTL_APDMAEN1_Msk (0x1ul << EPWM_APDMACTL_APDMAEN1_Pos) |
EPWM_T::APDMACTL: APDMAEN1 Mask
Definition at line 3416 of file epwm_reg.h.
| #define EPWM_APDMACTL_APDMAEN1_Pos (1) |
EPWM_T::APDMACTL: APDMAEN1 Position
Definition at line 3415 of file epwm_reg.h.
| #define EPWM_APDMACTL_APDMAEN2_Msk (0x1ul << EPWM_APDMACTL_APDMAEN2_Pos) |
EPWM_T::APDMACTL: APDMAEN2 Mask
Definition at line 3419 of file epwm_reg.h.
| #define EPWM_APDMACTL_APDMAEN2_Pos (2) |
EPWM_T::APDMACTL: APDMAEN2 Position
Definition at line 3418 of file epwm_reg.h.
| #define EPWM_APDMACTL_APDMAEN3_Msk (0x1ul << EPWM_APDMACTL_APDMAEN3_Pos) |
EPWM_T::APDMACTL: APDMAEN3 Mask
Definition at line 3422 of file epwm_reg.h.
| #define EPWM_APDMACTL_APDMAEN3_Pos (3) |
EPWM_T::APDMACTL: APDMAEN3 Position
Definition at line 3421 of file epwm_reg.h.
| #define EPWM_APDMACTL_APDMAEN4_Msk (0x1ul << EPWM_APDMACTL_APDMAEN4_Pos) |
EPWM_T::APDMACTL: APDMAEN4 Mask
Definition at line 3425 of file epwm_reg.h.
| #define EPWM_APDMACTL_APDMAEN4_Pos (4) |
EPWM_T::APDMACTL: APDMAEN4 Position
Definition at line 3424 of file epwm_reg.h.
| #define EPWM_APDMACTL_APDMAEN5_Msk (0x1ul << EPWM_APDMACTL_APDMAEN5_Pos) |
EPWM_T::APDMACTL: APDMAEN5 Mask
Definition at line 3428 of file epwm_reg.h.
| #define EPWM_APDMACTL_APDMAEN5_Pos (5) |
EPWM_T::APDMACTL: APDMAEN5 Position
Definition at line 3427 of file epwm_reg.h.
| #define EPWM_BNF_BK0SRC_Msk (0x1ul << EPWM_BNF_BK0SRC_Pos) |
EPWM_T::BNF: BK0SRC Mask
Definition at line 2666 of file epwm_reg.h.
| #define EPWM_BNF_BK0SRC_Pos (16) |
EPWM_T::BNF: BK0SRC Position
Definition at line 2665 of file epwm_reg.h.
| #define EPWM_BNF_BK1SRC_Msk (0x1ul << EPWM_BNF_BK1SRC_Pos) |
EPWM_T::BNF: BK1SRC Mask
Definition at line 2669 of file epwm_reg.h.
| #define EPWM_BNF_BK1SRC_Pos (24) |
EPWM_T::BNF: BK1SRC Position
Definition at line 2668 of file epwm_reg.h.
| #define EPWM_BNF_BRK0FCNT_Msk (0x7ul << EPWM_BNF_BRK0FCNT_Pos) |
EPWM_T::BNF: BRK0FCNT Mask
Definition at line 2648 of file epwm_reg.h.
| #define EPWM_BNF_BRK0FCNT_Pos (4) |
EPWM_T::BNF: BRK0FCNT Position
Definition at line 2647 of file epwm_reg.h.
| #define EPWM_BNF_BRK0NFEN_Msk (0x1ul << EPWM_BNF_BRK0NFEN_Pos) |
EPWM_T::BNF: BRK0NFEN Mask
Definition at line 2642 of file epwm_reg.h.
| #define EPWM_BNF_BRK0NFEN_Pos (0) |
EPWM_T::BNF: BRK0NFEN Position
Definition at line 2641 of file epwm_reg.h.
| #define EPWM_BNF_BRK0NFSEL_Msk (0x7ul << EPWM_BNF_BRK0NFSEL_Pos) |
EPWM_T::BNF: BRK0NFSEL Mask
Definition at line 2645 of file epwm_reg.h.
| #define EPWM_BNF_BRK0NFSEL_Pos (1) |
EPWM_T::BNF: BRK0NFSEL Position
Definition at line 2644 of file epwm_reg.h.
| #define EPWM_BNF_BRK0PINV_Msk (0x1ul << EPWM_BNF_BRK0PINV_Pos) |
EPWM_T::BNF: BRK0PINV Mask
Definition at line 2651 of file epwm_reg.h.
| #define EPWM_BNF_BRK0PINV_Pos (7) |
EPWM_T::BNF: BRK0PINV Position
Definition at line 2650 of file epwm_reg.h.
| #define EPWM_BNF_BRK1FCNT_Msk (0x7ul << EPWM_BNF_BRK1FCNT_Pos) |
EPWM_T::BNF: BRK1FCNT Mask
Definition at line 2660 of file epwm_reg.h.
| #define EPWM_BNF_BRK1FCNT_Pos (12) |
EPWM_T::BNF: BRK1FCNT Position
Definition at line 2659 of file epwm_reg.h.
| #define EPWM_BNF_BRK1NFEN_Msk (0x1ul << EPWM_BNF_BRK1NFEN_Pos) |
EPWM_T::BNF: BRK1NFEN Mask
Definition at line 2654 of file epwm_reg.h.
| #define EPWM_BNF_BRK1NFEN_Pos (8) |
EPWM_T::BNF: BRK1NFEN Position
Definition at line 2653 of file epwm_reg.h.
| #define EPWM_BNF_BRK1NFSEL_Msk (0x7ul << EPWM_BNF_BRK1NFSEL_Pos) |
EPWM_T::BNF: BRK1NFSEL Mask
Definition at line 2657 of file epwm_reg.h.
| #define EPWM_BNF_BRK1NFSEL_Pos (9) |
EPWM_T::BNF: BRK1NFSEL Position
Definition at line 2656 of file epwm_reg.h.
| #define EPWM_BNF_BRK1PINV_Msk (0x1ul << EPWM_BNF_BRK1PINV_Pos) |
EPWM_T::BNF: BRK1PINV Mask
Definition at line 2663 of file epwm_reg.h.
| #define EPWM_BNF_BRK1PINV_Pos (15) |
EPWM_T::BNF: BRK1PINV Position
Definition at line 2662 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAEVEN_Pos) |
EPWM_T::BRKCTL0_1: BRKAEVEN Mask
Definition at line 2714 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_BRKAEVEN_Pos (16) |
EPWM_T::BRKCTL0_1: BRKAEVEN Position
Definition at line 2713 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_BRKAODD_Msk (0x3ul << EPWM_BRKCTL0_1_BRKAODD_Pos) |
EPWM_T::BRKCTL0_1: BRKAODD Mask
Definition at line 2717 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_BRKAODD_Pos (18) |
EPWM_T::BRKCTL0_1: BRKAODD Position
Definition at line 2716 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0EEN_Pos) |
EPWM_T::BRKCTL0_1: BRKP0EEN Mask
Definition at line 2690 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_BRKP0EEN_Pos (4) |
EPWM_T::BRKCTL0_1: BRKP0EEN Position
Definition at line 2689 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP0LEN_Pos) |
EPWM_T::BRKCTL0_1: BRKP0LEN Mask
Definition at line 2705 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_BRKP0LEN_Pos (12) |
EPWM_T::BRKCTL0_1: BRKP0LEN Position
Definition at line 2704 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1EEN_Pos) |
EPWM_T::BRKCTL0_1: BRKP1EEN Mask
Definition at line 2693 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_BRKP1EEN_Pos (5) |
EPWM_T::BRKCTL0_1: BRKP1EEN Position
Definition at line 2692 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL0_1_BRKP1LEN_Pos) |
EPWM_T::BRKCTL0_1: BRKP1LEN Mask
Definition at line 2708 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_BRKP1LEN_Pos (13) |
EPWM_T::BRKCTL0_1: BRKP1LEN Position
Definition at line 2707 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0EBEN_Pos) |
EPWM_T::BRKCTL0_1: CPO0EBEN Mask
Definition at line 2684 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_CPO0EBEN_Pos (0) |
EPWM_T::BRKCTL0_1: CPO0EBEN Position
Definition at line 2683 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO0LBEN_Pos) |
EPWM_T::BRKCTL0_1: CPO0LBEN Mask
Definition at line 2699 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_CPO0LBEN_Pos (8) |
EPWM_T::BRKCTL0_1: CPO0LBEN Position
Definition at line 2698 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1EBEN_Pos) |
EPWM_T::BRKCTL0_1: CPO1EBEN Mask
Definition at line 2687 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_CPO1EBEN_Pos (1) |
EPWM_T::BRKCTL0_1: CPO1EBEN Position
Definition at line 2686 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL0_1_CPO1LBEN_Pos) |
EPWM_T::BRKCTL0_1: CPO1LBEN Mask
Definition at line 2702 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_CPO1LBEN_Pos (9) |
EPWM_T::BRKCTL0_1: CPO1LBEN Position
Definition at line 2701 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCEBEN_Pos) |
EPWM_T::BRKCTL0_1: EADCEBEN Mask
Definition at line 2720 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_EADCEBEN_Pos (20) |
EPWM_T::BRKCTL0_1: EADCEBEN Position
Definition at line 2719 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_EADCLBEN_Pos) |
EPWM_T::BRKCTL0_1: EADCLBEN Mask
Definition at line 2723 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_EADCLBEN_Pos (28) |
EPWM_T::BRKCTL0_1: EADCLBEN Position
Definition at line 2722 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSEBEN_Pos) |
EPWM_T::BRKCTL0_1: SYSEBEN Mask
Definition at line 2696 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_SYSEBEN_Pos (7) |
EPWM_T::BRKCTL0_1: SYSEBEN Position
Definition at line 2695 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL0_1_SYSLBEN_Pos) |
EPWM_T::BRKCTL0_1: SYSLBEN Mask
Definition at line 2711 of file epwm_reg.h.
| #define EPWM_BRKCTL0_1_SYSLBEN_Pos (15) |
EPWM_T::BRKCTL0_1: SYSLBEN Position
Definition at line 2710 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAEVEN_Pos) |
EPWM_T::BRKCTL2_3: BRKAEVEN Mask
Definition at line 2756 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_BRKAEVEN_Pos (16) |
EPWM_T::BRKCTL2_3: BRKAEVEN Position
Definition at line 2755 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_BRKAODD_Msk (0x3ul << EPWM_BRKCTL2_3_BRKAODD_Pos) |
EPWM_T::BRKCTL2_3: BRKAODD Mask
Definition at line 2759 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_BRKAODD_Pos (18) |
EPWM_T::BRKCTL2_3: BRKAODD Position
Definition at line 2758 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0EEN_Pos) |
EPWM_T::BRKCTL2_3: BRKP0EEN Mask
Definition at line 2732 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_BRKP0EEN_Pos (4) |
EPWM_T::BRKCTL2_3: BRKP0EEN Position
Definition at line 2731 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP0LEN_Pos) |
EPWM_T::BRKCTL2_3: BRKP0LEN Mask
Definition at line 2747 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_BRKP0LEN_Pos (12) |
EPWM_T::BRKCTL2_3: BRKP0LEN Position
Definition at line 2746 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1EEN_Pos) |
EPWM_T::BRKCTL2_3: BRKP1EEN Mask
Definition at line 2735 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_BRKP1EEN_Pos (5) |
EPWM_T::BRKCTL2_3: BRKP1EEN Position
Definition at line 2734 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL2_3_BRKP1LEN_Pos) |
EPWM_T::BRKCTL2_3: BRKP1LEN Mask
Definition at line 2750 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_BRKP1LEN_Pos (13) |
EPWM_T::BRKCTL2_3: BRKP1LEN Position
Definition at line 2749 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0EBEN_Pos) |
EPWM_T::BRKCTL2_3: CPO0EBEN Mask
Definition at line 2726 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_CPO0EBEN_Pos (0) |
EPWM_T::BRKCTL2_3: CPO0EBEN Position
Definition at line 2725 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO0LBEN_Pos) |
EPWM_T::BRKCTL2_3: CPO0LBEN Mask
Definition at line 2741 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_CPO0LBEN_Pos (8) |
EPWM_T::BRKCTL2_3: CPO0LBEN Position
Definition at line 2740 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1EBEN_Pos) |
EPWM_T::BRKCTL2_3: CPO1EBEN Mask
Definition at line 2729 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_CPO1EBEN_Pos (1) |
EPWM_T::BRKCTL2_3: CPO1EBEN Position
Definition at line 2728 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL2_3_CPO1LBEN_Pos) |
EPWM_T::BRKCTL2_3: CPO1LBEN Mask
Definition at line 2744 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_CPO1LBEN_Pos (9) |
EPWM_T::BRKCTL2_3: CPO1LBEN Position
Definition at line 2743 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCEBEN_Pos) |
EPWM_T::BRKCTL2_3: EADCEBEN Mask
Definition at line 2762 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_EADCEBEN_Pos (20) |
EPWM_T::BRKCTL2_3: EADCEBEN Position
Definition at line 2761 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_EADCLBEN_Pos) |
EPWM_T::BRKCTL2_3: EADCLBEN Mask
Definition at line 2765 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_EADCLBEN_Pos (28) |
EPWM_T::BRKCTL2_3: EADCLBEN Position
Definition at line 2764 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSEBEN_Pos) |
EPWM_T::BRKCTL2_3: SYSEBEN Mask
Definition at line 2738 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_SYSEBEN_Pos (7) |
EPWM_T::BRKCTL2_3: SYSEBEN Position
Definition at line 2737 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL2_3_SYSLBEN_Pos) |
EPWM_T::BRKCTL2_3: SYSLBEN Mask
Definition at line 2753 of file epwm_reg.h.
| #define EPWM_BRKCTL2_3_SYSLBEN_Pos (15) |
EPWM_T::BRKCTL2_3: SYSLBEN Position
Definition at line 2752 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_BRKAEVEN_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAEVEN_Pos) |
EPWM_T::BRKCTL4_5: BRKAEVEN Mask
Definition at line 2798 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_BRKAEVEN_Pos (16) |
EPWM_T::BRKCTL4_5: BRKAEVEN Position
Definition at line 2797 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_BRKAODD_Msk (0x3ul << EPWM_BRKCTL4_5_BRKAODD_Pos) |
EPWM_T::BRKCTL4_5: BRKAODD Mask
Definition at line 2801 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_BRKAODD_Pos (18) |
EPWM_T::BRKCTL4_5: BRKAODD Position
Definition at line 2800 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_BRKP0EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0EEN_Pos) |
EPWM_T::BRKCTL4_5: BRKP0EEN Mask
Definition at line 2774 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_BRKP0EEN_Pos (4) |
EPWM_T::BRKCTL4_5: BRKP0EEN Position
Definition at line 2773 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_BRKP0LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP0LEN_Pos) |
EPWM_T::BRKCTL4_5: BRKP0LEN Mask
Definition at line 2789 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_BRKP0LEN_Pos (12) |
EPWM_T::BRKCTL4_5: BRKP0LEN Position
Definition at line 2788 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_BRKP1EEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1EEN_Pos) |
EPWM_T::BRKCTL4_5: BRKP1EEN Mask
Definition at line 2777 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_BRKP1EEN_Pos (5) |
EPWM_T::BRKCTL4_5: BRKP1EEN Position
Definition at line 2776 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_BRKP1LEN_Msk (0x1ul << EPWM_BRKCTL4_5_BRKP1LEN_Pos) |
EPWM_T::BRKCTL4_5: BRKP1LEN Mask
Definition at line 2792 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_BRKP1LEN_Pos (13) |
EPWM_T::BRKCTL4_5: BRKP1LEN Position
Definition at line 2791 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_CPO0EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0EBEN_Pos) |
EPWM_T::BRKCTL4_5: CPO0EBEN Mask
Definition at line 2768 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_CPO0EBEN_Pos (0) |
EPWM_T::BRKCTL4_5: CPO0EBEN Position
Definition at line 2767 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_CPO0LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO0LBEN_Pos) |
EPWM_T::BRKCTL4_5: CPO0LBEN Mask
Definition at line 2783 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_CPO0LBEN_Pos (8) |
EPWM_T::BRKCTL4_5: CPO0LBEN Position
Definition at line 2782 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_CPO1EBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1EBEN_Pos) |
EPWM_T::BRKCTL4_5: CPO1EBEN Mask
Definition at line 2771 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_CPO1EBEN_Pos (1) |
EPWM_T::BRKCTL4_5: CPO1EBEN Position
Definition at line 2770 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_CPO1LBEN_Msk (0x1ul << EPWM_BRKCTL4_5_CPO1LBEN_Pos) |
EPWM_T::BRKCTL4_5: CPO1LBEN Mask
Definition at line 2786 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_CPO1LBEN_Pos (9) |
EPWM_T::BRKCTL4_5: CPO1LBEN Position
Definition at line 2785 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_EADCEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCEBEN_Pos) |
EPWM_T::BRKCTL4_5: EADCEBEN Mask
Definition at line 2804 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_EADCEBEN_Pos (20) |
EPWM_T::BRKCTL4_5: EADCEBEN Position
Definition at line 2803 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_EADCLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_EADCLBEN_Pos) |
EPWM_T::BRKCTL4_5: EADCLBEN Mask
Definition at line 2807 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_EADCLBEN_Pos (28) |
EPWM_T::BRKCTL4_5: EADCLBEN Position
Definition at line 2806 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_SYSEBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSEBEN_Pos) |
EPWM_T::BRKCTL4_5: SYSEBEN Mask
Definition at line 2780 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_SYSEBEN_Pos (7) |
EPWM_T::BRKCTL4_5: SYSEBEN Position
Definition at line 2779 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_SYSLBEN_Msk (0x1ul << EPWM_BRKCTL4_5_SYSLBEN_Pos) |
EPWM_T::BRKCTL4_5: SYSLBEN Mask
Definition at line 2795 of file epwm_reg.h.
| #define EPWM_BRKCTL4_5_SYSLBEN_Pos (15) |
EPWM_T::BRKCTL4_5: SYSLBEN Position
Definition at line 2794 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPEN0_Msk (0x1ul << EPWM_CAPCTL_CAPEN0_Pos) |
EPWM_T::CAPCTL: CAPEN0 Mask
Definition at line 3683 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPEN0_Pos (0) |
EPWM_T::CAPCTL: CAPEN0 Position
Definition at line 3682 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPEN1_Msk (0x1ul << EPWM_CAPCTL_CAPEN1_Pos) |
EPWM_T::CAPCTL: CAPEN1 Mask
Definition at line 3686 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPEN1_Pos (1) |
EPWM_T::CAPCTL: CAPEN1 Position
Definition at line 3685 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPEN2_Msk (0x1ul << EPWM_CAPCTL_CAPEN2_Pos) |
EPWM_T::CAPCTL: CAPEN2 Mask
Definition at line 3689 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPEN2_Pos (2) |
EPWM_T::CAPCTL: CAPEN2 Position
Definition at line 3688 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPEN3_Msk (0x1ul << EPWM_CAPCTL_CAPEN3_Pos) |
EPWM_T::CAPCTL: CAPEN3 Mask
Definition at line 3692 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPEN3_Pos (3) |
EPWM_T::CAPCTL: CAPEN3 Position
Definition at line 3691 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPEN4_Msk (0x1ul << EPWM_CAPCTL_CAPEN4_Pos) |
EPWM_T::CAPCTL: CAPEN4 Mask
Definition at line 3695 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPEN4_Pos (4) |
EPWM_T::CAPCTL: CAPEN4 Position
Definition at line 3694 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPEN5_Msk (0x1ul << EPWM_CAPCTL_CAPEN5_Pos) |
EPWM_T::CAPCTL: CAPEN5 Mask
Definition at line 3698 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPEN5_Pos (5) |
EPWM_T::CAPCTL: CAPEN5 Position
Definition at line 3697 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPINV0_Msk (0x1ul << EPWM_CAPCTL_CAPINV0_Pos) |
EPWM_T::CAPCTL: CAPINV0 Mask
Definition at line 3701 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPINV0_Pos (8) |
EPWM_T::CAPCTL: CAPINV0 Position
Definition at line 3700 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPINV1_Msk (0x1ul << EPWM_CAPCTL_CAPINV1_Pos) |
EPWM_T::CAPCTL: CAPINV1 Mask
Definition at line 3704 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPINV1_Pos (9) |
EPWM_T::CAPCTL: CAPINV1 Position
Definition at line 3703 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPINV2_Msk (0x1ul << EPWM_CAPCTL_CAPINV2_Pos) |
EPWM_T::CAPCTL: CAPINV2 Mask
Definition at line 3707 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPINV2_Pos (10) |
EPWM_T::CAPCTL: CAPINV2 Position
Definition at line 3706 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPINV3_Msk (0x1ul << EPWM_CAPCTL_CAPINV3_Pos) |
EPWM_T::CAPCTL: CAPINV3 Mask
Definition at line 3710 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPINV3_Pos (11) |
EPWM_T::CAPCTL: CAPINV3 Position
Definition at line 3709 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPINV4_Msk (0x1ul << EPWM_CAPCTL_CAPINV4_Pos) |
EPWM_T::CAPCTL: CAPINV4 Mask
Definition at line 3713 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPINV4_Pos (12) |
EPWM_T::CAPCTL: CAPINV4 Position
Definition at line 3712 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPINV5_Msk (0x1ul << EPWM_CAPCTL_CAPINV5_Pos) |
EPWM_T::CAPCTL: CAPINV5 Mask
Definition at line 3716 of file epwm_reg.h.
| #define EPWM_CAPCTL_CAPINV5_Pos (13) |
EPWM_T::CAPCTL: CAPINV5 Position
Definition at line 3715 of file epwm_reg.h.
| #define EPWM_CAPCTL_FCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN0_Pos) |
EPWM_T::CAPCTL: FCRLDEN0 Mask
Definition at line 3737 of file epwm_reg.h.
| #define EPWM_CAPCTL_FCRLDEN0_Pos (24) |
EPWM_T::CAPCTL: FCRLDEN0 Position
Definition at line 3736 of file epwm_reg.h.
| #define EPWM_CAPCTL_FCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN1_Pos) |
EPWM_T::CAPCTL: FCRLDEN1 Mask
Definition at line 3740 of file epwm_reg.h.
| #define EPWM_CAPCTL_FCRLDEN1_Pos (25) |
EPWM_T::CAPCTL: FCRLDEN1 Position
Definition at line 3739 of file epwm_reg.h.
| #define EPWM_CAPCTL_FCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN2_Pos) |
EPWM_T::CAPCTL: FCRLDEN2 Mask
Definition at line 3743 of file epwm_reg.h.
| #define EPWM_CAPCTL_FCRLDEN2_Pos (26) |
EPWM_T::CAPCTL: FCRLDEN2 Position
Definition at line 3742 of file epwm_reg.h.
| #define EPWM_CAPCTL_FCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN3_Pos) |
EPWM_T::CAPCTL: FCRLDEN3 Mask
Definition at line 3746 of file epwm_reg.h.
| #define EPWM_CAPCTL_FCRLDEN3_Pos (27) |
EPWM_T::CAPCTL: FCRLDEN3 Position
Definition at line 3745 of file epwm_reg.h.
| #define EPWM_CAPCTL_FCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN4_Pos) |
EPWM_T::CAPCTL: FCRLDEN4 Mask
Definition at line 3749 of file epwm_reg.h.
| #define EPWM_CAPCTL_FCRLDEN4_Pos (28) |
EPWM_T::CAPCTL: FCRLDEN4 Position
Definition at line 3748 of file epwm_reg.h.
| #define EPWM_CAPCTL_FCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_FCRLDEN5_Pos) |
EPWM_T::CAPCTL: FCRLDEN5 Mask
Definition at line 3752 of file epwm_reg.h.
| #define EPWM_CAPCTL_FCRLDEN5_Pos (29) |
EPWM_T::CAPCTL: FCRLDEN5 Position
Definition at line 3751 of file epwm_reg.h.
| #define EPWM_CAPCTL_RCRLDEN0_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN0_Pos) |
EPWM_T::CAPCTL: RCRLDEN0 Mask
Definition at line 3719 of file epwm_reg.h.
| #define EPWM_CAPCTL_RCRLDEN0_Pos (16) |
EPWM_T::CAPCTL: RCRLDEN0 Position
Definition at line 3718 of file epwm_reg.h.
| #define EPWM_CAPCTL_RCRLDEN1_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN1_Pos) |
EPWM_T::CAPCTL: RCRLDEN1 Mask
Definition at line 3722 of file epwm_reg.h.
| #define EPWM_CAPCTL_RCRLDEN1_Pos (17) |
EPWM_T::CAPCTL: RCRLDEN1 Position
Definition at line 3721 of file epwm_reg.h.
| #define EPWM_CAPCTL_RCRLDEN2_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN2_Pos) |
EPWM_T::CAPCTL: RCRLDEN2 Mask
Definition at line 3725 of file epwm_reg.h.
| #define EPWM_CAPCTL_RCRLDEN2_Pos (18) |
EPWM_T::CAPCTL: RCRLDEN2 Position
Definition at line 3724 of file epwm_reg.h.
| #define EPWM_CAPCTL_RCRLDEN3_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN3_Pos) |
EPWM_T::CAPCTL: RCRLDEN3 Mask
Definition at line 3728 of file epwm_reg.h.
| #define EPWM_CAPCTL_RCRLDEN3_Pos (19) |
EPWM_T::CAPCTL: RCRLDEN3 Position
Definition at line 3727 of file epwm_reg.h.
| #define EPWM_CAPCTL_RCRLDEN4_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN4_Pos) |
EPWM_T::CAPCTL: RCRLDEN4 Mask
Definition at line 3731 of file epwm_reg.h.
| #define EPWM_CAPCTL_RCRLDEN4_Pos (20) |
EPWM_T::CAPCTL: RCRLDEN4 Position
Definition at line 3730 of file epwm_reg.h.
| #define EPWM_CAPCTL_RCRLDEN5_Msk (0x1ul << EPWM_CAPCTL_RCRLDEN5_Pos) |
EPWM_T::CAPCTL: RCRLDEN5 Mask
Definition at line 3734 of file epwm_reg.h.
| #define EPWM_CAPCTL_RCRLDEN5_Pos (21) |
EPWM_T::CAPCTL: RCRLDEN5 Position
Definition at line 3733 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPFIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN0_Pos) |
EPWM_T::CAPIEN: CAPFIEN0 Mask
Definition at line 3890 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPFIEN0_Pos (8) |
EPWM_T::CAPIEN: CAPFIEN0 Position
Definition at line 3889 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPFIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN1_Pos) |
EPWM_T::CAPIEN: CAPFIEN1 Mask
Definition at line 3893 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPFIEN1_Pos (9) |
EPWM_T::CAPIEN: CAPFIEN1 Position
Definition at line 3892 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPFIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN2_Pos) |
EPWM_T::CAPIEN: CAPFIEN2 Mask
Definition at line 3896 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPFIEN2_Pos (10) |
EPWM_T::CAPIEN: CAPFIEN2 Position
Definition at line 3895 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPFIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN3_Pos) |
EPWM_T::CAPIEN: CAPFIEN3 Mask
Definition at line 3899 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPFIEN3_Pos (11) |
EPWM_T::CAPIEN: CAPFIEN3 Position
Definition at line 3898 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPFIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN4_Pos) |
EPWM_T::CAPIEN: CAPFIEN4 Mask
Definition at line 3902 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPFIEN4_Pos (12) |
EPWM_T::CAPIEN: CAPFIEN4 Position
Definition at line 3901 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPFIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPFIEN5_Pos) |
EPWM_T::CAPIEN: CAPFIEN5 Mask
Definition at line 3905 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPFIEN5_Pos (13) |
EPWM_T::CAPIEN: CAPFIEN5 Position
Definition at line 3904 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPRIEN0_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN0_Pos) |
EPWM_T::CAPIEN: CAPRIEN0 Mask
Definition at line 3872 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPRIEN0_Pos (0) |
EPWM_T::CAPIEN: CAPRIEN0 Position
Definition at line 3871 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPRIEN1_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN1_Pos) |
EPWM_T::CAPIEN: CAPRIEN1 Mask
Definition at line 3875 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPRIEN1_Pos (1) |
EPWM_T::CAPIEN: CAPRIEN1 Position
Definition at line 3874 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPRIEN2_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN2_Pos) |
EPWM_T::CAPIEN: CAPRIEN2 Mask
Definition at line 3878 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPRIEN2_Pos (2) |
EPWM_T::CAPIEN: CAPRIEN2 Position
Definition at line 3877 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPRIEN3_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN3_Pos) |
EPWM_T::CAPIEN: CAPRIEN3 Mask
Definition at line 3881 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPRIEN3_Pos (3) |
EPWM_T::CAPIEN: CAPRIEN3 Position
Definition at line 3880 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPRIEN4_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN4_Pos) |
EPWM_T::CAPIEN: CAPRIEN4 Mask
Definition at line 3884 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPRIEN4_Pos (4) |
EPWM_T::CAPIEN: CAPRIEN4 Position
Definition at line 3883 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPRIEN5_Msk (0x1ul << EPWM_CAPIEN_CAPRIEN5_Pos) |
EPWM_T::CAPIEN: CAPRIEN5 Mask
Definition at line 3887 of file epwm_reg.h.
| #define EPWM_CAPIEN_CAPRIEN5_Pos (5) |
EPWM_T::CAPIEN: CAPRIEN5 Position
Definition at line 3886 of file epwm_reg.h.
| #define EPWM_CAPIF_CFLIF0_Msk (0x1ul << EPWM_CAPIF_CFLIF0_Pos) |
EPWM_T::CAPIF: CFLIF0 Mask
Definition at line 3926 of file epwm_reg.h.
| #define EPWM_CAPIF_CFLIF0_Pos (8) |
EPWM_T::CAPIF: CFLIF0 Position
Definition at line 3925 of file epwm_reg.h.
| #define EPWM_CAPIF_CFLIF1_Msk (0x1ul << EPWM_CAPIF_CFLIF1_Pos) |
EPWM_T::CAPIF: CFLIF1 Mask
Definition at line 3929 of file epwm_reg.h.
| #define EPWM_CAPIF_CFLIF1_Pos (9) |
EPWM_T::CAPIF: CFLIF1 Position
Definition at line 3928 of file epwm_reg.h.
| #define EPWM_CAPIF_CFLIF2_Msk (0x1ul << EPWM_CAPIF_CFLIF2_Pos) |
EPWM_T::CAPIF: CFLIF2 Mask
Definition at line 3932 of file epwm_reg.h.
| #define EPWM_CAPIF_CFLIF2_Pos (10) |
EPWM_T::CAPIF: CFLIF2 Position
Definition at line 3931 of file epwm_reg.h.
| #define EPWM_CAPIF_CFLIF3_Msk (0x1ul << EPWM_CAPIF_CFLIF3_Pos) |
EPWM_T::CAPIF: CFLIF3 Mask
Definition at line 3935 of file epwm_reg.h.
| #define EPWM_CAPIF_CFLIF3_Pos (11) |
EPWM_T::CAPIF: CFLIF3 Position
Definition at line 3934 of file epwm_reg.h.
| #define EPWM_CAPIF_CFLIF4_Msk (0x1ul << EPWM_CAPIF_CFLIF4_Pos) |
EPWM_T::CAPIF: CFLIF4 Mask
Definition at line 3938 of file epwm_reg.h.
| #define EPWM_CAPIF_CFLIF4_Pos (12) |
EPWM_T::CAPIF: CFLIF4 Position
Definition at line 3937 of file epwm_reg.h.
| #define EPWM_CAPIF_CFLIF5_Msk (0x1ul << EPWM_CAPIF_CFLIF5_Pos) |
EPWM_T::CAPIF: CFLIF5 Mask
Definition at line 3941 of file epwm_reg.h.
| #define EPWM_CAPIF_CFLIF5_Pos (13) |
EPWM_T::CAPIF: CFLIF5 Position
Definition at line 3940 of file epwm_reg.h.
| #define EPWM_CAPIF_CRLIF0_Msk (0x1ul << EPWM_CAPIF_CRLIF0_Pos) |
EPWM_T::CAPIF: CRLIF0 Mask
Definition at line 3908 of file epwm_reg.h.
| #define EPWM_CAPIF_CRLIF0_Pos (0) |
EPWM_T::CAPIF: CRLIF0 Position
Definition at line 3907 of file epwm_reg.h.
| #define EPWM_CAPIF_CRLIF1_Msk (0x1ul << EPWM_CAPIF_CRLIF1_Pos) |
EPWM_T::CAPIF: CRLIF1 Mask
Definition at line 3911 of file epwm_reg.h.
| #define EPWM_CAPIF_CRLIF1_Pos (1) |
EPWM_T::CAPIF: CRLIF1 Position
Definition at line 3910 of file epwm_reg.h.
| #define EPWM_CAPIF_CRLIF2_Msk (0x1ul << EPWM_CAPIF_CRLIF2_Pos) |
EPWM_T::CAPIF: CRLIF2 Mask
Definition at line 3914 of file epwm_reg.h.
| #define EPWM_CAPIF_CRLIF2_Pos (2) |
EPWM_T::CAPIF: CRLIF2 Position
Definition at line 3913 of file epwm_reg.h.
| #define EPWM_CAPIF_CRLIF3_Msk (0x1ul << EPWM_CAPIF_CRLIF3_Pos) |
EPWM_T::CAPIF: CRLIF3 Mask
Definition at line 3917 of file epwm_reg.h.
| #define EPWM_CAPIF_CRLIF3_Pos (3) |
EPWM_T::CAPIF: CRLIF3 Position
Definition at line 3916 of file epwm_reg.h.
| #define EPWM_CAPIF_CRLIF4_Msk (0x1ul << EPWM_CAPIF_CRLIF4_Pos) |
EPWM_T::CAPIF: CRLIF4 Mask
Definition at line 3920 of file epwm_reg.h.
| #define EPWM_CAPIF_CRLIF4_Pos (4) |
EPWM_T::CAPIF: CRLIF4 Position
Definition at line 3919 of file epwm_reg.h.
| #define EPWM_CAPIF_CRLIF5_Msk (0x1ul << EPWM_CAPIF_CRLIF5_Pos) |
EPWM_T::CAPIF: CRLIF5 Mask
Definition at line 3923 of file epwm_reg.h.
| #define EPWM_CAPIF_CRLIF5_Pos (5) |
EPWM_T::CAPIF: CRLIF5 Position
Definition at line 3922 of file epwm_reg.h.
| #define EPWM_CAPINEN_CAPINEN0_Msk (0x1ul << EPWM_CAPINEN_CAPINEN0_Pos) |
EPWM_T::CAPINEN: CAPINEN0 Mask
Definition at line 3665 of file epwm_reg.h.
| #define EPWM_CAPINEN_CAPINEN0_Pos (0) |
EPWM_T::CAPINEN: CAPINEN0 Position
Definition at line 3664 of file epwm_reg.h.
| #define EPWM_CAPINEN_CAPINEN1_Msk (0x1ul << EPWM_CAPINEN_CAPINEN1_Pos) |
EPWM_T::CAPINEN: CAPINEN1 Mask
Definition at line 3668 of file epwm_reg.h.
| #define EPWM_CAPINEN_CAPINEN1_Pos (1) |
EPWM_T::CAPINEN: CAPINEN1 Position
Definition at line 3667 of file epwm_reg.h.
| #define EPWM_CAPINEN_CAPINEN2_Msk (0x1ul << EPWM_CAPINEN_CAPINEN2_Pos) |
EPWM_T::CAPINEN: CAPINEN2 Mask
Definition at line 3671 of file epwm_reg.h.
| #define EPWM_CAPINEN_CAPINEN2_Pos (2) |
EPWM_T::CAPINEN: CAPINEN2 Position
Definition at line 3670 of file epwm_reg.h.
| #define EPWM_CAPINEN_CAPINEN3_Msk (0x1ul << EPWM_CAPINEN_CAPINEN3_Pos) |
EPWM_T::CAPINEN: CAPINEN3 Mask
Definition at line 3674 of file epwm_reg.h.
| #define EPWM_CAPINEN_CAPINEN3_Pos (3) |
EPWM_T::CAPINEN: CAPINEN3 Position
Definition at line 3673 of file epwm_reg.h.
| #define EPWM_CAPINEN_CAPINEN4_Msk (0x1ul << EPWM_CAPINEN_CAPINEN4_Pos) |
EPWM_T::CAPINEN: CAPINEN4 Mask
Definition at line 3677 of file epwm_reg.h.
| #define EPWM_CAPINEN_CAPINEN4_Pos (4) |
EPWM_T::CAPINEN: CAPINEN4 Position
Definition at line 3676 of file epwm_reg.h.
| #define EPWM_CAPINEN_CAPINEN5_Msk (0x1ul << EPWM_CAPINEN_CAPINEN5_Pos) |
EPWM_T::CAPINEN: CAPINEN5 Mask
Definition at line 3680 of file epwm_reg.h.
| #define EPWM_CAPINEN_CAPINEN5_Pos (5) |
EPWM_T::CAPINEN: CAPINEN5 Position
Definition at line 3679 of file epwm_reg.h.
| #define EPWM_CAPSTS_CFLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV0_Pos) |
EPWM_T::CAPSTS: CFLIFOV0 Mask
Definition at line 3773 of file epwm_reg.h.
| #define EPWM_CAPSTS_CFLIFOV0_Pos (8) |
EPWM_T::CAPSTS: CFLIFOV0 Position
Definition at line 3772 of file epwm_reg.h.
| #define EPWM_CAPSTS_CFLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV1_Pos) |
EPWM_T::CAPSTS: CFLIFOV1 Mask
Definition at line 3776 of file epwm_reg.h.
| #define EPWM_CAPSTS_CFLIFOV1_Pos (9) |
EPWM_T::CAPSTS: CFLIFOV1 Position
Definition at line 3775 of file epwm_reg.h.
| #define EPWM_CAPSTS_CFLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV2_Pos) |
EPWM_T::CAPSTS: CFLIFOV2 Mask
Definition at line 3779 of file epwm_reg.h.
| #define EPWM_CAPSTS_CFLIFOV2_Pos (10) |
EPWM_T::CAPSTS: CFLIFOV2 Position
Definition at line 3778 of file epwm_reg.h.
| #define EPWM_CAPSTS_CFLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV3_Pos) |
EPWM_T::CAPSTS: CFLIFOV3 Mask
Definition at line 3782 of file epwm_reg.h.
| #define EPWM_CAPSTS_CFLIFOV3_Pos (11) |
EPWM_T::CAPSTS: CFLIFOV3 Position
Definition at line 3781 of file epwm_reg.h.
| #define EPWM_CAPSTS_CFLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV4_Pos) |
EPWM_T::CAPSTS: CFLIFOV4 Mask
Definition at line 3785 of file epwm_reg.h.
| #define EPWM_CAPSTS_CFLIFOV4_Pos (12) |
EPWM_T::CAPSTS: CFLIFOV4 Position
Definition at line 3784 of file epwm_reg.h.
| #define EPWM_CAPSTS_CFLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CFLIFOV5_Pos) |
EPWM_T::CAPSTS: CFLIFOV5 Mask
Definition at line 3788 of file epwm_reg.h.
| #define EPWM_CAPSTS_CFLIFOV5_Pos (13) |
EPWM_T::CAPSTS: CFLIFOV5 Position
Definition at line 3787 of file epwm_reg.h.
| #define EPWM_CAPSTS_CRLIFOV0_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV0_Pos) |
EPWM_T::CAPSTS: CRLIFOV0 Mask
Definition at line 3755 of file epwm_reg.h.
| #define EPWM_CAPSTS_CRLIFOV0_Pos (0) |
EPWM_T::CAPSTS: CRLIFOV0 Position
Definition at line 3754 of file epwm_reg.h.
| #define EPWM_CAPSTS_CRLIFOV1_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV1_Pos) |
EPWM_T::CAPSTS: CRLIFOV1 Mask
Definition at line 3758 of file epwm_reg.h.
| #define EPWM_CAPSTS_CRLIFOV1_Pos (1) |
EPWM_T::CAPSTS: CRLIFOV1 Position
Definition at line 3757 of file epwm_reg.h.
| #define EPWM_CAPSTS_CRLIFOV2_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV2_Pos) |
EPWM_T::CAPSTS: CRLIFOV2 Mask
Definition at line 3761 of file epwm_reg.h.
| #define EPWM_CAPSTS_CRLIFOV2_Pos (2) |
EPWM_T::CAPSTS: CRLIFOV2 Position
Definition at line 3760 of file epwm_reg.h.
| #define EPWM_CAPSTS_CRLIFOV3_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV3_Pos) |
EPWM_T::CAPSTS: CRLIFOV3 Mask
Definition at line 3764 of file epwm_reg.h.
| #define EPWM_CAPSTS_CRLIFOV3_Pos (3) |
EPWM_T::CAPSTS: CRLIFOV3 Position
Definition at line 3763 of file epwm_reg.h.
| #define EPWM_CAPSTS_CRLIFOV4_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV4_Pos) |
EPWM_T::CAPSTS: CRLIFOV4 Mask
Definition at line 3767 of file epwm_reg.h.
| #define EPWM_CAPSTS_CRLIFOV4_Pos (4) |
EPWM_T::CAPSTS: CRLIFOV4 Position
Definition at line 3766 of file epwm_reg.h.
| #define EPWM_CAPSTS_CRLIFOV5_Msk (0x1ul << EPWM_CAPSTS_CRLIFOV5_Pos) |
EPWM_T::CAPSTS: CRLIFOV5 Mask
Definition at line 3770 of file epwm_reg.h.
| #define EPWM_CAPSTS_CRLIFOV5_Pos (5) |
EPWM_T::CAPSTS: CRLIFOV5 Position
Definition at line 3769 of file epwm_reg.h.
| #define EPWM_CLKPSC0_1_CLKPSC_Msk (0xffful << EPWM_CLKPSC0_1_CLKPSC_Pos) |
EPWM_T::CLKPSC0_1: CLKPSC Mask
Definition at line 2363 of file epwm_reg.h.
| #define EPWM_CLKPSC0_1_CLKPSC_Pos (0) |
EPWM_T::CLKPSC0_1: CLKPSC Position
Definition at line 2362 of file epwm_reg.h.
| #define EPWM_CLKPSC2_3_CLKPSC_Msk (0xffful << EPWM_CLKPSC2_3_CLKPSC_Pos) |
EPWM_T::CLKPSC2_3: CLKPSC Mask
Definition at line 2366 of file epwm_reg.h.
| #define EPWM_CLKPSC2_3_CLKPSC_Pos (0) |
EPWM_T::CLKPSC2_3: CLKPSC Position
Definition at line 2365 of file epwm_reg.h.
| #define EPWM_CLKPSC4_5_CLKPSC_Msk (0xffful << EPWM_CLKPSC4_5_CLKPSC_Pos) |
EPWM_T::CLKPSC4_5: CLKPSC Mask
Definition at line 2369 of file epwm_reg.h.
| #define EPWM_CLKPSC4_5_CLKPSC_Pos (0) |
EPWM_T::CLKPSC4_5: CLKPSC Position
Definition at line 2368 of file epwm_reg.h.
| #define EPWM_CLKSRC_ECLKSRC0_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC0_Pos) |
EPWM_T::CLKSRC: ECLKSRC0 Mask
Definition at line 2354 of file epwm_reg.h.
| #define EPWM_CLKSRC_ECLKSRC0_Pos (0) |
EPWM_T::CLKSRC: ECLKSRC0 Position
Definition at line 2353 of file epwm_reg.h.
| #define EPWM_CLKSRC_ECLKSRC2_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC2_Pos) |
EPWM_T::CLKSRC: ECLKSRC2 Mask
Definition at line 2357 of file epwm_reg.h.
| #define EPWM_CLKSRC_ECLKSRC2_Pos (8) |
EPWM_T::CLKSRC: ECLKSRC2 Position
Definition at line 2356 of file epwm_reg.h.
| #define EPWM_CLKSRC_ECLKSRC4_Msk (0x7ul << EPWM_CLKSRC_ECLKSRC4_Pos) |
EPWM_T::CLKSRC: ECLKSRC4 Mask
Definition at line 2360 of file epwm_reg.h.
| #define EPWM_CLKSRC_ECLKSRC4_Pos (16) |
EPWM_T::CLKSRC: ECLKSRC4 Position
Definition at line 2359 of file epwm_reg.h.
| #define EPWM_CMPBUF0_CMPBUF_Msk (0xfffful << EPWM_CMPBUF0_CMPBUF_Pos) |
EPWM_T::CMPBUF0: CMPBUF Mask
Definition at line 3962 of file epwm_reg.h.
| #define EPWM_CMPBUF0_CMPBUF_Pos (0) |
EPWM_T::CMPBUF0: CMPBUF Position
Definition at line 3961 of file epwm_reg.h.
| #define EPWM_CMPBUF1_CMPBUF_Msk (0xfffful << EPWM_CMPBUF1_CMPBUF_Pos) |
EPWM_T::CMPBUF1: CMPBUF Mask
Definition at line 3965 of file epwm_reg.h.
| #define EPWM_CMPBUF1_CMPBUF_Pos (0) |
EPWM_T::CMPBUF1: CMPBUF Position
Definition at line 3964 of file epwm_reg.h.
| #define EPWM_CMPBUF2_CMPBUF_Msk (0xfffful << EPWM_CMPBUF2_CMPBUF_Pos) |
EPWM_T::CMPBUF2: CMPBUF Mask
Definition at line 3968 of file epwm_reg.h.
| #define EPWM_CMPBUF2_CMPBUF_Pos (0) |
EPWM_T::CMPBUF2: CMPBUF Position
Definition at line 3967 of file epwm_reg.h.
| #define EPWM_CMPBUF3_CMPBUF_Msk (0xfffful << EPWM_CMPBUF3_CMPBUF_Pos) |
EPWM_T::CMPBUF3: CMPBUF Mask
Definition at line 3971 of file epwm_reg.h.
| #define EPWM_CMPBUF3_CMPBUF_Pos (0) |
EPWM_T::CMPBUF3: CMPBUF Position
Definition at line 3970 of file epwm_reg.h.
| #define EPWM_CMPBUF4_CMPBUF_Msk (0xfffful << EPWM_CMPBUF4_CMPBUF_Pos) |
EPWM_T::CMPBUF4: CMPBUF Mask
Definition at line 3974 of file epwm_reg.h.
| #define EPWM_CMPBUF4_CMPBUF_Pos (0) |
EPWM_T::CMPBUF4: CMPBUF Position
Definition at line 3973 of file epwm_reg.h.
| #define EPWM_CMPBUF5_CMPBUF_Msk (0xfffful << EPWM_CMPBUF5_CMPBUF_Pos) |
EPWM_T::CMPBUF5: CMPBUF Mask
Definition at line 3977 of file epwm_reg.h.
| #define EPWM_CMPBUF5_CMPBUF_Pos (0) |
EPWM_T::CMPBUF5: CMPBUF Position
Definition at line 3976 of file epwm_reg.h.
| #define EPWM_CMPDAT0_CMP_Msk (0xfffful << EPWM_CMPDAT0_CMP_Pos) |
EPWM_T::CMPDAT0: CMP Mask
Definition at line 2444 of file epwm_reg.h.
| #define EPWM_CMPDAT0_CMP_Pos (0) |
EPWM_T::CMPDAT0: CMP Position
Definition at line 2443 of file epwm_reg.h.
| #define EPWM_CMPDAT1_CMP_Msk (0xfffful << EPWM_CMPDAT1_CMP_Pos) |
EPWM_T::CMPDAT1: CMP Mask
Definition at line 2447 of file epwm_reg.h.
| #define EPWM_CMPDAT1_CMP_Pos (0) |
EPWM_T::CMPDAT1: CMP Position
Definition at line 2446 of file epwm_reg.h.
| #define EPWM_CMPDAT2_CMP_Msk (0xfffful << EPWM_CMPDAT2_CMP_Pos) |
EPWM_T::CMPDAT2: CMP Mask
Definition at line 2450 of file epwm_reg.h.
| #define EPWM_CMPDAT2_CMP_Pos (0) |
EPWM_T::CMPDAT2: CMP Position
Definition at line 2449 of file epwm_reg.h.
| #define EPWM_CMPDAT3_CMP_Msk (0xfffful << EPWM_CMPDAT3_CMP_Pos) |
EPWM_T::CMPDAT3: CMP Mask
Definition at line 2453 of file epwm_reg.h.
| #define EPWM_CMPDAT3_CMP_Pos (0) |
EPWM_T::CMPDAT3: CMP Position
Definition at line 2452 of file epwm_reg.h.
| #define EPWM_CMPDAT4_CMP_Msk (0xfffful << EPWM_CMPDAT4_CMP_Pos) |
EPWM_T::CMPDAT4: CMP Mask
Definition at line 2456 of file epwm_reg.h.
| #define EPWM_CMPDAT4_CMP_Pos (0) |
EPWM_T::CMPDAT4: CMP Position
Definition at line 2455 of file epwm_reg.h.
| #define EPWM_CMPDAT5_CMP_Msk (0xfffful << EPWM_CMPDAT5_CMP_Pos) |
EPWM_T::CMPDAT5: CMP Mask
Definition at line 2459 of file epwm_reg.h.
| #define EPWM_CMPDAT5_CMP_Pos (0) |
EPWM_T::CMPDAT5: CMP Position
Definition at line 2458 of file epwm_reg.h.
| #define EPWM_CNT0_CNT_Msk (0xfffful << EPWM_CNT0_CNT_Pos) |
EPWM_T::CNT0: CNT Mask
Definition at line 2498 of file epwm_reg.h.
| #define EPWM_CNT0_CNT_Pos (0) |
EPWM_T::CNT0: CNT Position
Definition at line 2497 of file epwm_reg.h.
| #define EPWM_CNT0_DIRF_Msk (0x1ul << EPWM_CNT0_DIRF_Pos) |
EPWM_T::CNT0: DIRF Mask
Definition at line 2501 of file epwm_reg.h.
| #define EPWM_CNT0_DIRF_Pos (16) |
EPWM_T::CNT0: DIRF Position
Definition at line 2500 of file epwm_reg.h.
| #define EPWM_CNT1_CNT_Msk (0xfffful << EPWM_CNT1_CNT_Pos) |
EPWM_T::CNT1: CNT Mask
Definition at line 2504 of file epwm_reg.h.
| #define EPWM_CNT1_CNT_Pos (0) |
EPWM_T::CNT1: CNT Position
Definition at line 2503 of file epwm_reg.h.
| #define EPWM_CNT1_DIRF_Msk (0x1ul << EPWM_CNT1_DIRF_Pos) |
EPWM_T::CNT1: DIRF Mask
Definition at line 2507 of file epwm_reg.h.
| #define EPWM_CNT1_DIRF_Pos (16) |
EPWM_T::CNT1: DIRF Position
Definition at line 2506 of file epwm_reg.h.
| #define EPWM_CNT2_CNT_Msk (0xfffful << EPWM_CNT2_CNT_Pos) |
EPWM_T::CNT2: CNT Mask
Definition at line 2510 of file epwm_reg.h.
| #define EPWM_CNT2_CNT_Pos (0) |
EPWM_T::CNT2: CNT Position
Definition at line 2509 of file epwm_reg.h.
| #define EPWM_CNT2_DIRF_Msk (0x1ul << EPWM_CNT2_DIRF_Pos) |
EPWM_T::CNT2: DIRF Mask
Definition at line 2513 of file epwm_reg.h.
| #define EPWM_CNT2_DIRF_Pos (16) |
EPWM_T::CNT2: DIRF Position
Definition at line 2512 of file epwm_reg.h.
| #define EPWM_CNT3_CNT_Msk (0xfffful << EPWM_CNT3_CNT_Pos) |
EPWM_T::CNT3: CNT Mask
Definition at line 2516 of file epwm_reg.h.
| #define EPWM_CNT3_CNT_Pos (0) |
EPWM_T::CNT3: CNT Position
Definition at line 2515 of file epwm_reg.h.
| #define EPWM_CNT3_DIRF_Msk (0x1ul << EPWM_CNT3_DIRF_Pos) |
EPWM_T::CNT3: DIRF Mask
Definition at line 2519 of file epwm_reg.h.
| #define EPWM_CNT3_DIRF_Pos (16) |
EPWM_T::CNT3: DIRF Position
Definition at line 2518 of file epwm_reg.h.
| #define EPWM_CNT4_CNT_Msk (0xfffful << EPWM_CNT4_CNT_Pos) |
EPWM_T::CNT4: CNT Mask
Definition at line 2522 of file epwm_reg.h.
| #define EPWM_CNT4_CNT_Pos (0) |
EPWM_T::CNT4: CNT Position
Definition at line 2521 of file epwm_reg.h.
| #define EPWM_CNT4_DIRF_Msk (0x1ul << EPWM_CNT4_DIRF_Pos) |
EPWM_T::CNT4: DIRF Mask
Definition at line 2525 of file epwm_reg.h.
| #define EPWM_CNT4_DIRF_Pos (16) |
EPWM_T::CNT4: DIRF Position
Definition at line 2524 of file epwm_reg.h.
| #define EPWM_CNT5_CNT_Msk (0xfffful << EPWM_CNT5_CNT_Pos) |
EPWM_T::CNT5: CNT Mask
Definition at line 2528 of file epwm_reg.h.
| #define EPWM_CNT5_CNT_Pos (0) |
EPWM_T::CNT5: CNT Position
Definition at line 2527 of file epwm_reg.h.
| #define EPWM_CNT5_DIRF_Msk (0x1ul << EPWM_CNT5_DIRF_Pos) |
EPWM_T::CNT5: DIRF Mask
Definition at line 2531 of file epwm_reg.h.
| #define EPWM_CNT5_DIRF_Pos (16) |
EPWM_T::CNT5: DIRF Position
Definition at line 2530 of file epwm_reg.h.
| #define EPWM_CNTCLR_CNTCLR0_Msk (0x1ul << EPWM_CNTCLR_CNTCLR0_Pos) |
EPWM_T::CNTCLR: CNTCLR0 Mask
Definition at line 2390 of file epwm_reg.h.
| #define EPWM_CNTCLR_CNTCLR0_Pos (0) |
EPWM_T::CNTCLR: CNTCLR0 Position
Definition at line 2389 of file epwm_reg.h.
| #define EPWM_CNTCLR_CNTCLR1_Msk (0x1ul << EPWM_CNTCLR_CNTCLR1_Pos) |
EPWM_T::CNTCLR: CNTCLR1 Mask
Definition at line 2393 of file epwm_reg.h.
| #define EPWM_CNTCLR_CNTCLR1_Pos (1) |
EPWM_T::CNTCLR: CNTCLR1 Position
Definition at line 2392 of file epwm_reg.h.
| #define EPWM_CNTCLR_CNTCLR2_Msk (0x1ul << EPWM_CNTCLR_CNTCLR2_Pos) |
EPWM_T::CNTCLR: CNTCLR2 Mask
Definition at line 2396 of file epwm_reg.h.
| #define EPWM_CNTCLR_CNTCLR2_Pos (2) |
EPWM_T::CNTCLR: CNTCLR2 Position
Definition at line 2395 of file epwm_reg.h.
| #define EPWM_CNTCLR_CNTCLR3_Msk (0x1ul << EPWM_CNTCLR_CNTCLR3_Pos) |
EPWM_T::CNTCLR: CNTCLR3 Mask
Definition at line 2399 of file epwm_reg.h.
| #define EPWM_CNTCLR_CNTCLR3_Pos (3) |
EPWM_T::CNTCLR: CNTCLR3 Position
Definition at line 2398 of file epwm_reg.h.
| #define EPWM_CNTCLR_CNTCLR4_Msk (0x1ul << EPWM_CNTCLR_CNTCLR4_Pos) |
EPWM_T::CNTCLR: CNTCLR4 Mask
Definition at line 2402 of file epwm_reg.h.
| #define EPWM_CNTCLR_CNTCLR4_Pos (4) |
EPWM_T::CNTCLR: CNTCLR4 Position
Definition at line 2401 of file epwm_reg.h.
| #define EPWM_CNTCLR_CNTCLR5_Msk (0x1ul << EPWM_CNTCLR_CNTCLR5_Pos) |
EPWM_T::CNTCLR: CNTCLR5 Mask
Definition at line 2405 of file epwm_reg.h.
| #define EPWM_CNTCLR_CNTCLR5_Pos (5) |
EPWM_T::CNTCLR: CNTCLR5 Position
Definition at line 2404 of file epwm_reg.h.
| #define EPWM_CNTEN_CNTEN0_Msk (0x1ul << EPWM_CNTEN_CNTEN0_Pos) |
EPWM_T::CNTEN: CNTEN0 Mask
Definition at line 2372 of file epwm_reg.h.
| #define EPWM_CNTEN_CNTEN0_Pos (0) |
EPWM_T::CNTEN: CNTEN0 Position
Definition at line 2371 of file epwm_reg.h.
| #define EPWM_CNTEN_CNTEN1_Msk (0x1ul << EPWM_CNTEN_CNTEN1_Pos) |
EPWM_T::CNTEN: CNTEN1 Mask
Definition at line 2375 of file epwm_reg.h.
| #define EPWM_CNTEN_CNTEN1_Pos (1) |
EPWM_T::CNTEN: CNTEN1 Position
Definition at line 2374 of file epwm_reg.h.
| #define EPWM_CNTEN_CNTEN2_Msk (0x1ul << EPWM_CNTEN_CNTEN2_Pos) |
EPWM_T::CNTEN: CNTEN2 Mask
Definition at line 2378 of file epwm_reg.h.
| #define EPWM_CNTEN_CNTEN2_Pos (2) |
EPWM_T::CNTEN: CNTEN2 Position
Definition at line 2377 of file epwm_reg.h.
| #define EPWM_CNTEN_CNTEN3_Msk (0x1ul << EPWM_CNTEN_CNTEN3_Pos) |
EPWM_T::CNTEN: CNTEN3 Mask
Definition at line 2381 of file epwm_reg.h.
| #define EPWM_CNTEN_CNTEN3_Pos (3) |
EPWM_T::CNTEN: CNTEN3 Position
Definition at line 2380 of file epwm_reg.h.
| #define EPWM_CNTEN_CNTEN4_Msk (0x1ul << EPWM_CNTEN_CNTEN4_Pos) |
EPWM_T::CNTEN: CNTEN4 Mask
Definition at line 2384 of file epwm_reg.h.
| #define EPWM_CNTEN_CNTEN4_Pos (4) |
EPWM_T::CNTEN: CNTEN4 Position
Definition at line 2383 of file epwm_reg.h.
| #define EPWM_CNTEN_CNTEN5_Msk (0x1ul << EPWM_CNTEN_CNTEN5_Pos) |
EPWM_T::CNTEN: CNTEN5 Mask
Definition at line 2387 of file epwm_reg.h.
| #define EPWM_CNTEN_CNTEN5_Pos (5) |
EPWM_T::CNTEN: CNTEN5 Position
Definition at line 2386 of file epwm_reg.h.
| #define EPWM_CPSCBUF0_1_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF0_1_CPSCBUF_Pos) |
EPWM_T::CPSCBUF0_1: CPSCBUF Mask
Definition at line 3980 of file epwm_reg.h.
| #define EPWM_CPSCBUF0_1_CPSCBUF_Pos (0) |
EPWM_T::CPSCBUF0_1: CPSCBUF Position
Definition at line 3979 of file epwm_reg.h.
| #define EPWM_CPSCBUF2_3_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF2_3_CPSCBUF_Pos) |
EPWM_T::CPSCBUF2_3: CPSCBUF Mask
Definition at line 3983 of file epwm_reg.h.
| #define EPWM_CPSCBUF2_3_CPSCBUF_Pos (0) |
EPWM_T::CPSCBUF2_3: CPSCBUF Position
Definition at line 3982 of file epwm_reg.h.
| #define EPWM_CPSCBUF4_5_CPSCBUF_Msk (0xffful << EPWM_CPSCBUF4_5_CPSCBUF_Pos) |
EPWM_T::CPSCBUF4_5: CPSCBUF Mask
Definition at line 3986 of file epwm_reg.h.
| #define EPWM_CPSCBUF4_5_CPSCBUF_Pos (0) |
EPWM_T::CPSCBUF4_5: CPSCBUF Position
Definition at line 3985 of file epwm_reg.h.
| #define EPWM_CTL0_CTRLD0_Msk (0x1ul << EPWM_CTL0_CTRLD0_Pos) |
EPWM_T::CTL0: CTRLD0 Mask
Definition at line 2198 of file epwm_reg.h.
| #define EPWM_CTL0_CTRLD0_Pos (0) |
@addtogroup EPWM_CONST EPWM Bit Field Definition Constant Definitions for EPWM Controller
EPWM_T::CTL0: CTRLD0 Position
Definition at line 2197 of file epwm_reg.h.
| #define EPWM_CTL0_CTRLD1_Msk (0x1ul << EPWM_CTL0_CTRLD1_Pos) |
EPWM_T::CTL0: CTRLD1 Mask
Definition at line 2201 of file epwm_reg.h.
| #define EPWM_CTL0_CTRLD1_Pos (1) |
EPWM_T::CTL0: CTRLD1 Position
Definition at line 2200 of file epwm_reg.h.
| #define EPWM_CTL0_CTRLD2_Msk (0x1ul << EPWM_CTL0_CTRLD2_Pos) |
EPWM_T::CTL0: CTRLD2 Mask
Definition at line 2204 of file epwm_reg.h.
| #define EPWM_CTL0_CTRLD2_Pos (2) |
EPWM_T::CTL0: CTRLD2 Position
Definition at line 2203 of file epwm_reg.h.
| #define EPWM_CTL0_CTRLD3_Msk (0x1ul << EPWM_CTL0_CTRLD3_Pos) |
EPWM_T::CTL0: CTRLD3 Mask
Definition at line 2207 of file epwm_reg.h.
| #define EPWM_CTL0_CTRLD3_Pos (3) |
EPWM_T::CTL0: CTRLD3 Position
Definition at line 2206 of file epwm_reg.h.
| #define EPWM_CTL0_CTRLD4_Msk (0x1ul << EPWM_CTL0_CTRLD4_Pos) |
EPWM_T::CTL0: CTRLD4 Mask
Definition at line 2210 of file epwm_reg.h.
| #define EPWM_CTL0_CTRLD4_Pos (4) |
EPWM_T::CTL0: CTRLD4 Position
Definition at line 2209 of file epwm_reg.h.
| #define EPWM_CTL0_CTRLD5_Msk (0x1ul << EPWM_CTL0_CTRLD5_Pos) |
EPWM_T::CTL0: CTRLD5 Mask
Definition at line 2213 of file epwm_reg.h.
| #define EPWM_CTL0_CTRLD5_Pos (5) |
EPWM_T::CTL0: CTRLD5 Position
Definition at line 2212 of file epwm_reg.h.
| #define EPWM_CTL0_DBGHALT_Msk (0x1ul << EPWM_CTL0_DBGHALT_Pos) |
EPWM_T::CTL0: DBGHALT Mask
Definition at line 2255 of file epwm_reg.h.
| #define EPWM_CTL0_DBGHALT_Pos (30) |
EPWM_T::CTL0: DBGHALT Position
Definition at line 2254 of file epwm_reg.h.
| #define EPWM_CTL0_DBGTRIOFF_Msk (0x1ul << EPWM_CTL0_DBGTRIOFF_Pos) |
EPWM_T::CTL0: DBGTRIOFF Mask
Definition at line 2258 of file epwm_reg.h.
| #define EPWM_CTL0_DBGTRIOFF_Pos (31) |
EPWM_T::CTL0: DBGTRIOFF Position
Definition at line 2257 of file epwm_reg.h.
| #define EPWM_CTL0_GROUPEN_Msk (0x1ul << EPWM_CTL0_GROUPEN_Pos) |
EPWM_T::CTL0: GROUPEN Mask
Definition at line 2252 of file epwm_reg.h.
| #define EPWM_CTL0_GROUPEN_Pos (24) |
EPWM_T::CTL0: GROUPEN Position
Definition at line 2251 of file epwm_reg.h.
| #define EPWM_CTL0_IMMLDEN0_Msk (0x1ul << EPWM_CTL0_IMMLDEN0_Pos) |
EPWM_T::CTL0: IMMLDEN0 Mask
Definition at line 2234 of file epwm_reg.h.
| #define EPWM_CTL0_IMMLDEN0_Pos (16) |
EPWM_T::CTL0: IMMLDEN0 Position
Definition at line 2233 of file epwm_reg.h.
| #define EPWM_CTL0_IMMLDEN1_Msk (0x1ul << EPWM_CTL0_IMMLDEN1_Pos) |
EPWM_T::CTL0: IMMLDEN1 Mask
Definition at line 2237 of file epwm_reg.h.
| #define EPWM_CTL0_IMMLDEN1_Pos (17) |
EPWM_T::CTL0: IMMLDEN1 Position
Definition at line 2236 of file epwm_reg.h.
| #define EPWM_CTL0_IMMLDEN2_Msk (0x1ul << EPWM_CTL0_IMMLDEN2_Pos) |
EPWM_T::CTL0: IMMLDEN2 Mask
Definition at line 2240 of file epwm_reg.h.
| #define EPWM_CTL0_IMMLDEN2_Pos (18) |
EPWM_T::CTL0: IMMLDEN2 Position
Definition at line 2239 of file epwm_reg.h.
| #define EPWM_CTL0_IMMLDEN3_Msk (0x1ul << EPWM_CTL0_IMMLDEN3_Pos) |
EPWM_T::CTL0: IMMLDEN3 Mask
Definition at line 2243 of file epwm_reg.h.
| #define EPWM_CTL0_IMMLDEN3_Pos (19) |
EPWM_T::CTL0: IMMLDEN3 Position
Definition at line 2242 of file epwm_reg.h.
| #define EPWM_CTL0_IMMLDEN4_Msk (0x1ul << EPWM_CTL0_IMMLDEN4_Pos) |
EPWM_T::CTL0: IMMLDEN4 Mask
Definition at line 2246 of file epwm_reg.h.
| #define EPWM_CTL0_IMMLDEN4_Pos (20) |
EPWM_T::CTL0: IMMLDEN4 Position
Definition at line 2245 of file epwm_reg.h.
| #define EPWM_CTL0_IMMLDEN5_Msk (0x1ul << EPWM_CTL0_IMMLDEN5_Pos) |
EPWM_T::CTL0: IMMLDEN5 Mask
Definition at line 2249 of file epwm_reg.h.
| #define EPWM_CTL0_IMMLDEN5_Pos (21) |
EPWM_T::CTL0: IMMLDEN5 Position
Definition at line 2248 of file epwm_reg.h.
| #define EPWM_CTL0_WINLDEN0_Msk (0x1ul << EPWM_CTL0_WINLDEN0_Pos) |
EPWM_T::CTL0: WINLDEN0 Mask
Definition at line 2216 of file epwm_reg.h.
| #define EPWM_CTL0_WINLDEN0_Pos (8) |
EPWM_T::CTL0: WINLDEN0 Position
Definition at line 2215 of file epwm_reg.h.
| #define EPWM_CTL0_WINLDEN1_Msk (0x1ul << EPWM_CTL0_WINLDEN1_Pos) |
EPWM_T::CTL0: WINLDEN1 Mask
Definition at line 2219 of file epwm_reg.h.
| #define EPWM_CTL0_WINLDEN1_Pos (9) |
EPWM_T::CTL0: WINLDEN1 Position
Definition at line 2218 of file epwm_reg.h.
| #define EPWM_CTL0_WINLDEN2_Msk (0x1ul << EPWM_CTL0_WINLDEN2_Pos) |
EPWM_T::CTL0: WINLDEN2 Mask
Definition at line 2222 of file epwm_reg.h.
| #define EPWM_CTL0_WINLDEN2_Pos (10) |
EPWM_T::CTL0: WINLDEN2 Position
Definition at line 2221 of file epwm_reg.h.
| #define EPWM_CTL0_WINLDEN3_Msk (0x1ul << EPWM_CTL0_WINLDEN3_Pos) |
EPWM_T::CTL0: WINLDEN3 Mask
Definition at line 2225 of file epwm_reg.h.
| #define EPWM_CTL0_WINLDEN3_Pos (11) |
EPWM_T::CTL0: WINLDEN3 Position
Definition at line 2224 of file epwm_reg.h.
| #define EPWM_CTL0_WINLDEN4_Msk (0x1ul << EPWM_CTL0_WINLDEN4_Pos) |
EPWM_T::CTL0: WINLDEN4 Mask
Definition at line 2228 of file epwm_reg.h.
| #define EPWM_CTL0_WINLDEN4_Pos (12) |
EPWM_T::CTL0: WINLDEN4 Position
Definition at line 2227 of file epwm_reg.h.
| #define EPWM_CTL0_WINLDEN5_Msk (0x1ul << EPWM_CTL0_WINLDEN5_Pos) |
EPWM_T::CTL0: WINLDEN5 Mask
Definition at line 2231 of file epwm_reg.h.
| #define EPWM_CTL0_WINLDEN5_Pos (13) |
EPWM_T::CTL0: WINLDEN5 Position
Definition at line 2230 of file epwm_reg.h.
| #define EPWM_CTL1_CNTMODE0_Msk (0x1ul << EPWM_CTL1_CNTMODE0_Pos) |
EPWM_T::CTL1: CNTMODE0 Mask
Definition at line 2279 of file epwm_reg.h.
| #define EPWM_CTL1_CNTMODE0_Pos (16) |
EPWM_T::CTL1: CNTMODE0 Position
Definition at line 2278 of file epwm_reg.h.
| #define EPWM_CTL1_CNTMODE1_Msk (0x1ul << EPWM_CTL1_CNTMODE1_Pos) |
EPWM_T::CTL1: CNTMODE1 Mask
Definition at line 2282 of file epwm_reg.h.
| #define EPWM_CTL1_CNTMODE1_Pos (17) |
EPWM_T::CTL1: CNTMODE1 Position
Definition at line 2281 of file epwm_reg.h.
| #define EPWM_CTL1_CNTMODE2_Msk (0x1ul << EPWM_CTL1_CNTMODE2_Pos) |
EPWM_T::CTL1: CNTMODE2 Mask
Definition at line 2285 of file epwm_reg.h.
| #define EPWM_CTL1_CNTMODE2_Pos (18) |
EPWM_T::CTL1: CNTMODE2 Position
Definition at line 2284 of file epwm_reg.h.
| #define EPWM_CTL1_CNTMODE3_Msk (0x1ul << EPWM_CTL1_CNTMODE3_Pos) |
EPWM_T::CTL1: CNTMODE3 Mask
Definition at line 2288 of file epwm_reg.h.
| #define EPWM_CTL1_CNTMODE3_Pos (19) |
EPWM_T::CTL1: CNTMODE3 Position
Definition at line 2287 of file epwm_reg.h.
| #define EPWM_CTL1_CNTMODE4_Msk (0x1ul << EPWM_CTL1_CNTMODE4_Pos) |
EPWM_T::CTL1: CNTMODE4 Mask
Definition at line 2291 of file epwm_reg.h.
| #define EPWM_CTL1_CNTMODE4_Pos (20) |
EPWM_T::CTL1: CNTMODE4 Position
Definition at line 2290 of file epwm_reg.h.
| #define EPWM_CTL1_CNTMODE5_Msk (0x1ul << EPWM_CTL1_CNTMODE5_Pos) |
EPWM_T::CTL1: CNTMODE5 Mask
Definition at line 2294 of file epwm_reg.h.
| #define EPWM_CTL1_CNTMODE5_Pos (21) |
EPWM_T::CTL1: CNTMODE5 Position
Definition at line 2293 of file epwm_reg.h.
| #define EPWM_CTL1_CNTTYPE0_Msk (0x3ul << EPWM_CTL1_CNTTYPE0_Pos) |
EPWM_T::CTL1: CNTTYPE0 Mask
Definition at line 2261 of file epwm_reg.h.
| #define EPWM_CTL1_CNTTYPE0_Pos (0) |
EPWM_T::CTL1: CNTTYPE0 Position
Definition at line 2260 of file epwm_reg.h.
| #define EPWM_CTL1_CNTTYPE1_Msk (0x3ul << EPWM_CTL1_CNTTYPE1_Pos) |
EPWM_T::CTL1: CNTTYPE1 Mask
Definition at line 2264 of file epwm_reg.h.
| #define EPWM_CTL1_CNTTYPE1_Pos (2) |
EPWM_T::CTL1: CNTTYPE1 Position
Definition at line 2263 of file epwm_reg.h.
| #define EPWM_CTL1_CNTTYPE2_Msk (0x3ul << EPWM_CTL1_CNTTYPE2_Pos) |
EPWM_T::CTL1: CNTTYPE2 Mask
Definition at line 2267 of file epwm_reg.h.
| #define EPWM_CTL1_CNTTYPE2_Pos (4) |
EPWM_T::CTL1: CNTTYPE2 Position
Definition at line 2266 of file epwm_reg.h.
| #define EPWM_CTL1_CNTTYPE3_Msk (0x3ul << EPWM_CTL1_CNTTYPE3_Pos) |
EPWM_T::CTL1: CNTTYPE3 Mask
Definition at line 2270 of file epwm_reg.h.
| #define EPWM_CTL1_CNTTYPE3_Pos (6) |
EPWM_T::CTL1: CNTTYPE3 Position
Definition at line 2269 of file epwm_reg.h.
| #define EPWM_CTL1_CNTTYPE4_Msk (0x3ul << EPWM_CTL1_CNTTYPE4_Pos) |
EPWM_T::CTL1: CNTTYPE4 Mask
Definition at line 2273 of file epwm_reg.h.
| #define EPWM_CTL1_CNTTYPE4_Pos (8) |
EPWM_T::CTL1: CNTTYPE4 Position
Definition at line 2272 of file epwm_reg.h.
| #define EPWM_CTL1_CNTTYPE5_Msk (0x3ul << EPWM_CTL1_CNTTYPE5_Pos) |
EPWM_T::CTL1: CNTTYPE5 Mask
Definition at line 2276 of file epwm_reg.h.
| #define EPWM_CTL1_CNTTYPE5_Pos (10) |
EPWM_T::CTL1: CNTTYPE5 Position
Definition at line 2275 of file epwm_reg.h.
| #define EPWM_CTL1_OUTMODE0_Msk (0x1ul << EPWM_CTL1_OUTMODE0_Pos) |
EPWM_T::CTL1: OUTMODE0 Mask
Definition at line 2297 of file epwm_reg.h.
| #define EPWM_CTL1_OUTMODE0_Pos (24) |
EPWM_T::CTL1: OUTMODE0 Position
Definition at line 2296 of file epwm_reg.h.
| #define EPWM_CTL1_OUTMODE2_Msk (0x1ul << EPWM_CTL1_OUTMODE2_Pos) |
EPWM_T::CTL1: OUTMODE2 Mask
Definition at line 2300 of file epwm_reg.h.
| #define EPWM_CTL1_OUTMODE2_Pos (25) |
EPWM_T::CTL1: OUTMODE2 Position
Definition at line 2299 of file epwm_reg.h.
| #define EPWM_CTL1_OUTMODE4_Msk (0x1ul << EPWM_CTL1_OUTMODE4_Pos) |
EPWM_T::CTL1: OUTMODE4 Mask
Definition at line 2303 of file epwm_reg.h.
| #define EPWM_CTL1_OUTMODE4_Pos (26) |
EPWM_T::CTL1: OUTMODE4 Position
Definition at line 2302 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CDTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE0_Pos) |
EPWM_T::DACTRGEN: CDTRGE0 Mask
Definition at line 3152 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CDTRGE0_Pos (24) |
EPWM_T::DACTRGEN: CDTRGE0 Position
Definition at line 3151 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CDTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE1_Pos) |
EPWM_T::DACTRGEN: CDTRGE1 Mask
Definition at line 3155 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CDTRGE1_Pos (25) |
EPWM_T::DACTRGEN: CDTRGE1 Position
Definition at line 3154 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CDTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE2_Pos) |
EPWM_T::DACTRGEN: CDTRGE2 Mask
Definition at line 3158 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CDTRGE2_Pos (26) |
EPWM_T::DACTRGEN: CDTRGE2 Position
Definition at line 3157 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CDTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE3_Pos) |
EPWM_T::DACTRGEN: CDTRGE3 Mask
Definition at line 3161 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CDTRGE3_Pos (27) |
EPWM_T::DACTRGEN: CDTRGE3 Position
Definition at line 3160 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CDTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE4_Pos) |
EPWM_T::DACTRGEN: CDTRGE4 Mask
Definition at line 3164 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CDTRGE4_Pos (28) |
EPWM_T::DACTRGEN: CDTRGE4 Position
Definition at line 3163 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CDTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CDTRGE5_Pos) |
EPWM_T::DACTRGEN: CDTRGE5 Mask
Definition at line 3167 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CDTRGE5_Pos (29) |
EPWM_T::DACTRGEN: CDTRGE5 Position
Definition at line 3166 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CUTRGE0_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE0_Pos) |
EPWM_T::DACTRGEN: CUTRGE0 Mask
Definition at line 3134 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CUTRGE0_Pos (16) |
EPWM_T::DACTRGEN: CUTRGE0 Position
Definition at line 3133 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CUTRGE1_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE1_Pos) |
EPWM_T::DACTRGEN: CUTRGE1 Mask
Definition at line 3137 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CUTRGE1_Pos (17) |
EPWM_T::DACTRGEN: CUTRGE1 Position
Definition at line 3136 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CUTRGE2_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE2_Pos) |
EPWM_T::DACTRGEN: CUTRGE2 Mask
Definition at line 3140 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CUTRGE2_Pos (18) |
EPWM_T::DACTRGEN: CUTRGE2 Position
Definition at line 3139 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CUTRGE3_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE3_Pos) |
EPWM_T::DACTRGEN: CUTRGE3 Mask
Definition at line 3143 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CUTRGE3_Pos (19) |
EPWM_T::DACTRGEN: CUTRGE3 Position
Definition at line 3142 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CUTRGE4_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE4_Pos) |
EPWM_T::DACTRGEN: CUTRGE4 Mask
Definition at line 3146 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CUTRGE4_Pos (20) |
EPWM_T::DACTRGEN: CUTRGE4 Position
Definition at line 3145 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CUTRGE5_Msk (0x1ul << EPWM_DACTRGEN_CUTRGE5_Pos) |
EPWM_T::DACTRGEN: CUTRGE5 Mask
Definition at line 3149 of file epwm_reg.h.
| #define EPWM_DACTRGEN_CUTRGE5_Pos (21) |
EPWM_T::DACTRGEN: CUTRGE5 Position
Definition at line 3148 of file epwm_reg.h.
| #define EPWM_DACTRGEN_PTE0_Msk (0x1ul << EPWM_DACTRGEN_PTE0_Pos) |
EPWM_T::DACTRGEN: PTE0 Mask
Definition at line 3116 of file epwm_reg.h.
| #define EPWM_DACTRGEN_PTE0_Pos (8) |
EPWM_T::DACTRGEN: PTE0 Position
Definition at line 3115 of file epwm_reg.h.
| #define EPWM_DACTRGEN_PTE1_Msk (0x1ul << EPWM_DACTRGEN_PTE1_Pos) |
EPWM_T::DACTRGEN: PTE1 Mask
Definition at line 3119 of file epwm_reg.h.
| #define EPWM_DACTRGEN_PTE1_Pos (9) |
EPWM_T::DACTRGEN: PTE1 Position
Definition at line 3118 of file epwm_reg.h.
| #define EPWM_DACTRGEN_PTE2_Msk (0x1ul << EPWM_DACTRGEN_PTE2_Pos) |
EPWM_T::DACTRGEN: PTE2 Mask
Definition at line 3122 of file epwm_reg.h.
| #define EPWM_DACTRGEN_PTE2_Pos (10) |
EPWM_T::DACTRGEN: PTE2 Position
Definition at line 3121 of file epwm_reg.h.
| #define EPWM_DACTRGEN_PTE3_Msk (0x1ul << EPWM_DACTRGEN_PTE3_Pos) |
EPWM_T::DACTRGEN: PTE3 Mask
Definition at line 3125 of file epwm_reg.h.
| #define EPWM_DACTRGEN_PTE3_Pos (11) |
EPWM_T::DACTRGEN: PTE3 Position
Definition at line 3124 of file epwm_reg.h.
| #define EPWM_DACTRGEN_PTE4_Msk (0x1ul << EPWM_DACTRGEN_PTE4_Pos) |
EPWM_T::DACTRGEN: PTE4 Mask
Definition at line 3128 of file epwm_reg.h.
| #define EPWM_DACTRGEN_PTE4_Pos (12) |
EPWM_T::DACTRGEN: PTE4 Position
Definition at line 3127 of file epwm_reg.h.
| #define EPWM_DACTRGEN_PTE5_Msk (0x1ul << EPWM_DACTRGEN_PTE5_Pos) |
EPWM_T::DACTRGEN: PTE5 Mask
Definition at line 3131 of file epwm_reg.h.
| #define EPWM_DACTRGEN_PTE5_Pos (13) |
EPWM_T::DACTRGEN: PTE5 Position
Definition at line 3130 of file epwm_reg.h.
| #define EPWM_DACTRGEN_ZTE0_Msk (0x1ul << EPWM_DACTRGEN_ZTE0_Pos) |
EPWM_T::DACTRGEN: ZTE0 Mask
Definition at line 3098 of file epwm_reg.h.
| #define EPWM_DACTRGEN_ZTE0_Pos (0) |
EPWM_T::DACTRGEN: ZTE0 Position
Definition at line 3097 of file epwm_reg.h.
| #define EPWM_DACTRGEN_ZTE1_Msk (0x1ul << EPWM_DACTRGEN_ZTE1_Pos) |
EPWM_T::DACTRGEN: ZTE1 Mask
Definition at line 3101 of file epwm_reg.h.
| #define EPWM_DACTRGEN_ZTE1_Pos (1) |
EPWM_T::DACTRGEN: ZTE1 Position
Definition at line 3100 of file epwm_reg.h.
| #define EPWM_DACTRGEN_ZTE2_Msk (0x1ul << EPWM_DACTRGEN_ZTE2_Pos) |
EPWM_T::DACTRGEN: ZTE2 Mask
Definition at line 3104 of file epwm_reg.h.
| #define EPWM_DACTRGEN_ZTE2_Pos (2) |
EPWM_T::DACTRGEN: ZTE2 Position
Definition at line 3103 of file epwm_reg.h.
| #define EPWM_DACTRGEN_ZTE3_Msk (0x1ul << EPWM_DACTRGEN_ZTE3_Pos) |
EPWM_T::DACTRGEN: ZTE3 Mask
Definition at line 3107 of file epwm_reg.h.
| #define EPWM_DACTRGEN_ZTE3_Pos (3) |
EPWM_T::DACTRGEN: ZTE3 Position
Definition at line 3106 of file epwm_reg.h.
| #define EPWM_DACTRGEN_ZTE4_Msk (0x1ul << EPWM_DACTRGEN_ZTE4_Pos) |
EPWM_T::DACTRGEN: ZTE4 Mask
Definition at line 3110 of file epwm_reg.h.
| #define EPWM_DACTRGEN_ZTE4_Pos (4) |
EPWM_T::DACTRGEN: ZTE4 Position
Definition at line 3109 of file epwm_reg.h.
| #define EPWM_DACTRGEN_ZTE5_Msk (0x1ul << EPWM_DACTRGEN_ZTE5_Pos) |
EPWM_T::DACTRGEN: ZTE5 Mask
Definition at line 3113 of file epwm_reg.h.
| #define EPWM_DACTRGEN_ZTE5_Pos (5) |
EPWM_T::DACTRGEN: ZTE5 Position
Definition at line 3112 of file epwm_reg.h.
| #define EPWM_DTCTL0_1_DTCKSEL_Msk (0x1ul << EPWM_DTCTL0_1_DTCKSEL_Pos) |
EPWM_T::DTCTL0_1: DTCKSEL Mask
Definition at line 2468 of file epwm_reg.h.
| #define EPWM_DTCTL0_1_DTCKSEL_Pos (24) |
EPWM_T::DTCTL0_1: DTCKSEL Position
Definition at line 2467 of file epwm_reg.h.
| #define EPWM_DTCTL0_1_DTCNT_Msk (0xffful << EPWM_DTCTL0_1_DTCNT_Pos) |
EPWM_T::DTCTL0_1: DTCNT Mask
Definition at line 2462 of file epwm_reg.h.
| #define EPWM_DTCTL0_1_DTCNT_Pos (0) |
EPWM_T::DTCTL0_1: DTCNT Position
Definition at line 2461 of file epwm_reg.h.
| #define EPWM_DTCTL0_1_DTEN_Msk (0x1ul << EPWM_DTCTL0_1_DTEN_Pos) |
EPWM_T::DTCTL0_1: DTEN Mask
Definition at line 2465 of file epwm_reg.h.
| #define EPWM_DTCTL0_1_DTEN_Pos (16) |
EPWM_T::DTCTL0_1: DTEN Position
Definition at line 2464 of file epwm_reg.h.
| #define EPWM_DTCTL2_3_DTCKSEL_Msk (0x1ul << EPWM_DTCTL2_3_DTCKSEL_Pos) |
EPWM_T::DTCTL2_3: DTCKSEL Mask
Definition at line 2477 of file epwm_reg.h.
| #define EPWM_DTCTL2_3_DTCKSEL_Pos (24) |
EPWM_T::DTCTL2_3: DTCKSEL Position
Definition at line 2476 of file epwm_reg.h.
| #define EPWM_DTCTL2_3_DTCNT_Msk (0xffful << EPWM_DTCTL2_3_DTCNT_Pos) |
EPWM_T::DTCTL2_3: DTCNT Mask
Definition at line 2471 of file epwm_reg.h.
| #define EPWM_DTCTL2_3_DTCNT_Pos (0) |
EPWM_T::DTCTL2_3: DTCNT Position
Definition at line 2470 of file epwm_reg.h.
| #define EPWM_DTCTL2_3_DTEN_Msk (0x1ul << EPWM_DTCTL2_3_DTEN_Pos) |
EPWM_T::DTCTL2_3: DTEN Mask
Definition at line 2474 of file epwm_reg.h.
| #define EPWM_DTCTL2_3_DTEN_Pos (16) |
EPWM_T::DTCTL2_3: DTEN Position
Definition at line 2473 of file epwm_reg.h.
| #define EPWM_DTCTL4_5_DTCKSEL_Msk (0x1ul << EPWM_DTCTL4_5_DTCKSEL_Pos) |
EPWM_T::DTCTL4_5: DTCKSEL Mask
Definition at line 2486 of file epwm_reg.h.
| #define EPWM_DTCTL4_5_DTCKSEL_Pos (24) |
EPWM_T::DTCTL4_5: DTCKSEL Position
Definition at line 2485 of file epwm_reg.h.
| #define EPWM_DTCTL4_5_DTCNT_Msk (0xffful << EPWM_DTCTL4_5_DTCNT_Pos) |
EPWM_T::DTCTL4_5: DTCNT Mask
Definition at line 2480 of file epwm_reg.h.
| #define EPWM_DTCTL4_5_DTCNT_Pos (0) |
EPWM_T::DTCTL4_5: DTCNT Position
Definition at line 2479 of file epwm_reg.h.
| #define EPWM_DTCTL4_5_DTEN_Msk (0x1ul << EPWM_DTCTL4_5_DTEN_Pos) |
EPWM_T::DTCTL4_5: DTEN Mask
Definition at line 2483 of file epwm_reg.h.
| #define EPWM_DTCTL4_5_DTEN_Pos (16) |
EPWM_T::DTCTL4_5: DTEN Position
Definition at line 2482 of file epwm_reg.h.
| #define EPWM_EADCPSC0_EADCPSC0_Msk (0xful << EPWM_EADCPSC0_EADCPSC0_Pos) |
EPWM_T::EADCPSC0: EADCPSC0 Mask
Definition at line 3629 of file epwm_reg.h.
| #define EPWM_EADCPSC0_EADCPSC0_Pos (0) |
EPWM_T::EADCPSC0: EADCPSC0 Position
Definition at line 3628 of file epwm_reg.h.
| #define EPWM_EADCPSC0_EADCPSC1_Msk (0xful << EPWM_EADCPSC0_EADCPSC1_Pos) |
EPWM_T::EADCPSC0: EADCPSC1 Mask
Definition at line 3632 of file epwm_reg.h.
| #define EPWM_EADCPSC0_EADCPSC1_Pos (8) |
EPWM_T::EADCPSC0: EADCPSC1 Position
Definition at line 3631 of file epwm_reg.h.
| #define EPWM_EADCPSC0_EADCPSC2_Msk (0xful << EPWM_EADCPSC0_EADCPSC2_Pos) |
EPWM_T::EADCPSC0: EADCPSC2 Mask
Definition at line 3635 of file epwm_reg.h.
| #define EPWM_EADCPSC0_EADCPSC2_Pos (16) |
EPWM_T::EADCPSC0: EADCPSC2 Position
Definition at line 3634 of file epwm_reg.h.
| #define EPWM_EADCPSC0_EADCPSC3_Msk (0xful << EPWM_EADCPSC0_EADCPSC3_Pos) |
EPWM_T::EADCPSC0: EADCPSC3 Mask
Definition at line 3638 of file epwm_reg.h.
| #define EPWM_EADCPSC0_EADCPSC3_Pos (24) |
EPWM_T::EADCPSC0: EADCPSC3 Position
Definition at line 3637 of file epwm_reg.h.
| #define EPWM_EADCPSC1_EADCPSC4_Msk (0xful << EPWM_EADCPSC1_EADCPSC4_Pos) |
EPWM_T::EADCPSC1: EADCPSC4 Mask
Definition at line 3641 of file epwm_reg.h.
| #define EPWM_EADCPSC1_EADCPSC4_Pos (0) |
EPWM_T::EADCPSC1: EADCPSC4 Position
Definition at line 3640 of file epwm_reg.h.
| #define EPWM_EADCPSC1_EADCPSC5_Msk (0xful << EPWM_EADCPSC1_EADCPSC5_Pos) |
EPWM_T::EADCPSC1: EADCPSC5 Mask
Definition at line 3644 of file epwm_reg.h.
| #define EPWM_EADCPSC1_EADCPSC5_Pos (8) |
EPWM_T::EADCPSC1: EADCPSC5 Position
Definition at line 3643 of file epwm_reg.h.
| #define EPWM_EADCPSCCTL_PSCEN0_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN0_Pos) |
EPWM_T::EADCPSCCTL: PSCEN0 Mask
Definition at line 3611 of file epwm_reg.h.
| #define EPWM_EADCPSCCTL_PSCEN0_Pos (0) |
EPWM_T::EADCPSCCTL: PSCEN0 Position
Definition at line 3610 of file epwm_reg.h.
| #define EPWM_EADCPSCCTL_PSCEN1_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN1_Pos) |
EPWM_T::EADCPSCCTL: PSCEN1 Mask
Definition at line 3614 of file epwm_reg.h.
| #define EPWM_EADCPSCCTL_PSCEN1_Pos (1) |
EPWM_T::EADCPSCCTL: PSCEN1 Position
Definition at line 3613 of file epwm_reg.h.
| #define EPWM_EADCPSCCTL_PSCEN2_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN2_Pos) |
EPWM_T::EADCPSCCTL: PSCEN2 Mask
Definition at line 3617 of file epwm_reg.h.
| #define EPWM_EADCPSCCTL_PSCEN2_Pos (2) |
EPWM_T::EADCPSCCTL: PSCEN2 Position
Definition at line 3616 of file epwm_reg.h.
| #define EPWM_EADCPSCCTL_PSCEN3_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN3_Pos) |
EPWM_T::EADCPSCCTL: PSCEN3 Mask
Definition at line 3620 of file epwm_reg.h.
| #define EPWM_EADCPSCCTL_PSCEN3_Pos (3) |
EPWM_T::EADCPSCCTL: PSCEN3 Position
Definition at line 3619 of file epwm_reg.h.
| #define EPWM_EADCPSCCTL_PSCEN4_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN4_Pos) |
EPWM_T::EADCPSCCTL: PSCEN4 Mask
Definition at line 3623 of file epwm_reg.h.
| #define EPWM_EADCPSCCTL_PSCEN4_Pos (4) |
EPWM_T::EADCPSCCTL: PSCEN4 Position
Definition at line 3622 of file epwm_reg.h.
| #define EPWM_EADCPSCCTL_PSCEN5_Msk (0x1ul << EPWM_EADCPSCCTL_PSCEN5_Pos) |
EPWM_T::EADCPSCCTL: PSCEN5 Mask
Definition at line 3626 of file epwm_reg.h.
| #define EPWM_EADCPSCCTL_PSCEN5_Pos (5) |
EPWM_T::EADCPSCCTL: PSCEN5 Position
Definition at line 3625 of file epwm_reg.h.
| #define EPWM_EADCPSCNT0_PSCNT0_Msk (0xful << EPWM_EADCPSCNT0_PSCNT0_Pos) |
EPWM_T::EADCPSCNT0: PSCNT0 Mask
Definition at line 3647 of file epwm_reg.h.
| #define EPWM_EADCPSCNT0_PSCNT0_Pos (0) |
EPWM_T::EADCPSCNT0: PSCNT0 Position
Definition at line 3646 of file epwm_reg.h.
| #define EPWM_EADCPSCNT0_PSCNT1_Msk (0xful << EPWM_EADCPSCNT0_PSCNT1_Pos) |
EPWM_T::EADCPSCNT0: PSCNT1 Mask
Definition at line 3650 of file epwm_reg.h.
| #define EPWM_EADCPSCNT0_PSCNT1_Pos (8) |
EPWM_T::EADCPSCNT0: PSCNT1 Position
Definition at line 3649 of file epwm_reg.h.
| #define EPWM_EADCPSCNT0_PSCNT2_Msk (0xful << EPWM_EADCPSCNT0_PSCNT2_Pos) |
EPWM_T::EADCPSCNT0: PSCNT2 Mask
Definition at line 3653 of file epwm_reg.h.
| #define EPWM_EADCPSCNT0_PSCNT2_Pos (16) |
EPWM_T::EADCPSCNT0: PSCNT2 Position
Definition at line 3652 of file epwm_reg.h.
| #define EPWM_EADCPSCNT0_PSCNT3_Msk (0xful << EPWM_EADCPSCNT0_PSCNT3_Pos) |
EPWM_T::EADCPSCNT0: PSCNT3 Mask
Definition at line 3656 of file epwm_reg.h.
| #define EPWM_EADCPSCNT0_PSCNT3_Pos (24) |
EPWM_T::EADCPSCNT0: PSCNT3 Position
Definition at line 3655 of file epwm_reg.h.
| #define EPWM_EADCPSCNT1_PSCNT4_Msk (0xful << EPWM_EADCPSCNT1_PSCNT4_Pos) |
EPWM_T::EADCPSCNT1: PSCNT4 Mask
Definition at line 3659 of file epwm_reg.h.
| #define EPWM_EADCPSCNT1_PSCNT4_Pos (0) |
EPWM_T::EADCPSCNT1: PSCNT4 Position
Definition at line 3658 of file epwm_reg.h.
| #define EPWM_EADCPSCNT1_PSCNT5_Msk (0xful << EPWM_EADCPSCNT1_PSCNT5_Pos) |
EPWM_T::EADCPSCNT1: PSCNT5 Mask
Definition at line 3662 of file epwm_reg.h.
| #define EPWM_EADCPSCNT1_PSCNT5_Pos (8) |
EPWM_T::EADCPSCNT1: PSCNT5 Position
Definition at line 3661 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGEN0_Msk (0x1ul << EPWM_EADCTS0_TRGEN0_Pos) |
EPWM_T::EADCTS0: TRGEN0 Mask
Definition at line 3173 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGEN0_Pos (7) |
EPWM_T::EADCTS0: TRGEN0 Position
Definition at line 3172 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGEN1_Msk (0x1ul << EPWM_EADCTS0_TRGEN1_Pos) |
EPWM_T::EADCTS0: TRGEN1 Mask
Definition at line 3179 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGEN1_Pos (15) |
EPWM_T::EADCTS0: TRGEN1 Position
Definition at line 3178 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGEN2_Msk (0x1ul << EPWM_EADCTS0_TRGEN2_Pos) |
EPWM_T::EADCTS0: TRGEN2 Mask
Definition at line 3185 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGEN2_Pos (23) |
EPWM_T::EADCTS0: TRGEN2 Position
Definition at line 3184 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGEN3_Msk (0x1ul << EPWM_EADCTS0_TRGEN3_Pos) |
EPWM_T::EADCTS0: TRGEN3 Mask
Definition at line 3191 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGEN3_Pos (31) |
EPWM_T::EADCTS0: TRGEN3 Position
Definition at line 3190 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGSEL0_Msk (0xful << EPWM_EADCTS0_TRGSEL0_Pos) |
EPWM_T::EADCTS0: TRGSEL0 Mask
Definition at line 3170 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGSEL0_Pos (0) |
EPWM_T::EADCTS0: TRGSEL0 Position
Definition at line 3169 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGSEL1_Msk (0xful << EPWM_EADCTS0_TRGSEL1_Pos) |
EPWM_T::EADCTS0: TRGSEL1 Mask
Definition at line 3176 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGSEL1_Pos (8) |
EPWM_T::EADCTS0: TRGSEL1 Position
Definition at line 3175 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGSEL2_Msk (0xful << EPWM_EADCTS0_TRGSEL2_Pos) |
EPWM_T::EADCTS0: TRGSEL2 Mask
Definition at line 3182 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGSEL2_Pos (16) |
EPWM_T::EADCTS0: TRGSEL2 Position
Definition at line 3181 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGSEL3_Msk (0xful << EPWM_EADCTS0_TRGSEL3_Pos) |
EPWM_T::EADCTS0: TRGSEL3 Mask
Definition at line 3188 of file epwm_reg.h.
| #define EPWM_EADCTS0_TRGSEL3_Pos (24) |
EPWM_T::EADCTS0: TRGSEL3 Position
Definition at line 3187 of file epwm_reg.h.
| #define EPWM_EADCTS1_TRGEN4_Msk (0x1ul << EPWM_EADCTS1_TRGEN4_Pos) |
EPWM_T::EADCTS1: TRGEN4 Mask
Definition at line 3197 of file epwm_reg.h.
| #define EPWM_EADCTS1_TRGEN4_Pos (7) |
EPWM_T::EADCTS1: TRGEN4 Position
Definition at line 3196 of file epwm_reg.h.
| #define EPWM_EADCTS1_TRGEN5_Msk (0x1ul << EPWM_EADCTS1_TRGEN5_Pos) |
EPWM_T::EADCTS1: TRGEN5 Mask
Definition at line 3203 of file epwm_reg.h.
| #define EPWM_EADCTS1_TRGEN5_Pos (15) |
EPWM_T::EADCTS1: TRGEN5 Position
Definition at line 3202 of file epwm_reg.h.
| #define EPWM_EADCTS1_TRGSEL4_Msk (0xful << EPWM_EADCTS1_TRGSEL4_Pos) |
EPWM_T::EADCTS1: TRGSEL4 Mask
Definition at line 3194 of file epwm_reg.h.
| #define EPWM_EADCTS1_TRGSEL4_Pos (0) |
EPWM_T::EADCTS1: TRGSEL4 Position
Definition at line 3193 of file epwm_reg.h.
| #define EPWM_EADCTS1_TRGSEL5_Msk (0xful << EPWM_EADCTS1_TRGSEL5_Pos) |
EPWM_T::EADCTS1: TRGSEL5 Mask
Definition at line 3200 of file epwm_reg.h.
| #define EPWM_EADCTS1_TRGSEL5_Pos (8) |
EPWM_T::EADCTS1: TRGSEL5 Position
Definition at line 3199 of file epwm_reg.h.
| #define EPWM_FAILBRK_BODBRKEN_Msk (0x1ul << EPWM_FAILBRK_BODBRKEN_Pos) |
EPWM_T::FAILBRK: BODBRKEN Mask
Definition at line 2675 of file epwm_reg.h.
| #define EPWM_FAILBRK_BODBRKEN_Pos (1) |
EPWM_T::FAILBRK: BODBRKEN Position
Definition at line 2674 of file epwm_reg.h.
| #define EPWM_FAILBRK_CORBRKEN_Msk (0x1ul << EPWM_FAILBRK_CORBRKEN_Pos) |
EPWM_T::FAILBRK: CORBRKEN Mask
Definition at line 2681 of file epwm_reg.h.
| #define EPWM_FAILBRK_CORBRKEN_Pos (3) |
EPWM_T::FAILBRK: CORBRKEN Position
Definition at line 2680 of file epwm_reg.h.
| #define EPWM_FAILBRK_CSSBRKEN_Msk (0x1ul << EPWM_FAILBRK_CSSBRKEN_Pos) |
EPWM_T::FAILBRK: CSSBRKEN Mask
Definition at line 2672 of file epwm_reg.h.
| #define EPWM_FAILBRK_CSSBRKEN_Pos (0) |
EPWM_T::FAILBRK: CSSBRKEN Position
Definition at line 2671 of file epwm_reg.h.
| #define EPWM_FAILBRK_RAMBRKEN_Msk (0x1ul << EPWM_FAILBRK_RAMBRKEN_Pos) |
EPWM_T::FAILBRK: RAMBRKEN Mask
Definition at line 2678 of file epwm_reg.h.
| #define EPWM_FAILBRK_RAMBRKEN_Pos (2) |
EPWM_T::FAILBRK: RAMBRKEN Position
Definition at line 2677 of file epwm_reg.h.
| #define EPWM_FCAPDAT0_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT0_FCAPDAT_Pos) |
EPWM_T::FCAPDAT0: FCAPDAT Mask
Definition at line 3794 of file epwm_reg.h.
| #define EPWM_FCAPDAT0_FCAPDAT_Pos (0) |
EPWM_T::FCAPDAT0: FCAPDAT Position
Definition at line 3793 of file epwm_reg.h.
| #define EPWM_FCAPDAT1_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT1_FCAPDAT_Pos) |
EPWM_T::FCAPDAT1: FCAPDAT Mask
Definition at line 3800 of file epwm_reg.h.
| #define EPWM_FCAPDAT1_FCAPDAT_Pos (0) |
EPWM_T::FCAPDAT1: FCAPDAT Position
Definition at line 3799 of file epwm_reg.h.
| #define EPWM_FCAPDAT2_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT2_FCAPDAT_Pos) |
EPWM_T::FCAPDAT2: FCAPDAT Mask
Definition at line 3806 of file epwm_reg.h.
| #define EPWM_FCAPDAT2_FCAPDAT_Pos (0) |
EPWM_T::FCAPDAT2: FCAPDAT Position
Definition at line 3805 of file epwm_reg.h.
| #define EPWM_FCAPDAT3_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT3_FCAPDAT_Pos) |
EPWM_T::FCAPDAT3: FCAPDAT Mask
Definition at line 3812 of file epwm_reg.h.
| #define EPWM_FCAPDAT3_FCAPDAT_Pos (0) |
EPWM_T::FCAPDAT3: FCAPDAT Position
Definition at line 3811 of file epwm_reg.h.
| #define EPWM_FCAPDAT4_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT4_FCAPDAT_Pos) |
EPWM_T::FCAPDAT4: FCAPDAT Mask
Definition at line 3818 of file epwm_reg.h.
| #define EPWM_FCAPDAT4_FCAPDAT_Pos (0) |
EPWM_T::FCAPDAT4: FCAPDAT Position
Definition at line 3817 of file epwm_reg.h.
| #define EPWM_FCAPDAT5_FCAPDAT_Msk (0xfffful << EPWM_FCAPDAT5_FCAPDAT_Pos) |
EPWM_T::FCAPDAT5: FCAPDAT Mask
Definition at line 3824 of file epwm_reg.h.
| #define EPWM_FCAPDAT5_FCAPDAT_Pos (0) |
EPWM_T::FCAPDAT5: FCAPDAT Position
Definition at line 3823 of file epwm_reg.h.
| #define EPWM_FDCTL0_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL0_DGSMPCYC_Pos) |
EPWM_T::FDCTL0: DGSMPCYC Mask
Definition at line 3491 of file epwm_reg.h.
| #define EPWM_FDCTL0_DGSMPCYC_Pos (16) |
EPWM_T::FDCTL0: DGSMPCYC Position
Definition at line 3490 of file epwm_reg.h.
| #define EPWM_FDCTL0_FDCKSEL_Msk (0x3ul << EPWM_FDCTL0_FDCKSEL_Pos) |
EPWM_T::FDCTL0: FDCKSEL Mask
Definition at line 3494 of file epwm_reg.h.
| #define EPWM_FDCTL0_FDCKSEL_Pos (28) |
EPWM_T::FDCTL0: FDCKSEL Position
Definition at line 3493 of file epwm_reg.h.
| #define EPWM_FDCTL0_FDDGEN_Msk (0x1ul << EPWM_FDCTL0_FDDGEN_Pos) |
EPWM_T::FDCTL0: FDDGEN Mask
Definition at line 3497 of file epwm_reg.h.
| #define EPWM_FDCTL0_FDDGEN_Pos (31) |
EPWM_T::FDCTL0: FDDGEN Position
Definition at line 3496 of file epwm_reg.h.
| #define EPWM_FDCTL0_FDMSKEN_Msk (0x1ul << EPWM_FDCTL0_FDMSKEN_Pos) |
EPWM_T::FDCTL0: FDMSKEN Mask
Definition at line 3488 of file epwm_reg.h.
| #define EPWM_FDCTL0_FDMSKEN_Pos (15) |
EPWM_T::FDCTL0: FDMSKEN Position
Definition at line 3487 of file epwm_reg.h.
| #define EPWM_FDCTL0_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL0_TRMSKCNT_Pos) |
EPWM_T::FDCTL0: TRMSKCNT Mask
Definition at line 3485 of file epwm_reg.h.
| #define EPWM_FDCTL0_TRMSKCNT_Pos (0) |
EPWM_T::FDCTL0: TRMSKCNT Position
Definition at line 3484 of file epwm_reg.h.
| #define EPWM_FDCTL1_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL1_DGSMPCYC_Pos) |
EPWM_T::FDCTL1: DGSMPCYC Mask
Definition at line 3506 of file epwm_reg.h.
| #define EPWM_FDCTL1_DGSMPCYC_Pos (16) |
EPWM_T::FDCTL1: DGSMPCYC Position
Definition at line 3505 of file epwm_reg.h.
| #define EPWM_FDCTL1_FDCKSEL_Msk (0x3ul << EPWM_FDCTL1_FDCKSEL_Pos) |
EPWM_T::FDCTL1: FDCKSEL Mask
Definition at line 3509 of file epwm_reg.h.
| #define EPWM_FDCTL1_FDCKSEL_Pos (28) |
EPWM_T::FDCTL1: FDCKSEL Position
Definition at line 3508 of file epwm_reg.h.
| #define EPWM_FDCTL1_FDDGEN_Msk (0x1ul << EPWM_FDCTL1_FDDGEN_Pos) |
EPWM_T::FDCTL1: FDDGEN Mask
Definition at line 3512 of file epwm_reg.h.
| #define EPWM_FDCTL1_FDDGEN_Pos (31) |
EPWM_T::FDCTL1: FDDGEN Position
Definition at line 3511 of file epwm_reg.h.
| #define EPWM_FDCTL1_FDMSKEN_Msk (0x1ul << EPWM_FDCTL1_FDMSKEN_Pos) |
EPWM_T::FDCTL1: FDMSKEN Mask
Definition at line 3503 of file epwm_reg.h.
| #define EPWM_FDCTL1_FDMSKEN_Pos (15) |
EPWM_T::FDCTL1: FDMSKEN Position
Definition at line 3502 of file epwm_reg.h.
| #define EPWM_FDCTL1_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL1_TRMSKCNT_Pos) |
EPWM_T::FDCTL1: TRMSKCNT Mask
Definition at line 3500 of file epwm_reg.h.
| #define EPWM_FDCTL1_TRMSKCNT_Pos (0) |
EPWM_T::FDCTL1: TRMSKCNT Position
Definition at line 3499 of file epwm_reg.h.
| #define EPWM_FDCTL2_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL2_DGSMPCYC_Pos) |
EPWM_T::FDCTL2: DGSMPCYC Mask
Definition at line 3521 of file epwm_reg.h.
| #define EPWM_FDCTL2_DGSMPCYC_Pos (16) |
EPWM_T::FDCTL2: DGSMPCYC Position
Definition at line 3520 of file epwm_reg.h.
| #define EPWM_FDCTL2_FDCKSEL_Msk (0x3ul << EPWM_FDCTL2_FDCKSEL_Pos) |
EPWM_T::FDCTL2: FDCKSEL Mask
Definition at line 3524 of file epwm_reg.h.
| #define EPWM_FDCTL2_FDCKSEL_Pos (28) |
EPWM_T::FDCTL2: FDCKSEL Position
Definition at line 3523 of file epwm_reg.h.
| #define EPWM_FDCTL2_FDDGEN_Msk (0x1ul << EPWM_FDCTL2_FDDGEN_Pos) |
EPWM_T::FDCTL2: FDDGEN Mask
Definition at line 3527 of file epwm_reg.h.
| #define EPWM_FDCTL2_FDDGEN_Pos (31) |
EPWM_T::FDCTL2: FDDGEN Position
Definition at line 3526 of file epwm_reg.h.
| #define EPWM_FDCTL2_FDMSKEN_Msk (0x1ul << EPWM_FDCTL2_FDMSKEN_Pos) |
EPWM_T::FDCTL2: FDMSKEN Mask
Definition at line 3518 of file epwm_reg.h.
| #define EPWM_FDCTL2_FDMSKEN_Pos (15) |
EPWM_T::FDCTL2: FDMSKEN Position
Definition at line 3517 of file epwm_reg.h.
| #define EPWM_FDCTL2_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL2_TRMSKCNT_Pos) |
EPWM_T::FDCTL2: TRMSKCNT Mask
Definition at line 3515 of file epwm_reg.h.
| #define EPWM_FDCTL2_TRMSKCNT_Pos (0) |
EPWM_T::FDCTL2: TRMSKCNT Position
Definition at line 3514 of file epwm_reg.h.
| #define EPWM_FDCTL3_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL3_DGSMPCYC_Pos) |
EPWM_T::FDCTL3: DGSMPCYC Mask
Definition at line 3536 of file epwm_reg.h.
| #define EPWM_FDCTL3_DGSMPCYC_Pos (16) |
EPWM_T::FDCTL3: DGSMPCYC Position
Definition at line 3535 of file epwm_reg.h.
| #define EPWM_FDCTL3_FDCKSEL_Msk (0x3ul << EPWM_FDCTL3_FDCKSEL_Pos) |
EPWM_T::FDCTL3: FDCKSEL Mask
Definition at line 3539 of file epwm_reg.h.
| #define EPWM_FDCTL3_FDCKSEL_Pos (28) |
EPWM_T::FDCTL3: FDCKSEL Position
Definition at line 3538 of file epwm_reg.h.
| #define EPWM_FDCTL3_FDDGEN_Msk (0x1ul << EPWM_FDCTL3_FDDGEN_Pos) |
EPWM_T::FDCTL3: FDDGEN Mask
Definition at line 3542 of file epwm_reg.h.
| #define EPWM_FDCTL3_FDDGEN_Pos (31) |
EPWM_T::FDCTL3: FDDGEN Position
Definition at line 3541 of file epwm_reg.h.
| #define EPWM_FDCTL3_FDMSKEN_Msk (0x1ul << EPWM_FDCTL3_FDMSKEN_Pos) |
EPWM_T::FDCTL3: FDMSKEN Mask
Definition at line 3533 of file epwm_reg.h.
| #define EPWM_FDCTL3_FDMSKEN_Pos (15) |
EPWM_T::FDCTL3: FDMSKEN Position
Definition at line 3532 of file epwm_reg.h.
| #define EPWM_FDCTL3_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL3_TRMSKCNT_Pos) |
EPWM_T::FDCTL3: TRMSKCNT Mask
Definition at line 3530 of file epwm_reg.h.
| #define EPWM_FDCTL3_TRMSKCNT_Pos (0) |
EPWM_T::FDCTL3: TRMSKCNT Position
Definition at line 3529 of file epwm_reg.h.
| #define EPWM_FDCTL4_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL4_DGSMPCYC_Pos) |
EPWM_T::FDCTL4: DGSMPCYC Mask
Definition at line 3551 of file epwm_reg.h.
| #define EPWM_FDCTL4_DGSMPCYC_Pos (16) |
EPWM_T::FDCTL4: DGSMPCYC Position
Definition at line 3550 of file epwm_reg.h.
| #define EPWM_FDCTL4_FDCKSEL_Msk (0x3ul << EPWM_FDCTL4_FDCKSEL_Pos) |
EPWM_T::FDCTL4: FDCKSEL Mask
Definition at line 3554 of file epwm_reg.h.
| #define EPWM_FDCTL4_FDCKSEL_Pos (28) |
EPWM_T::FDCTL4: FDCKSEL Position
Definition at line 3553 of file epwm_reg.h.
| #define EPWM_FDCTL4_FDDGEN_Msk (0x1ul << EPWM_FDCTL4_FDDGEN_Pos) |
EPWM_T::FDCTL4: FDDGEN Mask
Definition at line 3557 of file epwm_reg.h.
| #define EPWM_FDCTL4_FDDGEN_Pos (31) |
EPWM_T::FDCTL4: FDDGEN Position
Definition at line 3556 of file epwm_reg.h.
| #define EPWM_FDCTL4_FDMSKEN_Msk (0x1ul << EPWM_FDCTL4_FDMSKEN_Pos) |
EPWM_T::FDCTL4: FDMSKEN Mask
Definition at line 3548 of file epwm_reg.h.
| #define EPWM_FDCTL4_FDMSKEN_Pos (15) |
EPWM_T::FDCTL4: FDMSKEN Position
Definition at line 3547 of file epwm_reg.h.
| #define EPWM_FDCTL4_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL4_TRMSKCNT_Pos) |
EPWM_T::FDCTL4: TRMSKCNT Mask
Definition at line 3545 of file epwm_reg.h.
| #define EPWM_FDCTL4_TRMSKCNT_Pos (0) |
EPWM_T::FDCTL4: TRMSKCNT Position
Definition at line 3544 of file epwm_reg.h.
| #define EPWM_FDCTL5_DGSMPCYC_Msk (0x7ul << EPWM_FDCTL5_DGSMPCYC_Pos) |
EPWM_T::FDCTL5: DGSMPCYC Mask
Definition at line 3566 of file epwm_reg.h.
| #define EPWM_FDCTL5_DGSMPCYC_Pos (16) |
EPWM_T::FDCTL5: DGSMPCYC Position
Definition at line 3565 of file epwm_reg.h.
| #define EPWM_FDCTL5_FDCKSEL_Msk (0x3ul << EPWM_FDCTL5_FDCKSEL_Pos) |
EPWM_T::FDCTL5: FDCKSEL Mask
Definition at line 3569 of file epwm_reg.h.
| #define EPWM_FDCTL5_FDCKSEL_Pos (28) |
EPWM_T::FDCTL5: FDCKSEL Position
Definition at line 3568 of file epwm_reg.h.
| #define EPWM_FDCTL5_FDDGEN_Msk (0x1ul << EPWM_FDCTL5_FDDGEN_Pos) |
EPWM_T::FDCTL5: FDDGEN Mask
Definition at line 3572 of file epwm_reg.h.
| #define EPWM_FDCTL5_FDDGEN_Pos (31) |
EPWM_T::FDCTL5: FDDGEN Position
Definition at line 3571 of file epwm_reg.h.
| #define EPWM_FDCTL5_FDMSKEN_Msk (0x1ul << EPWM_FDCTL5_FDMSKEN_Pos) |
EPWM_T::FDCTL5: FDMSKEN Mask
Definition at line 3563 of file epwm_reg.h.
| #define EPWM_FDCTL5_FDMSKEN_Pos (15) |
EPWM_T::FDCTL5: FDMSKEN Position
Definition at line 3562 of file epwm_reg.h.
| #define EPWM_FDCTL5_TRMSKCNT_Msk (0x7ful << EPWM_FDCTL5_TRMSKCNT_Pos) |
EPWM_T::FDCTL5: TRMSKCNT Mask
Definition at line 3560 of file epwm_reg.h.
| #define EPWM_FDCTL5_TRMSKCNT_Pos (0) |
EPWM_T::FDCTL5: TRMSKCNT Position
Definition at line 3559 of file epwm_reg.h.
| #define EPWM_FDEN_FDCKS0_Msk (0x1ul << EPWM_FDEN_FDCKS0_Pos) |
EPWM_T::FDEN: FDCKS0 Mask
Definition at line 3467 of file epwm_reg.h.
| #define EPWM_FDEN_FDCKS0_Pos (16) |
EPWM_T::FDEN: FDCKS0 Position
Definition at line 3466 of file epwm_reg.h.
| #define EPWM_FDEN_FDCKS1_Msk (0x1ul << EPWM_FDEN_FDCKS1_Pos) |
EPWM_T::FDEN: FDCKS1 Mask
Definition at line 3470 of file epwm_reg.h.
| #define EPWM_FDEN_FDCKS1_Pos (17) |
EPWM_T::FDEN: FDCKS1 Position
Definition at line 3469 of file epwm_reg.h.
| #define EPWM_FDEN_FDCKS2_Msk (0x1ul << EPWM_FDEN_FDCKS2_Pos) |
EPWM_T::FDEN: FDCKS2 Mask
Definition at line 3473 of file epwm_reg.h.
| #define EPWM_FDEN_FDCKS2_Pos (18) |
EPWM_T::FDEN: FDCKS2 Position
Definition at line 3472 of file epwm_reg.h.
| #define EPWM_FDEN_FDCKS3_Msk (0x1ul << EPWM_FDEN_FDCKS3_Pos) |
EPWM_T::FDEN: FDCKS3 Mask
Definition at line 3476 of file epwm_reg.h.
| #define EPWM_FDEN_FDCKS3_Pos (19) |
EPWM_T::FDEN: FDCKS3 Position
Definition at line 3475 of file epwm_reg.h.
| #define EPWM_FDEN_FDCKS4_Msk (0x1ul << EPWM_FDEN_FDCKS4_Pos) |
EPWM_T::FDEN: FDCKS4 Mask
Definition at line 3479 of file epwm_reg.h.
| #define EPWM_FDEN_FDCKS4_Pos (20) |
EPWM_T::FDEN: FDCKS4 Position
Definition at line 3478 of file epwm_reg.h.
| #define EPWM_FDEN_FDCKS5_Msk (0x1ul << EPWM_FDEN_FDCKS5_Pos) |
EPWM_T::FDEN: FDCKS5 Mask
Definition at line 3482 of file epwm_reg.h.
| #define EPWM_FDEN_FDCKS5_Pos (21) |
EPWM_T::FDEN: FDCKS5 Position
Definition at line 3481 of file epwm_reg.h.
| #define EPWM_FDEN_FDEN0_Msk (0x1ul << EPWM_FDEN_FDEN0_Pos) |
EPWM_T::FDEN: FDEN0 Mask
Definition at line 3431 of file epwm_reg.h.
| #define EPWM_FDEN_FDEN0_Pos (0) |
EPWM_T::FDEN: FDEN0 Position
Definition at line 3430 of file epwm_reg.h.
| #define EPWM_FDEN_FDEN1_Msk (0x1ul << EPWM_FDEN_FDEN1_Pos) |
EPWM_T::FDEN: FDEN1 Mask
Definition at line 3434 of file epwm_reg.h.
| #define EPWM_FDEN_FDEN1_Pos (1) |
EPWM_T::FDEN: FDEN1 Position
Definition at line 3433 of file epwm_reg.h.
| #define EPWM_FDEN_FDEN2_Msk (0x1ul << EPWM_FDEN_FDEN2_Pos) |
EPWM_T::FDEN: FDEN2 Mask
Definition at line 3437 of file epwm_reg.h.
| #define EPWM_FDEN_FDEN2_Pos (2) |
EPWM_T::FDEN: FDEN2 Position
Definition at line 3436 of file epwm_reg.h.
| #define EPWM_FDEN_FDEN3_Msk (0x1ul << EPWM_FDEN_FDEN3_Pos) |
EPWM_T::FDEN: FDEN3 Mask
Definition at line 3440 of file epwm_reg.h.
| #define EPWM_FDEN_FDEN3_Pos (3) |
EPWM_T::FDEN: FDEN3 Position
Definition at line 3439 of file epwm_reg.h.
| #define EPWM_FDEN_FDEN4_Msk (0x1ul << EPWM_FDEN_FDEN4_Pos) |
EPWM_T::FDEN: FDEN4 Mask
Definition at line 3443 of file epwm_reg.h.
| #define EPWM_FDEN_FDEN4_Pos (4) |
EPWM_T::FDEN: FDEN4 Position
Definition at line 3442 of file epwm_reg.h.
| #define EPWM_FDEN_FDEN5_Msk (0x1ul << EPWM_FDEN_FDEN5_Pos) |
EPWM_T::FDEN: FDEN5 Mask
Definition at line 3446 of file epwm_reg.h.
| #define EPWM_FDEN_FDEN5_Pos (5) |
EPWM_T::FDEN: FDEN5 Position
Definition at line 3445 of file epwm_reg.h.
| #define EPWM_FDEN_FDODIS0_Msk (0x1ul << EPWM_FDEN_FDODIS0_Pos) |
EPWM_T::FDEN: FDODIS0 Mask
Definition at line 3449 of file epwm_reg.h.
| #define EPWM_FDEN_FDODIS0_Pos (8) |
EPWM_T::FDEN: FDODIS0 Position
Definition at line 3448 of file epwm_reg.h.
| #define EPWM_FDEN_FDODIS1_Msk (0x1ul << EPWM_FDEN_FDODIS1_Pos) |
EPWM_T::FDEN: FDODIS1 Mask
Definition at line 3452 of file epwm_reg.h.
| #define EPWM_FDEN_FDODIS1_Pos (9) |
EPWM_T::FDEN: FDODIS1 Position
Definition at line 3451 of file epwm_reg.h.
| #define EPWM_FDEN_FDODIS2_Msk (0x1ul << EPWM_FDEN_FDODIS2_Pos) |
EPWM_T::FDEN: FDODIS2 Mask
Definition at line 3455 of file epwm_reg.h.
| #define EPWM_FDEN_FDODIS2_Pos (10) |
EPWM_T::FDEN: FDODIS2 Position
Definition at line 3454 of file epwm_reg.h.
| #define EPWM_FDEN_FDODIS3_Msk (0x1ul << EPWM_FDEN_FDODIS3_Pos) |
EPWM_T::FDEN: FDODIS3 Mask
Definition at line 3458 of file epwm_reg.h.
| #define EPWM_FDEN_FDODIS3_Pos (11) |
EPWM_T::FDEN: FDODIS3 Position
Definition at line 3457 of file epwm_reg.h.
| #define EPWM_FDEN_FDODIS4_Msk (0x1ul << EPWM_FDEN_FDODIS4_Pos) |
EPWM_T::FDEN: FDODIS4 Mask
Definition at line 3461 of file epwm_reg.h.
| #define EPWM_FDEN_FDODIS4_Pos (12) |
EPWM_T::FDEN: FDODIS4 Position
Definition at line 3460 of file epwm_reg.h.
| #define EPWM_FDEN_FDODIS5_Msk (0x1ul << EPWM_FDEN_FDODIS5_Pos) |
EPWM_T::FDEN: FDODIS5 Mask
Definition at line 3464 of file epwm_reg.h.
| #define EPWM_FDEN_FDODIS5_Pos (13) |
EPWM_T::FDEN: FDODIS5 Position
Definition at line 3463 of file epwm_reg.h.
| #define EPWM_FDIEN_FDIEN0_Msk (0x1ul << EPWM_FDIEN_FDIEN0_Pos) |
EPWM_T::FDIEN: FDIEN0 Mask
Definition at line 3575 of file epwm_reg.h.
| #define EPWM_FDIEN_FDIEN0_Pos (0) |
EPWM_T::FDIEN: FDIEN0 Position
Definition at line 3574 of file epwm_reg.h.
| #define EPWM_FDIEN_FDIEN1_Msk (0x1ul << EPWM_FDIEN_FDIEN1_Pos) |
EPWM_T::FDIEN: FDIEN1 Mask
Definition at line 3578 of file epwm_reg.h.
| #define EPWM_FDIEN_FDIEN1_Pos (1) |
EPWM_T::FDIEN: FDIEN1 Position
Definition at line 3577 of file epwm_reg.h.
| #define EPWM_FDIEN_FDIEN2_Msk (0x1ul << EPWM_FDIEN_FDIEN2_Pos) |
EPWM_T::FDIEN: FDIEN2 Mask
Definition at line 3581 of file epwm_reg.h.
| #define EPWM_FDIEN_FDIEN2_Pos (2) |
EPWM_T::FDIEN: FDIEN2 Position
Definition at line 3580 of file epwm_reg.h.
| #define EPWM_FDIEN_FDIEN3_Msk (0x1ul << EPWM_FDIEN_FDIEN3_Pos) |
EPWM_T::FDIEN: FDIEN3 Mask
Definition at line 3584 of file epwm_reg.h.
| #define EPWM_FDIEN_FDIEN3_Pos (3) |
EPWM_T::FDIEN: FDIEN3 Position
Definition at line 3583 of file epwm_reg.h.
| #define EPWM_FDIEN_FDIEN4_Msk (0x1ul << EPWM_FDIEN_FDIEN4_Pos) |
EPWM_T::FDIEN: FDIEN4 Mask
Definition at line 3587 of file epwm_reg.h.
| #define EPWM_FDIEN_FDIEN4_Pos (4) |
EPWM_T::FDIEN: FDIEN4 Position
Definition at line 3586 of file epwm_reg.h.
| #define EPWM_FDIEN_FDIEN5_Msk (0x1ul << EPWM_FDIEN_FDIEN5_Pos) |
EPWM_T::FDIEN: FDIEN5 Mask
Definition at line 3590 of file epwm_reg.h.
| #define EPWM_FDIEN_FDIEN5_Pos (5) |
EPWM_T::FDIEN: FDIEN5 Position
Definition at line 3589 of file epwm_reg.h.
| #define EPWM_FDSTS_FDIF0_Msk (0x1ul << EPWM_FDSTS_FDIF0_Pos) |
EPWM_T::FDSTS: FDIF0 Mask
Definition at line 3593 of file epwm_reg.h.
| #define EPWM_FDSTS_FDIF0_Pos (0) |
EPWM_T::FDSTS: FDIF0 Position
Definition at line 3592 of file epwm_reg.h.
| #define EPWM_FDSTS_FDIF1_Msk (0x1ul << EPWM_FDSTS_FDIF1_Pos) |
EPWM_T::FDSTS: FDIF1 Mask
Definition at line 3596 of file epwm_reg.h.
| #define EPWM_FDSTS_FDIF1_Pos (1) |
EPWM_T::FDSTS: FDIF1 Position
Definition at line 3595 of file epwm_reg.h.
| #define EPWM_FDSTS_FDIF2_Msk (0x1ul << EPWM_FDSTS_FDIF2_Pos) |
EPWM_T::FDSTS: FDIF2 Mask
Definition at line 3599 of file epwm_reg.h.
| #define EPWM_FDSTS_FDIF2_Pos (2) |
EPWM_T::FDSTS: FDIF2 Position
Definition at line 3598 of file epwm_reg.h.
| #define EPWM_FDSTS_FDIF3_Msk (0x1ul << EPWM_FDSTS_FDIF3_Pos) |
EPWM_T::FDSTS: FDIF3 Mask
Definition at line 3602 of file epwm_reg.h.
| #define EPWM_FDSTS_FDIF3_Pos (3) |
EPWM_T::FDSTS: FDIF3 Position
Definition at line 3601 of file epwm_reg.h.
| #define EPWM_FDSTS_FDIF4_Msk (0x1ul << EPWM_FDSTS_FDIF4_Pos) |
EPWM_T::FDSTS: FDIF4 Mask
Definition at line 3605 of file epwm_reg.h.
| #define EPWM_FDSTS_FDIF4_Pos (4) |
EPWM_T::FDSTS: FDIF4 Position
Definition at line 3604 of file epwm_reg.h.
| #define EPWM_FDSTS_FDIF5_Msk (0x1ul << EPWM_FDSTS_FDIF5_Pos) |
EPWM_T::FDSTS: FDIF5 Mask
Definition at line 3608 of file epwm_reg.h.
| #define EPWM_FDSTS_FDIF5_Pos (5) |
EPWM_T::FDSTS: FDIF5 Position
Definition at line 3607 of file epwm_reg.h.
| #define EPWM_FTCBUF0_1_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF0_1_FTCMPBUF_Pos) |
EPWM_T::FTCBUF0_1: FTCMPBUF Mask
Definition at line 3989 of file epwm_reg.h.
| #define EPWM_FTCBUF0_1_FTCMPBUF_Pos (0) |
EPWM_T::FTCBUF0_1: FTCMPBUF Position
Definition at line 3988 of file epwm_reg.h.
| #define EPWM_FTCBUF2_3_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF2_3_FTCMPBUF_Pos) |
EPWM_T::FTCBUF2_3: FTCMPBUF Mask
Definition at line 3992 of file epwm_reg.h.
| #define EPWM_FTCBUF2_3_FTCMPBUF_Pos (0) |
EPWM_T::FTCBUF2_3: FTCMPBUF Position
Definition at line 3991 of file epwm_reg.h.
| #define EPWM_FTCBUF4_5_FTCMPBUF_Msk (0xfffful << EPWM_FTCBUF4_5_FTCMPBUF_Pos) |
EPWM_T::FTCBUF4_5: FTCMPBUF Mask
Definition at line 3995 of file epwm_reg.h.
| #define EPWM_FTCBUF4_5_FTCMPBUF_Pos (0) |
EPWM_T::FTCBUF4_5: FTCMPBUF Position
Definition at line 3994 of file epwm_reg.h.
| #define EPWM_FTCI_FTCMD0_Msk (0x1ul << EPWM_FTCI_FTCMD0_Pos) |
EPWM_T::FTCI: FTCMD0 Mask
Definition at line 4007 of file epwm_reg.h.
| #define EPWM_FTCI_FTCMD0_Pos (8) |
EPWM_T::FTCI: FTCMD0 Position
Definition at line 4006 of file epwm_reg.h.
| #define EPWM_FTCI_FTCMD2_Msk (0x1ul << EPWM_FTCI_FTCMD2_Pos) |
EPWM_T::FTCI: FTCMD2 Mask
Definition at line 4010 of file epwm_reg.h.
| #define EPWM_FTCI_FTCMD2_Pos (9) |
EPWM_T::FTCI: FTCMD2 Position
Definition at line 4009 of file epwm_reg.h.
| #define EPWM_FTCI_FTCMD4_Msk (0x1ul << EPWM_FTCI_FTCMD4_Pos) |
EPWM_T::FTCI: FTCMD4 Mask
Definition at line 4013 of file epwm_reg.h.
| #define EPWM_FTCI_FTCMD4_Pos (10) |
EPWM_T::FTCI: FTCMD4 Position
Definition at line 4012 of file epwm_reg.h.
| #define EPWM_FTCI_FTCMU0_Msk (0x1ul << EPWM_FTCI_FTCMU0_Pos) |
EPWM_T::FTCI: FTCMU0 Mask
Definition at line 3998 of file epwm_reg.h.
| #define EPWM_FTCI_FTCMU0_Pos (0) |
EPWM_T::FTCI: FTCMU0 Position
Definition at line 3997 of file epwm_reg.h.
| #define EPWM_FTCI_FTCMU2_Msk (0x1ul << EPWM_FTCI_FTCMU2_Pos) |
EPWM_T::FTCI: FTCMU2 Mask
Definition at line 4001 of file epwm_reg.h.
| #define EPWM_FTCI_FTCMU2_Pos (1) |
EPWM_T::FTCI: FTCMU2 Position
Definition at line 4000 of file epwm_reg.h.
| #define EPWM_FTCI_FTCMU4_Msk (0x1ul << EPWM_FTCI_FTCMU4_Pos) |
EPWM_T::FTCI: FTCMU4 Mask
Definition at line 4004 of file epwm_reg.h.
| #define EPWM_FTCI_FTCMU4_Pos (2) |
EPWM_T::FTCI: FTCMU4 Position
Definition at line 4003 of file epwm_reg.h.
| #define EPWM_FTCMPDAT0_1_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT0_1_FTCMP_Pos) |
EPWM_T::FTCMPDAT0_1: FTCMP Mask
Definition at line 3206 of file epwm_reg.h.
| #define EPWM_FTCMPDAT0_1_FTCMP_Pos (0) |
EPWM_T::FTCMPDAT0_1: FTCMP Position
Definition at line 3205 of file epwm_reg.h.
| #define EPWM_FTCMPDAT2_3_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT2_3_FTCMP_Pos) |
EPWM_T::FTCMPDAT2_3: FTCMP Mask
Definition at line 3209 of file epwm_reg.h.
| #define EPWM_FTCMPDAT2_3_FTCMP_Pos (0) |
EPWM_T::FTCMPDAT2_3: FTCMP Position
Definition at line 3208 of file epwm_reg.h.
| #define EPWM_FTCMPDAT4_5_FTCMP_Msk (0xfffful << EPWM_FTCMPDAT4_5_FTCMP_Pos) |
EPWM_T::FTCMPDAT4_5: FTCMP Mask
Definition at line 3212 of file epwm_reg.h.
| #define EPWM_FTCMPDAT4_5_FTCMP_Pos (0) |
EPWM_T::FTCMPDAT4_5: FTCMP Position
Definition at line 3211 of file epwm_reg.h.
| #define EPWM_IFA0_IFACNT_Msk (0xfffful << EPWM_IFA0_IFACNT_Pos) |
EPWM_T::IFA0: IFACNT Mask
Definition at line 3305 of file epwm_reg.h.
| #define EPWM_IFA0_IFACNT_Pos (0) |
EPWM_T::IFA0: IFACNT Position
Definition at line 3304 of file epwm_reg.h.
| #define EPWM_IFA0_IFAEN_Msk (0x1ul << EPWM_IFA0_IFAEN_Pos) |
EPWM_T::IFA0: IFAEN Mask
Definition at line 3314 of file epwm_reg.h.
| #define EPWM_IFA0_IFAEN_Pos (31) |
EPWM_T::IFA0: IFAEN Position
Definition at line 3313 of file epwm_reg.h.
| #define EPWM_IFA0_IFASEL_Msk (0x3ul << EPWM_IFA0_IFASEL_Pos) |
EPWM_T::IFA0: IFASEL Mask
Definition at line 3311 of file epwm_reg.h.
| #define EPWM_IFA0_IFASEL_Pos (28) |
EPWM_T::IFA0: IFASEL Position
Definition at line 3310 of file epwm_reg.h.
| #define EPWM_IFA0_STPMOD_Msk (0x1ul << EPWM_IFA0_STPMOD_Pos) |
EPWM_T::IFA0: STPMOD Mask
Definition at line 3308 of file epwm_reg.h.
| #define EPWM_IFA0_STPMOD_Pos (24) |
EPWM_T::IFA0: STPMOD Position
Definition at line 3307 of file epwm_reg.h.
| #define EPWM_IFA1_IFACNT_Msk (0xfffful << EPWM_IFA1_IFACNT_Pos) |
EPWM_T::IFA1: IFACNT Mask
Definition at line 3317 of file epwm_reg.h.
| #define EPWM_IFA1_IFACNT_Pos (0) |
EPWM_T::IFA1: IFACNT Position
Definition at line 3316 of file epwm_reg.h.
| #define EPWM_IFA1_IFAEN_Msk (0x1ul << EPWM_IFA1_IFAEN_Pos) |
EPWM_T::IFA1: IFAEN Mask
Definition at line 3326 of file epwm_reg.h.
| #define EPWM_IFA1_IFAEN_Pos (31) |
EPWM_T::IFA1: IFAEN Position
Definition at line 3325 of file epwm_reg.h.
| #define EPWM_IFA1_IFASEL_Msk (0x3ul << EPWM_IFA1_IFASEL_Pos) |
EPWM_T::IFA1: IFASEL Mask
Definition at line 3323 of file epwm_reg.h.
| #define EPWM_IFA1_IFASEL_Pos (28) |
EPWM_T::IFA1: IFASEL Position
Definition at line 3322 of file epwm_reg.h.
| #define EPWM_IFA1_STPMOD_Msk (0x1ul << EPWM_IFA1_STPMOD_Pos) |
EPWM_T::IFA1: STPMOD Mask
Definition at line 3320 of file epwm_reg.h.
| #define EPWM_IFA1_STPMOD_Pos (24) |
EPWM_T::IFA1: STPMOD Position
Definition at line 3319 of file epwm_reg.h.
| #define EPWM_IFA2_IFACNT_Msk (0xfffful << EPWM_IFA2_IFACNT_Pos) |
EPWM_T::IFA2: IFACNT Mask
Definition at line 3329 of file epwm_reg.h.
| #define EPWM_IFA2_IFACNT_Pos (0) |
EPWM_T::IFA2: IFACNT Position
Definition at line 3328 of file epwm_reg.h.
| #define EPWM_IFA2_IFAEN_Msk (0x1ul << EPWM_IFA2_IFAEN_Pos) |
EPWM_T::IFA2: IFAEN Mask
Definition at line 3338 of file epwm_reg.h.
| #define EPWM_IFA2_IFAEN_Pos (31) |
EPWM_T::IFA2: IFAEN Position
Definition at line 3337 of file epwm_reg.h.
| #define EPWM_IFA2_IFASEL_Msk (0x3ul << EPWM_IFA2_IFASEL_Pos) |
EPWM_T::IFA2: IFASEL Mask
Definition at line 3335 of file epwm_reg.h.
| #define EPWM_IFA2_IFASEL_Pos (28) |
EPWM_T::IFA2: IFASEL Position
Definition at line 3334 of file epwm_reg.h.
| #define EPWM_IFA2_STPMOD_Msk (0x1ul << EPWM_IFA2_STPMOD_Pos) |
EPWM_T::IFA2: STPMOD Mask
Definition at line 3332 of file epwm_reg.h.
| #define EPWM_IFA2_STPMOD_Pos (24) |
EPWM_T::IFA2: STPMOD Position
Definition at line 3331 of file epwm_reg.h.
| #define EPWM_IFA3_IFACNT_Msk (0xfffful << EPWM_IFA3_IFACNT_Pos) |
EPWM_T::IFA3: IFACNT Mask
Definition at line 3341 of file epwm_reg.h.
| #define EPWM_IFA3_IFACNT_Pos (0) |
EPWM_T::IFA3: IFACNT Position
Definition at line 3340 of file epwm_reg.h.
| #define EPWM_IFA3_IFAEN_Msk (0x1ul << EPWM_IFA3_IFAEN_Pos) |
EPWM_T::IFA3: IFAEN Mask
Definition at line 3350 of file epwm_reg.h.
| #define EPWM_IFA3_IFAEN_Pos (31) |
EPWM_T::IFA3: IFAEN Position
Definition at line 3349 of file epwm_reg.h.
| #define EPWM_IFA3_IFASEL_Msk (0x3ul << EPWM_IFA3_IFASEL_Pos) |
EPWM_T::IFA3: IFASEL Mask
Definition at line 3347 of file epwm_reg.h.
| #define EPWM_IFA3_IFASEL_Pos (28) |
EPWM_T::IFA3: IFASEL Position
Definition at line 3346 of file epwm_reg.h.
| #define EPWM_IFA3_STPMOD_Msk (0x1ul << EPWM_IFA3_STPMOD_Pos) |
EPWM_T::IFA3: STPMOD Mask
Definition at line 3344 of file epwm_reg.h.
| #define EPWM_IFA3_STPMOD_Pos (24) |
EPWM_T::IFA3: STPMOD Position
Definition at line 3343 of file epwm_reg.h.
| #define EPWM_IFA4_IFACNT_Msk (0xfffful << EPWM_IFA4_IFACNT_Pos) |
EPWM_T::IFA4: IFACNT Mask
Definition at line 3353 of file epwm_reg.h.
| #define EPWM_IFA4_IFACNT_Pos (0) |
EPWM_T::IFA4: IFACNT Position
Definition at line 3352 of file epwm_reg.h.
| #define EPWM_IFA4_IFAEN_Msk (0x1ul << EPWM_IFA4_IFAEN_Pos) |
EPWM_T::IFA4: IFAEN Mask
Definition at line 3362 of file epwm_reg.h.
| #define EPWM_IFA4_IFAEN_Pos (31) |
EPWM_T::IFA4: IFAEN Position
Definition at line 3361 of file epwm_reg.h.
| #define EPWM_IFA4_IFASEL_Msk (0x3ul << EPWM_IFA4_IFASEL_Pos) |
EPWM_T::IFA4: IFASEL Mask
Definition at line 3359 of file epwm_reg.h.
| #define EPWM_IFA4_IFASEL_Pos (28) |
EPWM_T::IFA4: IFASEL Position
Definition at line 3358 of file epwm_reg.h.
| #define EPWM_IFA4_STPMOD_Msk (0x1ul << EPWM_IFA4_STPMOD_Pos) |
EPWM_T::IFA4: STPMOD Mask
Definition at line 3356 of file epwm_reg.h.
| #define EPWM_IFA4_STPMOD_Pos (24) |
EPWM_T::IFA4: STPMOD Position
Definition at line 3355 of file epwm_reg.h.
| #define EPWM_IFA5_IFACNT_Msk (0xfffful << EPWM_IFA5_IFACNT_Pos) |
EPWM_T::IFA5: IFACNT Mask
Definition at line 3365 of file epwm_reg.h.
| #define EPWM_IFA5_IFACNT_Pos (0) |
EPWM_T::IFA5: IFACNT Position
Definition at line 3364 of file epwm_reg.h.
| #define EPWM_IFA5_IFAEN_Msk (0x1ul << EPWM_IFA5_IFAEN_Pos) |
EPWM_T::IFA5: IFAEN Mask
Definition at line 3374 of file epwm_reg.h.
| #define EPWM_IFA5_IFAEN_Pos (31) |
EPWM_T::IFA5: IFAEN Position
Definition at line 3373 of file epwm_reg.h.
| #define EPWM_IFA5_IFASEL_Msk (0x3ul << EPWM_IFA5_IFASEL_Pos) |
EPWM_T::IFA5: IFASEL Mask
Definition at line 3371 of file epwm_reg.h.
| #define EPWM_IFA5_IFASEL_Pos (28) |
EPWM_T::IFA5: IFASEL Position
Definition at line 3370 of file epwm_reg.h.
| #define EPWM_IFA5_STPMOD_Msk (0x1ul << EPWM_IFA5_STPMOD_Pos) |
EPWM_T::IFA5: STPMOD Mask
Definition at line 3368 of file epwm_reg.h.
| #define EPWM_IFA5_STPMOD_Pos (24) |
EPWM_T::IFA5: STPMOD Position
Definition at line 3367 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPDIEN0_Msk (0x1ul << EPWM_INTEN0_CMPDIEN0_Pos) |
EPWM_T::INTEN0: CMPDIEN0 Mask
Definition at line 2918 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPDIEN0_Pos (24) |
EPWM_T::INTEN0: CMPDIEN0 Position
Definition at line 2917 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPDIEN1_Msk (0x1ul << EPWM_INTEN0_CMPDIEN1_Pos) |
EPWM_T::INTEN0: CMPDIEN1 Mask
Definition at line 2921 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPDIEN1_Pos (25) |
EPWM_T::INTEN0: CMPDIEN1 Position
Definition at line 2920 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPDIEN2_Msk (0x1ul << EPWM_INTEN0_CMPDIEN2_Pos) |
EPWM_T::INTEN0: CMPDIEN2 Mask
Definition at line 2924 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPDIEN2_Pos (26) |
EPWM_T::INTEN0: CMPDIEN2 Position
Definition at line 2923 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPDIEN3_Msk (0x1ul << EPWM_INTEN0_CMPDIEN3_Pos) |
EPWM_T::INTEN0: CMPDIEN3 Mask
Definition at line 2927 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPDIEN3_Pos (27) |
EPWM_T::INTEN0: CMPDIEN3 Position
Definition at line 2926 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPDIEN4_Msk (0x1ul << EPWM_INTEN0_CMPDIEN4_Pos) |
EPWM_T::INTEN0: CMPDIEN4 Mask
Definition at line 2930 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPDIEN4_Pos (28) |
EPWM_T::INTEN0: CMPDIEN4 Position
Definition at line 2929 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPDIEN5_Msk (0x1ul << EPWM_INTEN0_CMPDIEN5_Pos) |
EPWM_T::INTEN0: CMPDIEN5 Mask
Definition at line 2933 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPDIEN5_Pos (29) |
EPWM_T::INTEN0: CMPDIEN5 Position
Definition at line 2932 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPUIEN0_Msk (0x1ul << EPWM_INTEN0_CMPUIEN0_Pos) |
EPWM_T::INTEN0: CMPUIEN0 Mask
Definition at line 2900 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPUIEN0_Pos (16) |
EPWM_T::INTEN0: CMPUIEN0 Position
Definition at line 2899 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPUIEN1_Msk (0x1ul << EPWM_INTEN0_CMPUIEN1_Pos) |
EPWM_T::INTEN0: CMPUIEN1 Mask
Definition at line 2903 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPUIEN1_Pos (17) |
EPWM_T::INTEN0: CMPUIEN1 Position
Definition at line 2902 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPUIEN2_Msk (0x1ul << EPWM_INTEN0_CMPUIEN2_Pos) |
EPWM_T::INTEN0: CMPUIEN2 Mask
Definition at line 2906 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPUIEN2_Pos (18) |
EPWM_T::INTEN0: CMPUIEN2 Position
Definition at line 2905 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPUIEN3_Msk (0x1ul << EPWM_INTEN0_CMPUIEN3_Pos) |
EPWM_T::INTEN0: CMPUIEN3 Mask
Definition at line 2909 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPUIEN3_Pos (19) |
EPWM_T::INTEN0: CMPUIEN3 Position
Definition at line 2908 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPUIEN4_Msk (0x1ul << EPWM_INTEN0_CMPUIEN4_Pos) |
EPWM_T::INTEN0: CMPUIEN4 Mask
Definition at line 2912 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPUIEN4_Pos (20) |
EPWM_T::INTEN0: CMPUIEN4 Position
Definition at line 2911 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPUIEN5_Msk (0x1ul << EPWM_INTEN0_CMPUIEN5_Pos) |
EPWM_T::INTEN0: CMPUIEN5 Mask
Definition at line 2915 of file epwm_reg.h.
| #define EPWM_INTEN0_CMPUIEN5_Pos (21) |
EPWM_T::INTEN0: CMPUIEN5 Position
Definition at line 2914 of file epwm_reg.h.
| #define EPWM_INTEN0_PIEN0_Msk (0x1ul << EPWM_INTEN0_PIEN0_Pos) |
EPWM_T::INTEN0: PIEN0 Mask
Definition at line 2882 of file epwm_reg.h.
| #define EPWM_INTEN0_PIEN0_Pos (8) |
EPWM_T::INTEN0: PIEN0 Position
Definition at line 2881 of file epwm_reg.h.
| #define EPWM_INTEN0_PIEN1_Msk (0x1ul << EPWM_INTEN0_PIEN1_Pos) |
EPWM_T::INTEN0: PIEN1 Mask
Definition at line 2885 of file epwm_reg.h.
| #define EPWM_INTEN0_PIEN1_Pos (9) |
EPWM_T::INTEN0: PIEN1 Position
Definition at line 2884 of file epwm_reg.h.
| #define EPWM_INTEN0_PIEN2_Msk (0x1ul << EPWM_INTEN0_PIEN2_Pos) |
EPWM_T::INTEN0: PIEN2 Mask
Definition at line 2888 of file epwm_reg.h.
| #define EPWM_INTEN0_PIEN2_Pos (10) |
EPWM_T::INTEN0: PIEN2 Position
Definition at line 2887 of file epwm_reg.h.
| #define EPWM_INTEN0_PIEN3_Msk (0x1ul << EPWM_INTEN0_PIEN3_Pos) |
EPWM_T::INTEN0: PIEN3 Mask
Definition at line 2891 of file epwm_reg.h.
| #define EPWM_INTEN0_PIEN3_Pos (11) |
EPWM_T::INTEN0: PIEN3 Position
Definition at line 2890 of file epwm_reg.h.
| #define EPWM_INTEN0_PIEN4_Msk (0x1ul << EPWM_INTEN0_PIEN4_Pos) |
EPWM_T::INTEN0: PIEN4 Mask
Definition at line 2894 of file epwm_reg.h.
| #define EPWM_INTEN0_PIEN4_Pos (12) |
EPWM_T::INTEN0: PIEN4 Position
Definition at line 2893 of file epwm_reg.h.
| #define EPWM_INTEN0_PIEN5_Msk (0x1ul << EPWM_INTEN0_PIEN5_Pos) |
EPWM_T::INTEN0: PIEN5 Mask
Definition at line 2897 of file epwm_reg.h.
| #define EPWM_INTEN0_PIEN5_Pos (13) |
EPWM_T::INTEN0: PIEN5 Position
Definition at line 2896 of file epwm_reg.h.
| #define EPWM_INTEN0_ZIEN0_Msk (0x1ul << EPWM_INTEN0_ZIEN0_Pos) |
EPWM_T::INTEN0: ZIEN0 Mask
Definition at line 2864 of file epwm_reg.h.
| #define EPWM_INTEN0_ZIEN0_Pos (0) |
EPWM_T::INTEN0: ZIEN0 Position
Definition at line 2863 of file epwm_reg.h.
| #define EPWM_INTEN0_ZIEN1_Msk (0x1ul << EPWM_INTEN0_ZIEN1_Pos) |
EPWM_T::INTEN0: ZIEN1 Mask
Definition at line 2867 of file epwm_reg.h.
| #define EPWM_INTEN0_ZIEN1_Pos (1) |
EPWM_T::INTEN0: ZIEN1 Position
Definition at line 2866 of file epwm_reg.h.
| #define EPWM_INTEN0_ZIEN2_Msk (0x1ul << EPWM_INTEN0_ZIEN2_Pos) |
EPWM_T::INTEN0: ZIEN2 Mask
Definition at line 2870 of file epwm_reg.h.
| #define EPWM_INTEN0_ZIEN2_Pos (2) |
EPWM_T::INTEN0: ZIEN2 Position
Definition at line 2869 of file epwm_reg.h.
| #define EPWM_INTEN0_ZIEN3_Msk (0x1ul << EPWM_INTEN0_ZIEN3_Pos) |
EPWM_T::INTEN0: ZIEN3 Mask
Definition at line 2873 of file epwm_reg.h.
| #define EPWM_INTEN0_ZIEN3_Pos (3) |
EPWM_T::INTEN0: ZIEN3 Position
Definition at line 2872 of file epwm_reg.h.
| #define EPWM_INTEN0_ZIEN4_Msk (0x1ul << EPWM_INTEN0_ZIEN4_Pos) |
EPWM_T::INTEN0: ZIEN4 Mask
Definition at line 2876 of file epwm_reg.h.
| #define EPWM_INTEN0_ZIEN4_Pos (4) |
EPWM_T::INTEN0: ZIEN4 Position
Definition at line 2875 of file epwm_reg.h.
| #define EPWM_INTEN0_ZIEN5_Msk (0x1ul << EPWM_INTEN0_ZIEN5_Pos) |
EPWM_T::INTEN0: ZIEN5 Mask
Definition at line 2879 of file epwm_reg.h.
| #define EPWM_INTEN0_ZIEN5_Pos (5) |
EPWM_T::INTEN0: ZIEN5 Position
Definition at line 2878 of file epwm_reg.h.
| #define EPWM_INTEN1_BRKEIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKEIEN0_1_Pos) |
EPWM_T::INTEN1: BRKEIEN0_1 Mask
Definition at line 2936 of file epwm_reg.h.
| #define EPWM_INTEN1_BRKEIEN0_1_Pos (0) |
EPWM_T::INTEN1: BRKEIEN0_1 Position
Definition at line 2935 of file epwm_reg.h.
| #define EPWM_INTEN1_BRKEIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKEIEN2_3_Pos) |
EPWM_T::INTEN1: BRKEIEN2_3 Mask
Definition at line 2939 of file epwm_reg.h.
| #define EPWM_INTEN1_BRKEIEN2_3_Pos (1) |
EPWM_T::INTEN1: BRKEIEN2_3 Position
Definition at line 2938 of file epwm_reg.h.
| #define EPWM_INTEN1_BRKEIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKEIEN4_5_Pos) |
EPWM_T::INTEN1: BRKEIEN4_5 Mask
Definition at line 2942 of file epwm_reg.h.
| #define EPWM_INTEN1_BRKEIEN4_5_Pos (2) |
EPWM_T::INTEN1: BRKEIEN4_5 Position
Definition at line 2941 of file epwm_reg.h.
| #define EPWM_INTEN1_BRKLIEN0_1_Msk (0x1ul << EPWM_INTEN1_BRKLIEN0_1_Pos) |
EPWM_T::INTEN1: BRKLIEN0_1 Mask
Definition at line 2945 of file epwm_reg.h.
| #define EPWM_INTEN1_BRKLIEN0_1_Pos (8) |
EPWM_T::INTEN1: BRKLIEN0_1 Position
Definition at line 2944 of file epwm_reg.h.
| #define EPWM_INTEN1_BRKLIEN2_3_Msk (0x1ul << EPWM_INTEN1_BRKLIEN2_3_Pos) |
EPWM_T::INTEN1: BRKLIEN2_3 Mask
Definition at line 2948 of file epwm_reg.h.
| #define EPWM_INTEN1_BRKLIEN2_3_Pos (9) |
EPWM_T::INTEN1: BRKLIEN2_3 Position
Definition at line 2947 of file epwm_reg.h.
| #define EPWM_INTEN1_BRKLIEN4_5_Msk (0x1ul << EPWM_INTEN1_BRKLIEN4_5_Pos) |
EPWM_T::INTEN1: BRKLIEN4_5 Mask
Definition at line 2951 of file epwm_reg.h.
| #define EPWM_INTEN1_BRKLIEN4_5_Pos (10) |
EPWM_T::INTEN1: BRKLIEN4_5 Position
Definition at line 2950 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPDIF0_Msk (0x1ul << EPWM_INTSTS0_CMPDIF0_Pos) |
EPWM_T::INTSTS0: CMPDIF0 Mask
Definition at line 3008 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPDIF0_Pos (24) |
EPWM_T::INTSTS0: CMPDIF0 Position
Definition at line 3007 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPDIF1_Msk (0x1ul << EPWM_INTSTS0_CMPDIF1_Pos) |
EPWM_T::INTSTS0: CMPDIF1 Mask
Definition at line 3011 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPDIF1_Pos (25) |
EPWM_T::INTSTS0: CMPDIF1 Position
Definition at line 3010 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPDIF2_Msk (0x1ul << EPWM_INTSTS0_CMPDIF2_Pos) |
EPWM_T::INTSTS0: CMPDIF2 Mask
Definition at line 3014 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPDIF2_Pos (26) |
EPWM_T::INTSTS0: CMPDIF2 Position
Definition at line 3013 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPDIF3_Msk (0x1ul << EPWM_INTSTS0_CMPDIF3_Pos) |
EPWM_T::INTSTS0: CMPDIF3 Mask
Definition at line 3017 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPDIF3_Pos (27) |
EPWM_T::INTSTS0: CMPDIF3 Position
Definition at line 3016 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPDIF4_Msk (0x1ul << EPWM_INTSTS0_CMPDIF4_Pos) |
EPWM_T::INTSTS0: CMPDIF4 Mask
Definition at line 3020 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPDIF4_Pos (28) |
EPWM_T::INTSTS0: CMPDIF4 Position
Definition at line 3019 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPDIF5_Msk (0x1ul << EPWM_INTSTS0_CMPDIF5_Pos) |
EPWM_T::INTSTS0: CMPDIF5 Mask
Definition at line 3023 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPDIF5_Pos (29) |
EPWM_T::INTSTS0: CMPDIF5 Position
Definition at line 3022 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPUIF0_Msk (0x1ul << EPWM_INTSTS0_CMPUIF0_Pos) |
EPWM_T::INTSTS0: CMPUIF0 Mask
Definition at line 2990 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPUIF0_Pos (16) |
EPWM_T::INTSTS0: CMPUIF0 Position
Definition at line 2989 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPUIF1_Msk (0x1ul << EPWM_INTSTS0_CMPUIF1_Pos) |
EPWM_T::INTSTS0: CMPUIF1 Mask
Definition at line 2993 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPUIF1_Pos (17) |
EPWM_T::INTSTS0: CMPUIF1 Position
Definition at line 2992 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPUIF2_Msk (0x1ul << EPWM_INTSTS0_CMPUIF2_Pos) |
EPWM_T::INTSTS0: CMPUIF2 Mask
Definition at line 2996 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPUIF2_Pos (18) |
EPWM_T::INTSTS0: CMPUIF2 Position
Definition at line 2995 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPUIF3_Msk (0x1ul << EPWM_INTSTS0_CMPUIF3_Pos) |
EPWM_T::INTSTS0: CMPUIF3 Mask
Definition at line 2999 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPUIF3_Pos (19) |
EPWM_T::INTSTS0: CMPUIF3 Position
Definition at line 2998 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPUIF4_Msk (0x1ul << EPWM_INTSTS0_CMPUIF4_Pos) |
EPWM_T::INTSTS0: CMPUIF4 Mask
Definition at line 3002 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPUIF4_Pos (20) |
EPWM_T::INTSTS0: CMPUIF4 Position
Definition at line 3001 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPUIF5_Msk (0x1ul << EPWM_INTSTS0_CMPUIF5_Pos) |
EPWM_T::INTSTS0: CMPUIF5 Mask
Definition at line 3005 of file epwm_reg.h.
| #define EPWM_INTSTS0_CMPUIF5_Pos (21) |
EPWM_T::INTSTS0: CMPUIF5 Position
Definition at line 3004 of file epwm_reg.h.
| #define EPWM_INTSTS0_PIF0_Msk (0x1ul << EPWM_INTSTS0_PIF0_Pos) |
EPWM_T::INTSTS0: PIF0 Mask
Definition at line 2972 of file epwm_reg.h.
| #define EPWM_INTSTS0_PIF0_Pos (8) |
EPWM_T::INTSTS0: PIF0 Position
Definition at line 2971 of file epwm_reg.h.
| #define EPWM_INTSTS0_PIF1_Msk (0x1ul << EPWM_INTSTS0_PIF1_Pos) |
EPWM_T::INTSTS0: PIF1 Mask
Definition at line 2975 of file epwm_reg.h.
| #define EPWM_INTSTS0_PIF1_Pos (9) |
EPWM_T::INTSTS0: PIF1 Position
Definition at line 2974 of file epwm_reg.h.
| #define EPWM_INTSTS0_PIF2_Msk (0x1ul << EPWM_INTSTS0_PIF2_Pos) |
EPWM_T::INTSTS0: PIF2 Mask
Definition at line 2978 of file epwm_reg.h.
| #define EPWM_INTSTS0_PIF2_Pos (10) |
EPWM_T::INTSTS0: PIF2 Position
Definition at line 2977 of file epwm_reg.h.
| #define EPWM_INTSTS0_PIF3_Msk (0x1ul << EPWM_INTSTS0_PIF3_Pos) |
EPWM_T::INTSTS0: PIF3 Mask
Definition at line 2981 of file epwm_reg.h.
| #define EPWM_INTSTS0_PIF3_Pos (11) |
EPWM_T::INTSTS0: PIF3 Position
Definition at line 2980 of file epwm_reg.h.
| #define EPWM_INTSTS0_PIF4_Msk (0x1ul << EPWM_INTSTS0_PIF4_Pos) |
EPWM_T::INTSTS0: PIF4 Mask
Definition at line 2984 of file epwm_reg.h.
| #define EPWM_INTSTS0_PIF4_Pos (12) |
EPWM_T::INTSTS0: PIF4 Position
Definition at line 2983 of file epwm_reg.h.
| #define EPWM_INTSTS0_PIF5_Msk (0x1ul << EPWM_INTSTS0_PIF5_Pos) |
EPWM_T::INTSTS0: PIF5 Mask
Definition at line 2987 of file epwm_reg.h.
| #define EPWM_INTSTS0_PIF5_Pos (13) |
EPWM_T::INTSTS0: PIF5 Position
Definition at line 2986 of file epwm_reg.h.
| #define EPWM_INTSTS0_ZIF0_Msk (0x1ul << EPWM_INTSTS0_ZIF0_Pos) |
EPWM_T::INTSTS0: ZIF0 Mask
Definition at line 2954 of file epwm_reg.h.
| #define EPWM_INTSTS0_ZIF0_Pos (0) |
EPWM_T::INTSTS0: ZIF0 Position
Definition at line 2953 of file epwm_reg.h.
| #define EPWM_INTSTS0_ZIF1_Msk (0x1ul << EPWM_INTSTS0_ZIF1_Pos) |
EPWM_T::INTSTS0: ZIF1 Mask
Definition at line 2957 of file epwm_reg.h.
| #define EPWM_INTSTS0_ZIF1_Pos (1) |
EPWM_T::INTSTS0: ZIF1 Position
Definition at line 2956 of file epwm_reg.h.
| #define EPWM_INTSTS0_ZIF2_Msk (0x1ul << EPWM_INTSTS0_ZIF2_Pos) |
EPWM_T::INTSTS0: ZIF2 Mask
Definition at line 2960 of file epwm_reg.h.
| #define EPWM_INTSTS0_ZIF2_Pos (2) |
EPWM_T::INTSTS0: ZIF2 Position
Definition at line 2959 of file epwm_reg.h.
| #define EPWM_INTSTS0_ZIF3_Msk (0x1ul << EPWM_INTSTS0_ZIF3_Pos) |
EPWM_T::INTSTS0: ZIF3 Mask
Definition at line 2963 of file epwm_reg.h.
| #define EPWM_INTSTS0_ZIF3_Pos (3) |
EPWM_T::INTSTS0: ZIF3 Position
Definition at line 2962 of file epwm_reg.h.
| #define EPWM_INTSTS0_ZIF4_Msk (0x1ul << EPWM_INTSTS0_ZIF4_Pos) |
EPWM_T::INTSTS0: ZIF4 Mask
Definition at line 2966 of file epwm_reg.h.
| #define EPWM_INTSTS0_ZIF4_Pos (4) |
EPWM_T::INTSTS0: ZIF4 Position
Definition at line 2965 of file epwm_reg.h.
| #define EPWM_INTSTS0_ZIF5_Msk (0x1ul << EPWM_INTSTS0_ZIF5_Pos) |
EPWM_T::INTSTS0: ZIF5 Mask
Definition at line 2969 of file epwm_reg.h.
| #define EPWM_INTSTS0_ZIF5_Pos (5) |
EPWM_T::INTSTS0: ZIF5 Position
Definition at line 2968 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKEIF0_Msk (0x1ul << EPWM_INTSTS1_BRKEIF0_Pos) |
EPWM_T::INTSTS1: BRKEIF0 Mask
Definition at line 3026 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKEIF0_Pos (0) |
EPWM_T::INTSTS1: BRKEIF0 Position
Definition at line 3025 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKEIF1_Msk (0x1ul << EPWM_INTSTS1_BRKEIF1_Pos) |
EPWM_T::INTSTS1: BRKEIF1 Mask
Definition at line 3029 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKEIF1_Pos (1) |
EPWM_T::INTSTS1: BRKEIF1 Position
Definition at line 3028 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKEIF2_Msk (0x1ul << EPWM_INTSTS1_BRKEIF2_Pos) |
EPWM_T::INTSTS1: BRKEIF2 Mask
Definition at line 3032 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKEIF2_Pos (2) |
EPWM_T::INTSTS1: BRKEIF2 Position
Definition at line 3031 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKEIF3_Msk (0x1ul << EPWM_INTSTS1_BRKEIF3_Pos) |
EPWM_T::INTSTS1: BRKEIF3 Mask
Definition at line 3035 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKEIF3_Pos (3) |
EPWM_T::INTSTS1: BRKEIF3 Position
Definition at line 3034 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKEIF4_Msk (0x1ul << EPWM_INTSTS1_BRKEIF4_Pos) |
EPWM_T::INTSTS1: BRKEIF4 Mask
Definition at line 3038 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKEIF4_Pos (4) |
EPWM_T::INTSTS1: BRKEIF4 Position
Definition at line 3037 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKEIF5_Msk (0x1ul << EPWM_INTSTS1_BRKEIF5_Pos) |
EPWM_T::INTSTS1: BRKEIF5 Mask
Definition at line 3041 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKEIF5_Pos (5) |
EPWM_T::INTSTS1: BRKEIF5 Position
Definition at line 3040 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKESTS0_Msk (0x1ul << EPWM_INTSTS1_BRKESTS0_Pos) |
EPWM_T::INTSTS1: BRKESTS0 Mask
Definition at line 3062 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKESTS0_Pos (16) |
EPWM_T::INTSTS1: BRKESTS0 Position
Definition at line 3061 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKESTS1_Msk (0x1ul << EPWM_INTSTS1_BRKESTS1_Pos) |
EPWM_T::INTSTS1: BRKESTS1 Mask
Definition at line 3065 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKESTS1_Pos (17) |
EPWM_T::INTSTS1: BRKESTS1 Position
Definition at line 3064 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKESTS2_Msk (0x1ul << EPWM_INTSTS1_BRKESTS2_Pos) |
EPWM_T::INTSTS1: BRKESTS2 Mask
Definition at line 3068 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKESTS2_Pos (18) |
EPWM_T::INTSTS1: BRKESTS2 Position
Definition at line 3067 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKESTS3_Msk (0x1ul << EPWM_INTSTS1_BRKESTS3_Pos) |
EPWM_T::INTSTS1: BRKESTS3 Mask
Definition at line 3071 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKESTS3_Pos (19) |
EPWM_T::INTSTS1: BRKESTS3 Position
Definition at line 3070 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKESTS4_Msk (0x1ul << EPWM_INTSTS1_BRKESTS4_Pos) |
EPWM_T::INTSTS1: BRKESTS4 Mask
Definition at line 3074 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKESTS4_Pos (20) |
EPWM_T::INTSTS1: BRKESTS4 Position
Definition at line 3073 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKESTS5_Msk (0x1ul << EPWM_INTSTS1_BRKESTS5_Pos) |
EPWM_T::INTSTS1: BRKESTS5 Mask
Definition at line 3077 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKESTS5_Pos (21) |
EPWM_T::INTSTS1: BRKESTS5 Position
Definition at line 3076 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLIF0_Msk (0x1ul << EPWM_INTSTS1_BRKLIF0_Pos) |
EPWM_T::INTSTS1: BRKLIF0 Mask
Definition at line 3044 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLIF0_Pos (8) |
EPWM_T::INTSTS1: BRKLIF0 Position
Definition at line 3043 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLIF1_Msk (0x1ul << EPWM_INTSTS1_BRKLIF1_Pos) |
EPWM_T::INTSTS1: BRKLIF1 Mask
Definition at line 3047 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLIF1_Pos (9) |
EPWM_T::INTSTS1: BRKLIF1 Position
Definition at line 3046 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLIF2_Msk (0x1ul << EPWM_INTSTS1_BRKLIF2_Pos) |
EPWM_T::INTSTS1: BRKLIF2 Mask
Definition at line 3050 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLIF2_Pos (10) |
EPWM_T::INTSTS1: BRKLIF2 Position
Definition at line 3049 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLIF3_Msk (0x1ul << EPWM_INTSTS1_BRKLIF3_Pos) |
EPWM_T::INTSTS1: BRKLIF3 Mask
Definition at line 3053 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLIF3_Pos (11) |
EPWM_T::INTSTS1: BRKLIF3 Position
Definition at line 3052 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLIF4_Msk (0x1ul << EPWM_INTSTS1_BRKLIF4_Pos) |
EPWM_T::INTSTS1: BRKLIF4 Mask
Definition at line 3056 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLIF4_Pos (12) |
EPWM_T::INTSTS1: BRKLIF4 Position
Definition at line 3055 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLIF5_Msk (0x1ul << EPWM_INTSTS1_BRKLIF5_Pos) |
EPWM_T::INTSTS1: BRKLIF5 Mask
Definition at line 3059 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLIF5_Pos (13) |
EPWM_T::INTSTS1: BRKLIF5 Position
Definition at line 3058 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLSTS0_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS0_Pos) |
EPWM_T::INTSTS1: BRKLSTS0 Mask
Definition at line 3080 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLSTS0_Pos (24) |
EPWM_T::INTSTS1: BRKLSTS0 Position
Definition at line 3079 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLSTS1_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS1_Pos) |
EPWM_T::INTSTS1: BRKLSTS1 Mask
Definition at line 3083 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLSTS1_Pos (25) |
EPWM_T::INTSTS1: BRKLSTS1 Position
Definition at line 3082 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLSTS2_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS2_Pos) |
EPWM_T::INTSTS1: BRKLSTS2 Mask
Definition at line 3086 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLSTS2_Pos (26) |
EPWM_T::INTSTS1: BRKLSTS2 Position
Definition at line 3085 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLSTS3_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS3_Pos) |
EPWM_T::INTSTS1: BRKLSTS3 Mask
Definition at line 3089 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLSTS3_Pos (27) |
EPWM_T::INTSTS1: BRKLSTS3 Position
Definition at line 3088 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLSTS4_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS4_Pos) |
EPWM_T::INTSTS1: BRKLSTS4 Mask
Definition at line 3092 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLSTS4_Pos (28) |
EPWM_T::INTSTS1: BRKLSTS4 Position
Definition at line 3091 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLSTS5_Msk (0x1ul << EPWM_INTSTS1_BRKLSTS5_Pos) |
EPWM_T::INTSTS1: BRKLSTS5 Mask
Definition at line 3095 of file epwm_reg.h.
| #define EPWM_INTSTS1_BRKLSTS5_Pos (29) |
EPWM_T::INTSTS1: BRKLSTS5 Position
Definition at line 3094 of file epwm_reg.h.
| #define EPWM_LEBCNT_LEBCNT_Msk (0x1fful << EPWM_LEBCNT_LEBCNT_Pos) |
EPWM_T::LEBCNT: LEBCNT Mask
Definition at line 3254 of file epwm_reg.h.
| #define EPWM_LEBCNT_LEBCNT_Pos (0) |
EPWM_T::LEBCNT: LEBCNT Position
Definition at line 3253 of file epwm_reg.h.
| #define EPWM_LEBCTL_LEBEN_Msk (0x1ul << EPWM_LEBCTL_LEBEN_Pos) |
EPWM_T::LEBCTL: LEBEN Mask
Definition at line 3239 of file epwm_reg.h.
| #define EPWM_LEBCTL_LEBEN_Pos (0) |
EPWM_T::LEBCTL: LEBEN Position
Definition at line 3238 of file epwm_reg.h.
| #define EPWM_LEBCTL_SRCEN0_Msk (0x1ul << EPWM_LEBCTL_SRCEN0_Pos) |
EPWM_T::LEBCTL: SRCEN0 Mask
Definition at line 3242 of file epwm_reg.h.
| #define EPWM_LEBCTL_SRCEN0_Pos (8) |
EPWM_T::LEBCTL: SRCEN0 Position
Definition at line 3241 of file epwm_reg.h.
| #define EPWM_LEBCTL_SRCEN2_Msk (0x1ul << EPWM_LEBCTL_SRCEN2_Pos) |
EPWM_T::LEBCTL: SRCEN2 Mask
Definition at line 3245 of file epwm_reg.h.
| #define EPWM_LEBCTL_SRCEN2_Pos (9) |
EPWM_T::LEBCTL: SRCEN2 Position
Definition at line 3244 of file epwm_reg.h.
| #define EPWM_LEBCTL_SRCEN4_Msk (0x1ul << EPWM_LEBCTL_SRCEN4_Pos) |
EPWM_T::LEBCTL: SRCEN4 Mask
Definition at line 3248 of file epwm_reg.h.
| #define EPWM_LEBCTL_SRCEN4_Pos (10) |
EPWM_T::LEBCTL: SRCEN4 Position
Definition at line 3247 of file epwm_reg.h.
| #define EPWM_LEBCTL_TRGTYPE_Msk (0x3ul << EPWM_LEBCTL_TRGTYPE_Pos) |
EPWM_T::LEBCTL: TRGTYPE Mask
Definition at line 3251 of file epwm_reg.h.
| #define EPWM_LEBCTL_TRGTYPE_Pos (16) |
EPWM_T::LEBCTL: TRGTYPE Position
Definition at line 3250 of file epwm_reg.h.
| #define EPWM_LOAD_LOAD0_Msk (0x1ul << EPWM_LOAD_LOAD0_Pos) |
EPWM_T::LOAD: LOAD0 Mask
Definition at line 2408 of file epwm_reg.h.
| #define EPWM_LOAD_LOAD0_Pos (0) |
EPWM_T::LOAD: LOAD0 Position
Definition at line 2407 of file epwm_reg.h.
| #define EPWM_LOAD_LOAD1_Msk (0x1ul << EPWM_LOAD_LOAD1_Pos) |
EPWM_T::LOAD: LOAD1 Mask
Definition at line 2411 of file epwm_reg.h.
| #define EPWM_LOAD_LOAD1_Pos (1) |
EPWM_T::LOAD: LOAD1 Position
Definition at line 2410 of file epwm_reg.h.
| #define EPWM_LOAD_LOAD2_Msk (0x1ul << EPWM_LOAD_LOAD2_Pos) |
EPWM_T::LOAD: LOAD2 Mask
Definition at line 2414 of file epwm_reg.h.
| #define EPWM_LOAD_LOAD2_Pos (2) |
EPWM_T::LOAD: LOAD2 Position
Definition at line 2413 of file epwm_reg.h.
| #define EPWM_LOAD_LOAD3_Msk (0x1ul << EPWM_LOAD_LOAD3_Pos) |
EPWM_T::LOAD: LOAD3 Mask
Definition at line 2417 of file epwm_reg.h.
| #define EPWM_LOAD_LOAD3_Pos (3) |
EPWM_T::LOAD: LOAD3 Position
Definition at line 2416 of file epwm_reg.h.
| #define EPWM_LOAD_LOAD4_Msk (0x1ul << EPWM_LOAD_LOAD4_Pos) |
EPWM_T::LOAD: LOAD4 Mask
Definition at line 2420 of file epwm_reg.h.
| #define EPWM_LOAD_LOAD4_Pos (4) |
EPWM_T::LOAD: LOAD4 Position
Definition at line 2419 of file epwm_reg.h.
| #define EPWM_LOAD_LOAD5_Msk (0x1ul << EPWM_LOAD_LOAD5_Pos) |
EPWM_T::LOAD: LOAD5 Mask
Definition at line 2423 of file epwm_reg.h.
| #define EPWM_LOAD_LOAD5_Pos (5) |
EPWM_T::LOAD: LOAD5 Position
Definition at line 2422 of file epwm_reg.h.
| #define EPWM_MSK_MSKDAT0_Msk (0x1ul << EPWM_MSK_MSKDAT0_Pos) |
EPWM_T::MSK: MSKDAT0 Mask
Definition at line 2624 of file epwm_reg.h.
| #define EPWM_MSK_MSKDAT0_Pos (0) |
EPWM_T::MSK: MSKDAT0 Position
Definition at line 2623 of file epwm_reg.h.
| #define EPWM_MSK_MSKDAT1_Msk (0x1ul << EPWM_MSK_MSKDAT1_Pos) |
EPWM_T::MSK: MSKDAT1 Mask
Definition at line 2627 of file epwm_reg.h.
| #define EPWM_MSK_MSKDAT1_Pos (1) |
EPWM_T::MSK: MSKDAT1 Position
Definition at line 2626 of file epwm_reg.h.
| #define EPWM_MSK_MSKDAT2_Msk (0x1ul << EPWM_MSK_MSKDAT2_Pos) |
EPWM_T::MSK: MSKDAT2 Mask
Definition at line 2630 of file epwm_reg.h.
| #define EPWM_MSK_MSKDAT2_Pos (2) |
EPWM_T::MSK: MSKDAT2 Position
Definition at line 2629 of file epwm_reg.h.
| #define EPWM_MSK_MSKDAT3_Msk (0x1ul << EPWM_MSK_MSKDAT3_Pos) |
EPWM_T::MSK: MSKDAT3 Mask
Definition at line 2633 of file epwm_reg.h.
| #define EPWM_MSK_MSKDAT3_Pos (3) |
EPWM_T::MSK: MSKDAT3 Position
Definition at line 2632 of file epwm_reg.h.
| #define EPWM_MSK_MSKDAT4_Msk (0x1ul << EPWM_MSK_MSKDAT4_Pos) |
EPWM_T::MSK: MSKDAT4 Mask
Definition at line 2636 of file epwm_reg.h.
| #define EPWM_MSK_MSKDAT4_Pos (4) |
EPWM_T::MSK: MSKDAT4 Position
Definition at line 2635 of file epwm_reg.h.
| #define EPWM_MSK_MSKDAT5_Msk (0x1ul << EPWM_MSK_MSKDAT5_Pos) |
EPWM_T::MSK: MSKDAT5 Mask
Definition at line 2639 of file epwm_reg.h.
| #define EPWM_MSK_MSKDAT5_Pos (5) |
EPWM_T::MSK: MSKDAT5 Position
Definition at line 2638 of file epwm_reg.h.
| #define EPWM_MSKEN_MSKEN0_Msk (0x1ul << EPWM_MSKEN_MSKEN0_Pos) |
EPWM_T::MSKEN: MSKEN0 Mask
Definition at line 2606 of file epwm_reg.h.
| #define EPWM_MSKEN_MSKEN0_Pos (0) |
EPWM_T::MSKEN: MSKEN0 Position
Definition at line 2605 of file epwm_reg.h.
| #define EPWM_MSKEN_MSKEN1_Msk (0x1ul << EPWM_MSKEN_MSKEN1_Pos) |
EPWM_T::MSKEN: MSKEN1 Mask
Definition at line 2609 of file epwm_reg.h.
| #define EPWM_MSKEN_MSKEN1_Pos (1) |
EPWM_T::MSKEN: MSKEN1 Position
Definition at line 2608 of file epwm_reg.h.
| #define EPWM_MSKEN_MSKEN2_Msk (0x1ul << EPWM_MSKEN_MSKEN2_Pos) |
EPWM_T::MSKEN: MSKEN2 Mask
Definition at line 2612 of file epwm_reg.h.
| #define EPWM_MSKEN_MSKEN2_Pos (2) |
EPWM_T::MSKEN: MSKEN2 Position
Definition at line 2611 of file epwm_reg.h.
| #define EPWM_MSKEN_MSKEN3_Msk (0x1ul << EPWM_MSKEN_MSKEN3_Pos) |
EPWM_T::MSKEN: MSKEN3 Mask
Definition at line 2615 of file epwm_reg.h.
| #define EPWM_MSKEN_MSKEN3_Pos (3) |
EPWM_T::MSKEN: MSKEN3 Position
Definition at line 2614 of file epwm_reg.h.
| #define EPWM_MSKEN_MSKEN4_Msk (0x1ul << EPWM_MSKEN_MSKEN4_Pos) |
EPWM_T::MSKEN: MSKEN4 Mask
Definition at line 2618 of file epwm_reg.h.
| #define EPWM_MSKEN_MSKEN4_Pos (4) |
EPWM_T::MSKEN: MSKEN4 Position
Definition at line 2617 of file epwm_reg.h.
| #define EPWM_MSKEN_MSKEN5_Msk (0x1ul << EPWM_MSKEN_MSKEN5_Pos) |
EPWM_T::MSKEN: MSKEN5 Mask
Definition at line 2621 of file epwm_reg.h.
| #define EPWM_MSKEN_MSKEN5_Pos (5) |
EPWM_T::MSKEN: MSKEN5 Position
Definition at line 2620 of file epwm_reg.h.
| #define EPWM_PBUF0_PBUF_Msk (0xfffful << EPWM_PBUF0_PBUF_Pos) |
EPWM_T::PBUF0: PBUF Mask
Definition at line 3944 of file epwm_reg.h.
| #define EPWM_PBUF0_PBUF_Pos (0) |
EPWM_T::PBUF0: PBUF Position
Definition at line 3943 of file epwm_reg.h.
| #define EPWM_PBUF1_PBUF_Msk (0xfffful << EPWM_PBUF1_PBUF_Pos) |
EPWM_T::PBUF1: PBUF Mask
Definition at line 3947 of file epwm_reg.h.
| #define EPWM_PBUF1_PBUF_Pos (0) |
EPWM_T::PBUF1: PBUF Position
Definition at line 3946 of file epwm_reg.h.
| #define EPWM_PBUF2_PBUF_Msk (0xfffful << EPWM_PBUF2_PBUF_Pos) |
EPWM_T::PBUF2: PBUF Mask
Definition at line 3950 of file epwm_reg.h.
| #define EPWM_PBUF2_PBUF_Pos (0) |
EPWM_T::PBUF2: PBUF Position
Definition at line 3949 of file epwm_reg.h.
| #define EPWM_PBUF3_PBUF_Msk (0xfffful << EPWM_PBUF3_PBUF_Pos) |
EPWM_T::PBUF3: PBUF Mask
Definition at line 3953 of file epwm_reg.h.
| #define EPWM_PBUF3_PBUF_Pos (0) |
EPWM_T::PBUF3: PBUF Position
Definition at line 3952 of file epwm_reg.h.
| #define EPWM_PBUF4_PBUF_Msk (0xfffful << EPWM_PBUF4_PBUF_Pos) |
EPWM_T::PBUF4: PBUF Mask
Definition at line 3956 of file epwm_reg.h.
| #define EPWM_PBUF4_PBUF_Pos (0) |
EPWM_T::PBUF4: PBUF Position
Definition at line 3955 of file epwm_reg.h.
| #define EPWM_PBUF5_PBUF_Msk (0xfffful << EPWM_PBUF5_PBUF_Pos) |
EPWM_T::PBUF5: PBUF Mask
Definition at line 3959 of file epwm_reg.h.
| #define EPWM_PBUF5_PBUF_Pos (0) |
EPWM_T::PBUF5: PBUF Position
Definition at line 3958 of file epwm_reg.h.
| #define EPWM_PDMACAP0_1_CAPBUF_Msk (0xfffful << EPWM_PDMACAP0_1_CAPBUF_Pos) |
EPWM_T::PDMACAP0_1: CAPBUF Mask
Definition at line 3863 of file epwm_reg.h.
| #define EPWM_PDMACAP0_1_CAPBUF_Pos (0) |
EPWM_T::PDMACAP0_1: CAPBUF Position
Definition at line 3862 of file epwm_reg.h.
| #define EPWM_PDMACAP2_3_CAPBUF_Msk (0xfffful << EPWM_PDMACAP2_3_CAPBUF_Pos) |
EPWM_T::PDMACAP2_3: CAPBUF Mask
Definition at line 3866 of file epwm_reg.h.
| #define EPWM_PDMACAP2_3_CAPBUF_Pos (0) |
EPWM_T::PDMACAP2_3: CAPBUF Position
Definition at line 3865 of file epwm_reg.h.
| #define EPWM_PDMACAP4_5_CAPBUF_Msk (0xfffful << EPWM_PDMACAP4_5_CAPBUF_Pos) |
EPWM_T::PDMACAP4_5: CAPBUF Mask
Definition at line 3869 of file epwm_reg.h.
| #define EPWM_PDMACAP4_5_CAPBUF_Pos (0) |
EPWM_T::PDMACAP4_5: CAPBUF Position
Definition at line 3868 of file epwm_reg.h.
| #define EPWM_PDMACTL_CAPMOD0_1_Msk (0x3ul << EPWM_PDMACTL_CAPMOD0_1_Pos) |
EPWM_T::PDMACTL: CAPMOD0_1 Mask
Definition at line 3830 of file epwm_reg.h.
| #define EPWM_PDMACTL_CAPMOD0_1_Pos (1) |
EPWM_T::PDMACTL: CAPMOD0_1 Position
Definition at line 3829 of file epwm_reg.h.
| #define EPWM_PDMACTL_CAPMOD2_3_Msk (0x3ul << EPWM_PDMACTL_CAPMOD2_3_Pos) |
EPWM_T::PDMACTL: CAPMOD2_3 Mask
Definition at line 3842 of file epwm_reg.h.
| #define EPWM_PDMACTL_CAPMOD2_3_Pos (9) |
EPWM_T::PDMACTL: CAPMOD2_3 Position
Definition at line 3841 of file epwm_reg.h.
| #define EPWM_PDMACTL_CAPMOD4_5_Msk (0x3ul << EPWM_PDMACTL_CAPMOD4_5_Pos) |
EPWM_T::PDMACTL: CAPMOD4_5 Mask
Definition at line 3854 of file epwm_reg.h.
| #define EPWM_PDMACTL_CAPMOD4_5_Pos (17) |
EPWM_T::PDMACTL: CAPMOD4_5 Position
Definition at line 3853 of file epwm_reg.h.
| #define EPWM_PDMACTL_CAPORD0_1_Msk (0x1ul << EPWM_PDMACTL_CAPORD0_1_Pos) |
EPWM_T::PDMACTL: CAPORD0_1 Mask
Definition at line 3833 of file epwm_reg.h.
| #define EPWM_PDMACTL_CAPORD0_1_Pos (3) |
EPWM_T::PDMACTL: CAPORD0_1 Position
Definition at line 3832 of file epwm_reg.h.
| #define EPWM_PDMACTL_CAPORD2_3_Msk (0x1ul << EPWM_PDMACTL_CAPORD2_3_Pos) |
EPWM_T::PDMACTL: CAPORD2_3 Mask
Definition at line 3845 of file epwm_reg.h.
| #define EPWM_PDMACTL_CAPORD2_3_Pos (11) |
EPWM_T::PDMACTL: CAPORD2_3 Position
Definition at line 3844 of file epwm_reg.h.
| #define EPWM_PDMACTL_CAPORD4_5_Msk (0x1ul << EPWM_PDMACTL_CAPORD4_5_Pos) |
EPWM_T::PDMACTL: CAPORD4_5 Mask
Definition at line 3857 of file epwm_reg.h.
| #define EPWM_PDMACTL_CAPORD4_5_Pos (19) |
EPWM_T::PDMACTL: CAPORD4_5 Position
Definition at line 3856 of file epwm_reg.h.
| #define EPWM_PDMACTL_CHEN0_1_Msk (0x1ul << EPWM_PDMACTL_CHEN0_1_Pos) |
EPWM_T::PDMACTL: CHEN0_1 Mask
Definition at line 3827 of file epwm_reg.h.
| #define EPWM_PDMACTL_CHEN0_1_Pos (0) |
EPWM_T::PDMACTL: CHEN0_1 Position
Definition at line 3826 of file epwm_reg.h.
| #define EPWM_PDMACTL_CHEN2_3_Msk (0x1ul << EPWM_PDMACTL_CHEN2_3_Pos) |
EPWM_T::PDMACTL: CHEN2_3 Mask
Definition at line 3839 of file epwm_reg.h.
| #define EPWM_PDMACTL_CHEN2_3_Pos (8) |
EPWM_T::PDMACTL: CHEN2_3 Position
Definition at line 3838 of file epwm_reg.h.
| #define EPWM_PDMACTL_CHEN4_5_Msk (0x1ul << EPWM_PDMACTL_CHEN4_5_Pos) |
EPWM_T::PDMACTL: CHEN4_5 Mask
Definition at line 3851 of file epwm_reg.h.
| #define EPWM_PDMACTL_CHEN4_5_Pos (16) |
EPWM_T::PDMACTL: CHEN4_5 Position
Definition at line 3850 of file epwm_reg.h.
| #define EPWM_PDMACTL_CHSEL0_1_Msk (0x1ul << EPWM_PDMACTL_CHSEL0_1_Pos) |
EPWM_T::PDMACTL: CHSEL0_1 Mask
Definition at line 3836 of file epwm_reg.h.
| #define EPWM_PDMACTL_CHSEL0_1_Pos (4) |
EPWM_T::PDMACTL: CHSEL0_1 Position
Definition at line 3835 of file epwm_reg.h.
| #define EPWM_PDMACTL_CHSEL2_3_Msk (0x1ul << EPWM_PDMACTL_CHSEL2_3_Pos) |
EPWM_T::PDMACTL: CHSEL2_3 Mask
Definition at line 3848 of file epwm_reg.h.
| #define EPWM_PDMACTL_CHSEL2_3_Pos (12) |
EPWM_T::PDMACTL: CHSEL2_3 Position
Definition at line 3847 of file epwm_reg.h.
| #define EPWM_PDMACTL_CHSEL4_5_Msk (0x1ul << EPWM_PDMACTL_CHSEL4_5_Pos) |
EPWM_T::PDMACTL: CHSEL4_5 Mask
Definition at line 3860 of file epwm_reg.h.
| #define EPWM_PDMACTL_CHSEL4_5_Pos (20) |
EPWM_T::PDMACTL: CHSEL4_5 Position
Definition at line 3859 of file epwm_reg.h.
| #define EPWM_PERIOD0_PERIOD_Msk (0xfffful << EPWM_PERIOD0_PERIOD_Pos) |
EPWM_T::PERIOD0: PERIOD Mask
Definition at line 2426 of file epwm_reg.h.
| #define EPWM_PERIOD0_PERIOD_Pos (0) |
EPWM_T::PERIOD0: PERIOD Position
Definition at line 2425 of file epwm_reg.h.
| #define EPWM_PERIOD1_PERIOD_Msk (0xfffful << EPWM_PERIOD1_PERIOD_Pos) |
EPWM_T::PERIOD1: PERIOD Mask
Definition at line 2429 of file epwm_reg.h.
| #define EPWM_PERIOD1_PERIOD_Pos (0) |
EPWM_T::PERIOD1: PERIOD Position
Definition at line 2428 of file epwm_reg.h.
| #define EPWM_PERIOD2_PERIOD_Msk (0xfffful << EPWM_PERIOD2_PERIOD_Pos) |
EPWM_T::PERIOD2: PERIOD Mask
Definition at line 2432 of file epwm_reg.h.
| #define EPWM_PERIOD2_PERIOD_Pos (0) |
EPWM_T::PERIOD2: PERIOD Position
Definition at line 2431 of file epwm_reg.h.
| #define EPWM_PERIOD3_PERIOD_Msk (0xfffful << EPWM_PERIOD3_PERIOD_Pos) |
EPWM_T::PERIOD3: PERIOD Mask
Definition at line 2435 of file epwm_reg.h.
| #define EPWM_PERIOD3_PERIOD_Pos (0) |
EPWM_T::PERIOD3: PERIOD Position
Definition at line 2434 of file epwm_reg.h.
| #define EPWM_PERIOD4_PERIOD_Msk (0xfffful << EPWM_PERIOD4_PERIOD_Pos) |
EPWM_T::PERIOD4: PERIOD Mask
Definition at line 2438 of file epwm_reg.h.
| #define EPWM_PERIOD4_PERIOD_Pos (0) |
EPWM_T::PERIOD4: PERIOD Position
Definition at line 2437 of file epwm_reg.h.
| #define EPWM_PERIOD5_PERIOD_Msk (0xfffful << EPWM_PERIOD5_PERIOD_Pos) |
EPWM_T::PERIOD5: PERIOD Mask
Definition at line 2441 of file epwm_reg.h.
| #define EPWM_PERIOD5_PERIOD_Pos (0) |
EPWM_T::PERIOD5: PERIOD Position
Definition at line 2440 of file epwm_reg.h.
| #define EPWM_PHS0_1_PHS_Msk (0xfffful << EPWM_PHS0_1_PHS_Pos) |
EPWM_T::PHS0_1: PHS Mask
Definition at line 2489 of file epwm_reg.h.
| #define EPWM_PHS0_1_PHS_Pos (0) |
EPWM_T::PHS0_1: PHS Position
Definition at line 2488 of file epwm_reg.h.
| #define EPWM_PHS2_3_PHS_Msk (0xfffful << EPWM_PHS2_3_PHS_Pos) |
EPWM_T::PHS2_3: PHS Mask
Definition at line 2492 of file epwm_reg.h.
| #define EPWM_PHS2_3_PHS_Pos (0) |
EPWM_T::PHS2_3: PHS Position
Definition at line 2491 of file epwm_reg.h.
| #define EPWM_PHS4_5_PHS_Msk (0xfffful << EPWM_PHS4_5_PHS_Pos) |
EPWM_T::PHS4_5: PHS Mask
Definition at line 2495 of file epwm_reg.h.
| #define EPWM_PHS4_5_PHS_Pos (0) |
EPWM_T::PHS4_5: PHS Position
Definition at line 2494 of file epwm_reg.h.
| #define EPWM_POEN_POEN0_Msk (0x1ul << EPWM_POEN_POEN0_Pos) |
EPWM_T::POEN: POEN0 Mask
Definition at line 2828 of file epwm_reg.h.
| #define EPWM_POEN_POEN0_Pos (0) |
EPWM_T::POEN: POEN0 Position
Definition at line 2827 of file epwm_reg.h.
| #define EPWM_POEN_POEN1_Msk (0x1ul << EPWM_POEN_POEN1_Pos) |
EPWM_T::POEN: POEN1 Mask
Definition at line 2831 of file epwm_reg.h.
| #define EPWM_POEN_POEN1_Pos (1) |
EPWM_T::POEN: POEN1 Position
Definition at line 2830 of file epwm_reg.h.
| #define EPWM_POEN_POEN2_Msk (0x1ul << EPWM_POEN_POEN2_Pos) |
EPWM_T::POEN: POEN2 Mask
Definition at line 2834 of file epwm_reg.h.
| #define EPWM_POEN_POEN2_Pos (2) |
EPWM_T::POEN: POEN2 Position
Definition at line 2833 of file epwm_reg.h.
| #define EPWM_POEN_POEN3_Msk (0x1ul << EPWM_POEN_POEN3_Pos) |
EPWM_T::POEN: POEN3 Mask
Definition at line 2837 of file epwm_reg.h.
| #define EPWM_POEN_POEN3_Pos (3) |
EPWM_T::POEN: POEN3 Position
Definition at line 2836 of file epwm_reg.h.
| #define EPWM_POEN_POEN4_Msk (0x1ul << EPWM_POEN_POEN4_Pos) |
EPWM_T::POEN: POEN4 Mask
Definition at line 2840 of file epwm_reg.h.
| #define EPWM_POEN_POEN4_Pos (4) |
EPWM_T::POEN: POEN4 Position
Definition at line 2839 of file epwm_reg.h.
| #define EPWM_POEN_POEN5_Msk (0x1ul << EPWM_POEN_POEN5_Pos) |
EPWM_T::POEN: POEN5 Mask
Definition at line 2843 of file epwm_reg.h.
| #define EPWM_POEN_POEN5_Pos (5) |
EPWM_T::POEN: POEN5 Position
Definition at line 2842 of file epwm_reg.h.
| #define EPWM_POLCTL_PINV0_Msk (0x1ul << EPWM_POLCTL_PINV0_Pos) |
EPWM_T::POLCTL: PINV0 Mask
Definition at line 2810 of file epwm_reg.h.
| #define EPWM_POLCTL_PINV0_Pos (0) |
EPWM_T::POLCTL: PINV0 Position
Definition at line 2809 of file epwm_reg.h.
| #define EPWM_POLCTL_PINV1_Msk (0x1ul << EPWM_POLCTL_PINV1_Pos) |
EPWM_T::POLCTL: PINV1 Mask
Definition at line 2813 of file epwm_reg.h.
| #define EPWM_POLCTL_PINV1_Pos (1) |
EPWM_T::POLCTL: PINV1 Position
Definition at line 2812 of file epwm_reg.h.
| #define EPWM_POLCTL_PINV2_Msk (0x1ul << EPWM_POLCTL_PINV2_Pos) |
EPWM_T::POLCTL: PINV2 Mask
Definition at line 2816 of file epwm_reg.h.
| #define EPWM_POLCTL_PINV2_Pos (2) |
EPWM_T::POLCTL: PINV2 Position
Definition at line 2815 of file epwm_reg.h.
| #define EPWM_POLCTL_PINV3_Msk (0x1ul << EPWM_POLCTL_PINV3_Pos) |
EPWM_T::POLCTL: PINV3 Mask
Definition at line 2819 of file epwm_reg.h.
| #define EPWM_POLCTL_PINV3_Pos (3) |
EPWM_T::POLCTL: PINV3 Position
Definition at line 2818 of file epwm_reg.h.
| #define EPWM_POLCTL_PINV4_Msk (0x1ul << EPWM_POLCTL_PINV4_Pos) |
EPWM_T::POLCTL: PINV4 Mask
Definition at line 2822 of file epwm_reg.h.
| #define EPWM_POLCTL_PINV4_Pos (4) |
EPWM_T::POLCTL: PINV4 Position
Definition at line 2821 of file epwm_reg.h.
| #define EPWM_POLCTL_PINV5_Msk (0x1ul << EPWM_POLCTL_PINV5_Pos) |
EPWM_T::POLCTL: PINV5 Mask
Definition at line 2825 of file epwm_reg.h.
| #define EPWM_POLCTL_PINV5_Pos (5) |
EPWM_T::POLCTL: PINV5 Position
Definition at line 2824 of file epwm_reg.h.
| #define EPWM_RCAPDAT0_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT0_RCAPDAT_Pos) |
EPWM_T::RCAPDAT0: RCAPDAT Mask
Definition at line 3791 of file epwm_reg.h.
| #define EPWM_RCAPDAT0_RCAPDAT_Pos (0) |
EPWM_T::RCAPDAT0: RCAPDAT Position
Definition at line 3790 of file epwm_reg.h.
| #define EPWM_RCAPDAT1_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT1_RCAPDAT_Pos) |
EPWM_T::RCAPDAT1: RCAPDAT Mask
Definition at line 3797 of file epwm_reg.h.
| #define EPWM_RCAPDAT1_RCAPDAT_Pos (0) |
EPWM_T::RCAPDAT1: RCAPDAT Position
Definition at line 3796 of file epwm_reg.h.
| #define EPWM_RCAPDAT2_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT2_RCAPDAT_Pos) |
EPWM_T::RCAPDAT2: RCAPDAT Mask
Definition at line 3803 of file epwm_reg.h.
| #define EPWM_RCAPDAT2_RCAPDAT_Pos (0) |
EPWM_T::RCAPDAT2: RCAPDAT Position
Definition at line 3802 of file epwm_reg.h.
| #define EPWM_RCAPDAT3_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT3_RCAPDAT_Pos) |
EPWM_T::RCAPDAT3: RCAPDAT Mask
Definition at line 3809 of file epwm_reg.h.
| #define EPWM_RCAPDAT3_RCAPDAT_Pos (0) |
EPWM_T::RCAPDAT3: RCAPDAT Position
Definition at line 3808 of file epwm_reg.h.
| #define EPWM_RCAPDAT4_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT4_RCAPDAT_Pos) |
EPWM_T::RCAPDAT4: RCAPDAT Mask
Definition at line 3815 of file epwm_reg.h.
| #define EPWM_RCAPDAT4_RCAPDAT_Pos (0) |
EPWM_T::RCAPDAT4: RCAPDAT Position
Definition at line 3814 of file epwm_reg.h.
| #define EPWM_RCAPDAT5_RCAPDAT_Msk (0xfffful << EPWM_RCAPDAT5_RCAPDAT_Pos) |
EPWM_T::RCAPDAT5: RCAPDAT Mask
Definition at line 3821 of file epwm_reg.h.
| #define EPWM_RCAPDAT5_RCAPDAT_Pos (0) |
EPWM_T::RCAPDAT5: RCAPDAT Position
Definition at line 3820 of file epwm_reg.h.
| #define EPWM_SSCTL_SSEN0_Msk (0x1ul << EPWM_SSCTL_SSEN0_Pos) |
EPWM_T::SSCTL: SSEN0 Mask
Definition at line 3215 of file epwm_reg.h.
| #define EPWM_SSCTL_SSEN0_Pos (0) |
EPWM_T::SSCTL: SSEN0 Position
Definition at line 3214 of file epwm_reg.h.
| #define EPWM_SSCTL_SSEN1_Msk (0x1ul << EPWM_SSCTL_SSEN1_Pos) |
EPWM_T::SSCTL: SSEN1 Mask
Definition at line 3218 of file epwm_reg.h.
| #define EPWM_SSCTL_SSEN1_Pos (1) |
EPWM_T::SSCTL: SSEN1 Position
Definition at line 3217 of file epwm_reg.h.
| #define EPWM_SSCTL_SSEN2_Msk (0x1ul << EPWM_SSCTL_SSEN2_Pos) |
EPWM_T::SSCTL: SSEN2 Mask
Definition at line 3221 of file epwm_reg.h.
| #define EPWM_SSCTL_SSEN2_Pos (2) |
EPWM_T::SSCTL: SSEN2 Position
Definition at line 3220 of file epwm_reg.h.
| #define EPWM_SSCTL_SSEN3_Msk (0x1ul << EPWM_SSCTL_SSEN3_Pos) |
EPWM_T::SSCTL: SSEN3 Mask
Definition at line 3224 of file epwm_reg.h.
| #define EPWM_SSCTL_SSEN3_Pos (3) |
EPWM_T::SSCTL: SSEN3 Position
Definition at line 3223 of file epwm_reg.h.
| #define EPWM_SSCTL_SSEN4_Msk (0x1ul << EPWM_SSCTL_SSEN4_Pos) |
EPWM_T::SSCTL: SSEN4 Mask
Definition at line 3227 of file epwm_reg.h.
| #define EPWM_SSCTL_SSEN4_Pos (4) |
EPWM_T::SSCTL: SSEN4 Position
Definition at line 3226 of file epwm_reg.h.
| #define EPWM_SSCTL_SSEN5_Msk (0x1ul << EPWM_SSCTL_SSEN5_Pos) |
EPWM_T::SSCTL: SSEN5 Mask
Definition at line 3230 of file epwm_reg.h.
| #define EPWM_SSCTL_SSEN5_Pos (5) |
EPWM_T::SSCTL: SSEN5 Position
Definition at line 3229 of file epwm_reg.h.
| #define EPWM_SSCTL_SSRC_Msk (0x3ul << EPWM_SSCTL_SSRC_Pos) |
EPWM_T::SSCTL: SSRC Mask
Definition at line 3233 of file epwm_reg.h.
| #define EPWM_SSCTL_SSRC_Pos (8) |
EPWM_T::SSCTL: SSRC Position
Definition at line 3232 of file epwm_reg.h.
| #define EPWM_SSTRG_CNTSEN_Msk (0x1ul << EPWM_SSTRG_CNTSEN_Pos) |
EPWM_T::SSTRG: CNTSEN Mask
Definition at line 3236 of file epwm_reg.h.
| #define EPWM_SSTRG_CNTSEN_Pos (0) |
EPWM_T::SSTRG: CNTSEN Position
Definition at line 3235 of file epwm_reg.h.
| #define EPWM_STATUS_CNTMAXF0_Msk (0x1ul << EPWM_STATUS_CNTMAXF0_Pos) |
EPWM_T::STATUS: CNTMAXF0 Mask
Definition at line 3257 of file epwm_reg.h.
| #define EPWM_STATUS_CNTMAXF0_Pos (0) |
EPWM_T::STATUS: CNTMAXF0 Position
Definition at line 3256 of file epwm_reg.h.
| #define EPWM_STATUS_CNTMAXF1_Msk (0x1ul << EPWM_STATUS_CNTMAXF1_Pos) |
EPWM_T::STATUS: CNTMAXF1 Mask
Definition at line 3260 of file epwm_reg.h.
| #define EPWM_STATUS_CNTMAXF1_Pos (1) |
EPWM_T::STATUS: CNTMAXF1 Position
Definition at line 3259 of file epwm_reg.h.
| #define EPWM_STATUS_CNTMAXF2_Msk (0x1ul << EPWM_STATUS_CNTMAXF2_Pos) |
EPWM_T::STATUS: CNTMAXF2 Mask
Definition at line 3263 of file epwm_reg.h.
| #define EPWM_STATUS_CNTMAXF2_Pos (2) |
EPWM_T::STATUS: CNTMAXF2 Position
Definition at line 3262 of file epwm_reg.h.
| #define EPWM_STATUS_CNTMAXF3_Msk (0x1ul << EPWM_STATUS_CNTMAXF3_Pos) |
EPWM_T::STATUS: CNTMAXF3 Mask
Definition at line 3266 of file epwm_reg.h.
| #define EPWM_STATUS_CNTMAXF3_Pos (3) |
EPWM_T::STATUS: CNTMAXF3 Position
Definition at line 3265 of file epwm_reg.h.
| #define EPWM_STATUS_CNTMAXF4_Msk (0x1ul << EPWM_STATUS_CNTMAXF4_Pos) |
EPWM_T::STATUS: CNTMAXF4 Mask
Definition at line 3269 of file epwm_reg.h.
| #define EPWM_STATUS_CNTMAXF4_Pos (4) |
EPWM_T::STATUS: CNTMAXF4 Position
Definition at line 3268 of file epwm_reg.h.
| #define EPWM_STATUS_CNTMAXF5_Msk (0x1ul << EPWM_STATUS_CNTMAXF5_Pos) |
EPWM_T::STATUS: CNTMAXF5 Mask
Definition at line 3272 of file epwm_reg.h.
| #define EPWM_STATUS_CNTMAXF5_Pos (5) |
EPWM_T::STATUS: CNTMAXF5 Position
Definition at line 3271 of file epwm_reg.h.
| #define EPWM_STATUS_DACTRGF_Msk (0x1ul << EPWM_STATUS_DACTRGF_Pos) |
EPWM_T::STATUS: DACTRGF Mask
Definition at line 3302 of file epwm_reg.h.
| #define EPWM_STATUS_DACTRGF_Pos (24) |
EPWM_T::STATUS: DACTRGF Position
Definition at line 3301 of file epwm_reg.h.
| #define EPWM_STATUS_EADCTRGF0_Msk (0x1ul << EPWM_STATUS_EADCTRGF0_Pos) |
EPWM_T::STATUS: EADCTRGF0 Mask
Definition at line 3284 of file epwm_reg.h.
| #define EPWM_STATUS_EADCTRGF0_Pos (16) |
EPWM_T::STATUS: EADCTRGF0 Position
Definition at line 3283 of file epwm_reg.h.
| #define EPWM_STATUS_EADCTRGF1_Msk (0x1ul << EPWM_STATUS_EADCTRGF1_Pos) |
EPWM_T::STATUS: EADCTRGF1 Mask
Definition at line 3287 of file epwm_reg.h.
| #define EPWM_STATUS_EADCTRGF1_Pos (17) |
EPWM_T::STATUS: EADCTRGF1 Position
Definition at line 3286 of file epwm_reg.h.
| #define EPWM_STATUS_EADCTRGF2_Msk (0x1ul << EPWM_STATUS_EADCTRGF2_Pos) |
EPWM_T::STATUS: EADCTRGF2 Mask
Definition at line 3290 of file epwm_reg.h.
| #define EPWM_STATUS_EADCTRGF2_Pos (18) |
EPWM_T::STATUS: EADCTRGF2 Position
Definition at line 3289 of file epwm_reg.h.
| #define EPWM_STATUS_EADCTRGF3_Msk (0x1ul << EPWM_STATUS_EADCTRGF3_Pos) |
EPWM_T::STATUS: EADCTRGF3 Mask
Definition at line 3293 of file epwm_reg.h.
| #define EPWM_STATUS_EADCTRGF3_Pos (19) |
EPWM_T::STATUS: EADCTRGF3 Position
Definition at line 3292 of file epwm_reg.h.
| #define EPWM_STATUS_EADCTRGF4_Msk (0x1ul << EPWM_STATUS_EADCTRGF4_Pos) |
EPWM_T::STATUS: EADCTRGF4 Mask
Definition at line 3296 of file epwm_reg.h.
| #define EPWM_STATUS_EADCTRGF4_Pos (20) |
EPWM_T::STATUS: EADCTRGF4 Position
Definition at line 3295 of file epwm_reg.h.
| #define EPWM_STATUS_EADCTRGF5_Msk (0x1ul << EPWM_STATUS_EADCTRGF5_Pos) |
EPWM_T::STATUS: EADCTRGF5 Mask
Definition at line 3299 of file epwm_reg.h.
| #define EPWM_STATUS_EADCTRGF5_Pos (21) |
EPWM_T::STATUS: EADCTRGF5 Position
Definition at line 3298 of file epwm_reg.h.
| #define EPWM_STATUS_SYNCINF0_Msk (0x1ul << EPWM_STATUS_SYNCINF0_Pos) |
EPWM_T::STATUS: SYNCINF0 Mask
Definition at line 3275 of file epwm_reg.h.
| #define EPWM_STATUS_SYNCINF0_Pos (8) |
EPWM_T::STATUS: SYNCINF0 Position
Definition at line 3274 of file epwm_reg.h.
| #define EPWM_STATUS_SYNCINF2_Msk (0x1ul << EPWM_STATUS_SYNCINF2_Pos) |
EPWM_T::STATUS: SYNCINF2 Mask
Definition at line 3278 of file epwm_reg.h.
| #define EPWM_STATUS_SYNCINF2_Pos (9) |
EPWM_T::STATUS: SYNCINF2 Position
Definition at line 3277 of file epwm_reg.h.
| #define EPWM_STATUS_SYNCINF4_Msk (0x1ul << EPWM_STATUS_SYNCINF4_Pos) |
EPWM_T::STATUS: SYNCINF4 Mask
Definition at line 3281 of file epwm_reg.h.
| #define EPWM_STATUS_SYNCINF4_Pos (10) |
EPWM_T::STATUS: SYNCINF4 Position
Definition at line 3280 of file epwm_reg.h.
| #define EPWM_SWBRK_BRKETRG0_Msk (0x1ul << EPWM_SWBRK_BRKETRG0_Pos) |
EPWM_T::SWBRK: BRKETRG0 Mask
Definition at line 2846 of file epwm_reg.h.
| #define EPWM_SWBRK_BRKETRG0_Pos (0) |
EPWM_T::SWBRK: BRKETRG0 Position
Definition at line 2845 of file epwm_reg.h.
| #define EPWM_SWBRK_BRKETRG2_Msk (0x1ul << EPWM_SWBRK_BRKETRG2_Pos) |
EPWM_T::SWBRK: BRKETRG2 Mask
Definition at line 2849 of file epwm_reg.h.
| #define EPWM_SWBRK_BRKETRG2_Pos (1) |
EPWM_T::SWBRK: BRKETRG2 Position
Definition at line 2848 of file epwm_reg.h.
| #define EPWM_SWBRK_BRKETRG4_Msk (0x1ul << EPWM_SWBRK_BRKETRG4_Pos) |
EPWM_T::SWBRK: BRKETRG4 Mask
Definition at line 2852 of file epwm_reg.h.
| #define EPWM_SWBRK_BRKETRG4_Pos (2) |
EPWM_T::SWBRK: BRKETRG4 Position
Definition at line 2851 of file epwm_reg.h.
| #define EPWM_SWBRK_BRKLTRG0_Msk (0x1ul << EPWM_SWBRK_BRKLTRG0_Pos) |
EPWM_T::SWBRK: BRKLTRG0 Mask
Definition at line 2855 of file epwm_reg.h.
| #define EPWM_SWBRK_BRKLTRG0_Pos (8) |
EPWM_T::SWBRK: BRKLTRG0 Position
Definition at line 2854 of file epwm_reg.h.
| #define EPWM_SWBRK_BRKLTRG2_Msk (0x1ul << EPWM_SWBRK_BRKLTRG2_Pos) |
EPWM_T::SWBRK: BRKLTRG2 Mask
Definition at line 2858 of file epwm_reg.h.
| #define EPWM_SWBRK_BRKLTRG2_Pos (9) |
EPWM_T::SWBRK: BRKLTRG2 Position
Definition at line 2857 of file epwm_reg.h.
| #define EPWM_SWBRK_BRKLTRG4_Msk (0x1ul << EPWM_SWBRK_BRKLTRG4_Pos) |
EPWM_T::SWBRK: BRKLTRG4 Mask
Definition at line 2861 of file epwm_reg.h.
| #define EPWM_SWBRK_BRKLTRG4_Pos (10) |
EPWM_T::SWBRK: BRKLTRG4 Position
Definition at line 2860 of file epwm_reg.h.
| #define EPWM_SWSYNC_SWSYNC0_Msk (0x1ul << EPWM_SWSYNC_SWSYNC0_Pos) |
EPWM_T::SWSYNC: SWSYNC0 Mask
Definition at line 2345 of file epwm_reg.h.
| #define EPWM_SWSYNC_SWSYNC0_Pos (0) |
EPWM_T::SWSYNC: SWSYNC0 Position
Definition at line 2344 of file epwm_reg.h.
| #define EPWM_SWSYNC_SWSYNC2_Msk (0x1ul << EPWM_SWSYNC_SWSYNC2_Pos) |
EPWM_T::SWSYNC: SWSYNC2 Mask
Definition at line 2348 of file epwm_reg.h.
| #define EPWM_SWSYNC_SWSYNC2_Pos (1) |
EPWM_T::SWSYNC: SWSYNC2 Position
Definition at line 2347 of file epwm_reg.h.
| #define EPWM_SWSYNC_SWSYNC4_Msk (0x1ul << EPWM_SWSYNC_SWSYNC4_Pos) |
EPWM_T::SWSYNC: SWSYNC4 Mask
Definition at line 2351 of file epwm_reg.h.
| #define EPWM_SWSYNC_SWSYNC4_Pos (2) |
EPWM_T::SWSYNC: SWSYNC4 Position
Definition at line 2350 of file epwm_reg.h.
| #define EPWM_SYNC_PHSDIR0_Msk (0x1ul << EPWM_SYNC_PHSDIR0_Pos) |
EPWM_T::SYNC: PHSDIR0 Mask
Definition at line 2336 of file epwm_reg.h.
| #define EPWM_SYNC_PHSDIR0_Pos (24) |
EPWM_T::SYNC: PHSDIR0 Position
Definition at line 2335 of file epwm_reg.h.
| #define EPWM_SYNC_PHSDIR2_Msk (0x1ul << EPWM_SYNC_PHSDIR2_Pos) |
EPWM_T::SYNC: PHSDIR2 Mask
Definition at line 2339 of file epwm_reg.h.
| #define EPWM_SYNC_PHSDIR2_Pos (25) |
EPWM_T::SYNC: PHSDIR2 Position
Definition at line 2338 of file epwm_reg.h.
| #define EPWM_SYNC_PHSDIR4_Msk (0x1ul << EPWM_SYNC_PHSDIR4_Pos) |
EPWM_T::SYNC: PHSDIR4 Mask
Definition at line 2342 of file epwm_reg.h.
| #define EPWM_SYNC_PHSDIR4_Pos (26) |
EPWM_T::SYNC: PHSDIR4 Position
Definition at line 2341 of file epwm_reg.h.
| #define EPWM_SYNC_PHSEN0_Msk (0x1ul << EPWM_SYNC_PHSEN0_Pos) |
EPWM_T::SYNC: PHSEN0 Mask
Definition at line 2306 of file epwm_reg.h.
| #define EPWM_SYNC_PHSEN0_Pos (0) |
EPWM_T::SYNC: PHSEN0 Position
Definition at line 2305 of file epwm_reg.h.
| #define EPWM_SYNC_PHSEN2_Msk (0x1ul << EPWM_SYNC_PHSEN2_Pos) |
EPWM_T::SYNC: PHSEN2 Mask
Definition at line 2309 of file epwm_reg.h.
| #define EPWM_SYNC_PHSEN2_Pos (1) |
EPWM_T::SYNC: PHSEN2 Position
Definition at line 2308 of file epwm_reg.h.
| #define EPWM_SYNC_PHSEN4_Msk (0x1ul << EPWM_SYNC_PHSEN4_Pos) |
EPWM_T::SYNC: PHSEN4 Mask
Definition at line 2312 of file epwm_reg.h.
| #define EPWM_SYNC_PHSEN4_Pos (2) |
EPWM_T::SYNC: PHSEN4 Position
Definition at line 2311 of file epwm_reg.h.
| #define EPWM_SYNC_SFLTCNT_Msk (0x7ul << EPWM_SYNC_SFLTCNT_Pos) |
EPWM_T::SYNC: SFLTCNT Mask
Definition at line 2330 of file epwm_reg.h.
| #define EPWM_SYNC_SFLTCNT_Pos (20) |
EPWM_T::SYNC: SFLTCNT Position
Definition at line 2329 of file epwm_reg.h.
| #define EPWM_SYNC_SFLTCSEL_Msk (0x7ul << EPWM_SYNC_SFLTCSEL_Pos) |
EPWM_T::SYNC: SFLTCSEL Mask
Definition at line 2327 of file epwm_reg.h.
| #define EPWM_SYNC_SFLTCSEL_Pos (17) |
EPWM_T::SYNC: SFLTCSEL Position
Definition at line 2326 of file epwm_reg.h.
| #define EPWM_SYNC_SINPINV_Msk (0x1ul << EPWM_SYNC_SINPINV_Pos) |
EPWM_T::SYNC: SINPINV Mask
Definition at line 2333 of file epwm_reg.h.
| #define EPWM_SYNC_SINPINV_Pos (23) |
EPWM_T::SYNC: SINPINV Position
Definition at line 2332 of file epwm_reg.h.
| #define EPWM_SYNC_SINSRC0_Msk (0x3ul << EPWM_SYNC_SINSRC0_Pos) |
EPWM_T::SYNC: SINSRC0 Mask
Definition at line 2315 of file epwm_reg.h.
| #define EPWM_SYNC_SINSRC0_Pos (8) |
EPWM_T::SYNC: SINSRC0 Position
Definition at line 2314 of file epwm_reg.h.
| #define EPWM_SYNC_SINSRC2_Msk (0x3ul << EPWM_SYNC_SINSRC2_Pos) |
EPWM_T::SYNC: SINSRC2 Mask
Definition at line 2318 of file epwm_reg.h.
| #define EPWM_SYNC_SINSRC2_Pos (10) |
EPWM_T::SYNC: SINSRC2 Position
Definition at line 2317 of file epwm_reg.h.
| #define EPWM_SYNC_SINSRC4_Msk (0x3ul << EPWM_SYNC_SINSRC4_Pos) |
EPWM_T::SYNC: SINSRC4 Mask
Definition at line 2321 of file epwm_reg.h.
| #define EPWM_SYNC_SINSRC4_Pos (12) |
EPWM_T::SYNC: SINSRC4 Position
Definition at line 2320 of file epwm_reg.h.
| #define EPWM_SYNC_SNFLTEN_Msk (0x1ul << EPWM_SYNC_SNFLTEN_Pos) |
EPWM_T::SYNC: SNFLTEN Mask
Definition at line 2324 of file epwm_reg.h.
| #define EPWM_SYNC_SNFLTEN_Pos (16) |
EPWM_T::SYNC: SNFLTEN Position
Definition at line 2323 of file epwm_reg.h.
| #define EPWM_WGCTL0_PRDPCTL0_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL0_Pos) |
EPWM_T::WGCTL0: PRDPCTL0 Mask
Definition at line 2552 of file epwm_reg.h.
| #define EPWM_WGCTL0_PRDPCTL0_Pos (16) |
EPWM_T::WGCTL0: PRDPCTL0 Position
Definition at line 2551 of file epwm_reg.h.
| #define EPWM_WGCTL0_PRDPCTL1_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL1_Pos) |
EPWM_T::WGCTL0: PRDPCTL1 Mask
Definition at line 2555 of file epwm_reg.h.
| #define EPWM_WGCTL0_PRDPCTL1_Pos (18) |
EPWM_T::WGCTL0: PRDPCTL1 Position
Definition at line 2554 of file epwm_reg.h.
| #define EPWM_WGCTL0_PRDPCTL2_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL2_Pos) |
EPWM_T::WGCTL0: PRDPCTL2 Mask
Definition at line 2558 of file epwm_reg.h.
| #define EPWM_WGCTL0_PRDPCTL2_Pos (20) |
EPWM_T::WGCTL0: PRDPCTL2 Position
Definition at line 2557 of file epwm_reg.h.
| #define EPWM_WGCTL0_PRDPCTL3_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL3_Pos) |
EPWM_T::WGCTL0: PRDPCTL3 Mask
Definition at line 2561 of file epwm_reg.h.
| #define EPWM_WGCTL0_PRDPCTL3_Pos (22) |
EPWM_T::WGCTL0: PRDPCTL3 Position
Definition at line 2560 of file epwm_reg.h.
| #define EPWM_WGCTL0_PRDPCTL4_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL4_Pos) |
EPWM_T::WGCTL0: PRDPCTL4 Mask
Definition at line 2564 of file epwm_reg.h.
| #define EPWM_WGCTL0_PRDPCTL4_Pos (24) |
EPWM_T::WGCTL0: PRDPCTL4 Position
Definition at line 2563 of file epwm_reg.h.
| #define EPWM_WGCTL0_PRDPCTL5_Msk (0x3ul << EPWM_WGCTL0_PRDPCTL5_Pos) |
EPWM_T::WGCTL0: PRDPCTL5 Mask
Definition at line 2567 of file epwm_reg.h.
| #define EPWM_WGCTL0_PRDPCTL5_Pos (26) |
EPWM_T::WGCTL0: PRDPCTL5 Position
Definition at line 2566 of file epwm_reg.h.
| #define EPWM_WGCTL0_ZPCTL0_Msk (0x3ul << EPWM_WGCTL0_ZPCTL0_Pos) |
EPWM_T::WGCTL0: ZPCTL0 Mask
Definition at line 2534 of file epwm_reg.h.
| #define EPWM_WGCTL0_ZPCTL0_Pos (0) |
EPWM_T::WGCTL0: ZPCTL0 Position
Definition at line 2533 of file epwm_reg.h.
| #define EPWM_WGCTL0_ZPCTL1_Msk (0x3ul << EPWM_WGCTL0_ZPCTL1_Pos) |
EPWM_T::WGCTL0: ZPCTL1 Mask
Definition at line 2537 of file epwm_reg.h.
| #define EPWM_WGCTL0_ZPCTL1_Pos (2) |
EPWM_T::WGCTL0: ZPCTL1 Position
Definition at line 2536 of file epwm_reg.h.
| #define EPWM_WGCTL0_ZPCTL2_Msk (0x3ul << EPWM_WGCTL0_ZPCTL2_Pos) |
EPWM_T::WGCTL0: ZPCTL2 Mask
Definition at line 2540 of file epwm_reg.h.
| #define EPWM_WGCTL0_ZPCTL2_Pos (4) |
EPWM_T::WGCTL0: ZPCTL2 Position
Definition at line 2539 of file epwm_reg.h.
| #define EPWM_WGCTL0_ZPCTL3_Msk (0x3ul << EPWM_WGCTL0_ZPCTL3_Pos) |
EPWM_T::WGCTL0: ZPCTL3 Mask
Definition at line 2543 of file epwm_reg.h.
| #define EPWM_WGCTL0_ZPCTL3_Pos (6) |
EPWM_T::WGCTL0: ZPCTL3 Position
Definition at line 2542 of file epwm_reg.h.
| #define EPWM_WGCTL0_ZPCTL4_Msk (0x3ul << EPWM_WGCTL0_ZPCTL4_Pos) |
EPWM_T::WGCTL0: ZPCTL4 Mask
Definition at line 2546 of file epwm_reg.h.
| #define EPWM_WGCTL0_ZPCTL4_Pos (8) |
EPWM_T::WGCTL0: ZPCTL4 Position
Definition at line 2545 of file epwm_reg.h.
| #define EPWM_WGCTL0_ZPCTL5_Msk (0x3ul << EPWM_WGCTL0_ZPCTL5_Pos) |
EPWM_T::WGCTL0: ZPCTL5 Mask
Definition at line 2549 of file epwm_reg.h.
| #define EPWM_WGCTL0_ZPCTL5_Pos (10) |
EPWM_T::WGCTL0: ZPCTL5 Position
Definition at line 2548 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPDCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL0_Pos) |
EPWM_T::WGCTL1: CMPDCTL0 Mask
Definition at line 2588 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPDCTL0_Pos (16) |
EPWM_T::WGCTL1: CMPDCTL0 Position
Definition at line 2587 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPDCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL1_Pos) |
EPWM_T::WGCTL1: CMPDCTL1 Mask
Definition at line 2591 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPDCTL1_Pos (18) |
EPWM_T::WGCTL1: CMPDCTL1 Position
Definition at line 2590 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPDCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL2_Pos) |
EPWM_T::WGCTL1: CMPDCTL2 Mask
Definition at line 2594 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPDCTL2_Pos (20) |
EPWM_T::WGCTL1: CMPDCTL2 Position
Definition at line 2593 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPDCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL3_Pos) |
EPWM_T::WGCTL1: CMPDCTL3 Mask
Definition at line 2597 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPDCTL3_Pos (22) |
EPWM_T::WGCTL1: CMPDCTL3 Position
Definition at line 2596 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPDCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL4_Pos) |
EPWM_T::WGCTL1: CMPDCTL4 Mask
Definition at line 2600 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPDCTL4_Pos (24) |
EPWM_T::WGCTL1: CMPDCTL4 Position
Definition at line 2599 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPDCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPDCTL5_Pos) |
EPWM_T::WGCTL1: CMPDCTL5 Mask
Definition at line 2603 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPDCTL5_Pos (26) |
EPWM_T::WGCTL1: CMPDCTL5 Position
Definition at line 2602 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPUCTL0_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL0_Pos) |
EPWM_T::WGCTL1: CMPUCTL0 Mask
Definition at line 2570 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPUCTL0_Pos (0) |
EPWM_T::WGCTL1: CMPUCTL0 Position
Definition at line 2569 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPUCTL1_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL1_Pos) |
EPWM_T::WGCTL1: CMPUCTL1 Mask
Definition at line 2573 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPUCTL1_Pos (2) |
EPWM_T::WGCTL1: CMPUCTL1 Position
Definition at line 2572 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPUCTL2_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL2_Pos) |
EPWM_T::WGCTL1: CMPUCTL2 Mask
Definition at line 2576 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPUCTL2_Pos (4) |
EPWM_T::WGCTL1: CMPUCTL2 Position
Definition at line 2575 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPUCTL3_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL3_Pos) |
EPWM_T::WGCTL1: CMPUCTL3 Mask
Definition at line 2579 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPUCTL3_Pos (6) |
EPWM_T::WGCTL1: CMPUCTL3 Position
Definition at line 2578 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPUCTL4_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL4_Pos) |
EPWM_T::WGCTL1: CMPUCTL4 Mask
Definition at line 2582 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPUCTL4_Pos (8) |
EPWM_T::WGCTL1: CMPUCTL4 Position
Definition at line 2581 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPUCTL5_Msk (0x3ul << EPWM_WGCTL1_CMPUCTL5_Pos) |
EPWM_T::WGCTL1: CMPUCTL5 Mask
Definition at line 2585 of file epwm_reg.h.
| #define EPWM_WGCTL1_CMPUCTL5_Pos (10) |
EPWM_T::WGCTL1: CMPUCTL5 Position
Definition at line 2584 of file epwm_reg.h.
| #define FMC_CYCCTL_CYCLE_Msk (0xful << FMC_CYCCTL_CYCLE_Pos) |
FMC_T::CYCCTL: CYCLE Mask
| #define FMC_CYCCTL_CYCLE_Pos (0) |
FMC_T::CYCCTL: CYCLE Position
| #define FMC_DFBA_DFBA_Msk (0xfffffffful << FMC_DFBA_DFBA_Pos) |
FMC_T::DFBA: DFBA Mask
| #define FMC_DFBA_DFBA_Pos (0) |
FMC_T::DFBA: DFBA Position
| #define FMC_ISPADDR_ISPADDR_Msk (0xfffffffful << FMC_ISPADDR_ISPADDR_Pos) |
FMC_T::ISPADDR: ISPADDR Mask
| #define FMC_ISPADDR_ISPADDR_Pos (0) |
FMC_T::ISPADDR: ISPADDR Position
| #define FMC_ISPCMD_CMD_Msk (0x7ful << FMC_ISPCMD_CMD_Pos) |
FMC_T::ISPCMD: CMD Mask
| #define FMC_ISPCMD_CMD_Pos (0) |
FMC_T::ISPCMD: CMD Position
| #define FMC_ISPCTL_APUEN_Msk (0x1ul << FMC_ISPCTL_APUEN_Pos) |
FMC_T::ISPCTL: APUEN Mask
| #define FMC_ISPCTL_APUEN_Pos (3) |
FMC_T::ISPCTL: APUEN Position
| #define FMC_ISPCTL_BL_Msk (0x1ul << FMC_ISPCTL_BL_Pos) |
FMC_T::ISPCTL: BL Mask
| #define FMC_ISPCTL_BL_Pos (16) |
FMC_T::ISPCTL: BL Position
| #define FMC_ISPCTL_BS_Msk (0x1ul << FMC_ISPCTL_BS_Pos) |
FMC_T::ISPCTL: BS Mask
| #define FMC_ISPCTL_BS_Pos (1) |
FMC_T::ISPCTL: BS Position
| #define FMC_ISPCTL_CFGUEN_Msk (0x1ul << FMC_ISPCTL_CFGUEN_Pos) |
FMC_T::ISPCTL: CFGUEN Mask
| #define FMC_ISPCTL_CFGUEN_Pos (4) |
FMC_T::ISPCTL: CFGUEN Position
| #define FMC_ISPCTL_ISPEN_Msk (0x1ul << FMC_ISPCTL_ISPEN_Pos) |
FMC_T::ISPCTL: ISPEN Mask
| #define FMC_ISPCTL_ISPEN_Pos (0) |
@addtogroup FMC_CONST FMC Bit Field Definition Constant Definitions for FMC Controller
FMC_T::ISPCTL: ISPEN Position
| #define FMC_ISPCTL_ISPFF_Msk (0x1ul << FMC_ISPCTL_ISPFF_Pos) |
FMC_T::ISPCTL: ISPFF Mask
| #define FMC_ISPCTL_ISPFF_Pos (6) |
FMC_T::ISPCTL: ISPFF Position
| #define FMC_ISPCTL_LDUEN_Msk (0x1ul << FMC_ISPCTL_LDUEN_Pos) |
FMC_T::ISPCTL: LDUEN Mask
| #define FMC_ISPCTL_LDUEN_Pos (5) |
FMC_T::ISPCTL: LDUEN Position
| #define FMC_ISPCTL_SPUEN_Msk (0x1ul << FMC_ISPCTL_SPUEN_Pos) |
FMC_T::ISPCTL: SPUEN Mask
| #define FMC_ISPCTL_SPUEN_Pos (2) |
FMC_T::ISPCTL: SPUEN Position
| #define FMC_ISPDAT_ISPDAT_Msk (0xfffffffful << FMC_ISPDAT_ISPDAT_Pos) |
FMC_T::ISPDAT: ISPDAT Mask
| #define FMC_ISPDAT_ISPDAT_Pos (0) |
FMC_T::ISPDAT: ISPDAT Position
| #define FMC_ISPSTS_ALLONE_Msk (0x1ul << FMC_ISPSTS_ALLONE_Pos) |
FMC_T::ISPSTS: ALLONE Mask
| #define FMC_ISPSTS_ALLONE_Pos (7) |
FMC_T::ISPSTS: ALLONE Position
| #define FMC_ISPSTS_CBS_Msk (0x3ul << FMC_ISPSTS_CBS_Pos) |
FMC_T::ISPSTS: CBS Mask
| #define FMC_ISPSTS_CBS_Pos (1) |
FMC_T::ISPSTS: CBS Position
| #define FMC_ISPSTS_FCYCDIS_Msk (0x1ul << FMC_ISPSTS_FCYCDIS_Pos) |
FMC_T::ISPSTS: FCYCDIS Mask
| #define FMC_ISPSTS_FCYCDIS_Pos (4) |
FMC_T::ISPSTS: FCYCDIS Position
| #define FMC_ISPSTS_ISPBUSY_Msk (0x1ul << FMC_ISPSTS_ISPBUSY_Pos) |
FMC_T::ISPSTS: ISPBUSY Mask
| #define FMC_ISPSTS_ISPBUSY_Pos (0) |
FMC_T::ISPSTS: ISPBUSY Position
| #define FMC_ISPSTS_ISPFF_Msk (0x1ul << FMC_ISPSTS_ISPFF_Pos) |
FMC_T::ISPSTS: ISPFF Mask
| #define FMC_ISPSTS_ISPFF_Pos (6) |
FMC_T::ISPSTS: ISPFF Position
| #define FMC_ISPSTS_MBS_Msk (0x1ul << FMC_ISPSTS_MBS_Pos) |
FMC_T::ISPSTS: MBS Mask
| #define FMC_ISPSTS_MBS_Pos (3) |
FMC_T::ISPSTS: MBS Position
| #define FMC_ISPSTS_PGFF_Msk (0x1ul << FMC_ISPSTS_PGFF_Pos) |
FMC_T::ISPSTS: PGFF Mask
| #define FMC_ISPSTS_PGFF_Pos (5) |
FMC_T::ISPSTS: PGFF Position
| #define FMC_ISPSTS_SCODE_Msk (0x1ul << FMC_ISPSTS_SCODE_Pos) |
FMC_T::ISPSTS: SCODE Mask
| #define FMC_ISPSTS_SCODE_Pos (31) |
FMC_T::ISPSTS: SCODE Position
| #define FMC_ISPSTS_VECMAP_Msk (0x7ffful << FMC_ISPSTS_VECMAP_Pos) |
FMC_T::ISPSTS: VECMAP Mask
| #define FMC_ISPSTS_VECMAP_Pos (9) |
FMC_T::ISPSTS: VECMAP Position
| #define FMC_ISPTRG_ISPGO_Msk (0x1ul << FMC_ISPTRG_ISPGO_Pos) |
FMC_T::ISPTRG: ISPGO Mask
| #define FMC_ISPTRG_ISPGO_Pos (0) |
FMC_T::ISPTRG: ISPGO Position
| #define FMC_KPCNT_KPCNT_Msk (0xful << FMC_KPCNT_KPCNT_Pos) |
FMC_T::KPCNT: KPCNT Mask
| #define FMC_KPCNT_KPCNT_Pos (0) |
FMC_T::KPCNT: KPCNT Position
| #define FMC_KPCNT_KPMAX_Msk (0xful << FMC_KPCNT_KPMAX_Pos) |
FMC_T::KPCNT: KPMAX Mask
| #define FMC_KPCNT_KPMAX_Pos (8) |
FMC_T::KPCNT: KPMAX Position
| #define FMC_KPKEY0_KPKEY0_Msk (0xfffffffful << FMC_KPKEY0_KPKEY0_Pos) |
FMC_T::KPKEY0: KPKEY0 Mask
| #define FMC_KPKEY0_KPKEY0_Pos (0) |
FMC_T::KPKEY0: KPKEY0 Position
| #define FMC_KPKEY1_KPKEY1_Msk (0xfffffffful << FMC_KPKEY1_KPKEY1_Pos) |
FMC_T::KPKEY1: KPKEY1 Mask
| #define FMC_KPKEY1_KPKEY1_Pos (0) |
FMC_T::KPKEY1: KPKEY1 Position
| #define FMC_KPKEY2_KPKEY2_Msk (0xfffffffful << FMC_KPKEY2_KPKEY2_Pos) |
FMC_T::KPKEY2: KPKEY2 Mask
| #define FMC_KPKEY2_KPKEY2_Pos (0) |
FMC_T::KPKEY2: KPKEY2 Position
| #define FMC_KPKEYCNT_KPKECNT_Msk (0x3ful << FMC_KPKEYCNT_KPKECNT_Pos) |
FMC_T::KPKEYCNT: KPKECNT Mask
| #define FMC_KPKEYCNT_KPKECNT_Pos (0) |
FMC_T::KPKEYCNT: KPKECNT Position
| #define FMC_KPKEYCNT_KPKEMAX_Msk (0x3ful << FMC_KPKEYCNT_KPKEMAX_Pos) |
FMC_T::KPKEYCNT: KPKEMAX Mask
| #define FMC_KPKEYCNT_KPKEMAX_Pos (8) |
FMC_T::KPKEYCNT: KPKEMAX Position
| #define FMC_KPKEYSTS_CFGFLAG_Msk (0x1ul << FMC_KPKEYSTS_CFGFLAG_Pos) |
FMC_T::KPKEYSTS: CFGFLAG Mask
| #define FMC_KPKEYSTS_CFGFLAG_Pos (5) |
FMC_T::KPKEYSTS: CFGFLAG Position
| #define FMC_KPKEYSTS_FORBID_Msk (0x1ul << FMC_KPKEYSTS_FORBID_Pos) |
FMC_T::KPKEYSTS: FORBID Mask
| #define FMC_KPKEYSTS_FORBID_Pos (3) |
FMC_T::KPKEYSTS: FORBID Position
| #define FMC_KPKEYSTS_KEYBUSY_Msk (0x1ul << FMC_KPKEYSTS_KEYBUSY_Pos) |
FMC_T::KPKEYSTS: KEYBUSY Mask
| #define FMC_KPKEYSTS_KEYBUSY_Pos (0) |
FMC_T::KPKEYSTS: KEYBUSY Position
| #define FMC_KPKEYSTS_KEYFLAG_Msk (0x1ul << FMC_KPKEYSTS_KEYFLAG_Pos) |
FMC_T::KPKEYSTS: KEYFLAG Mask
| #define FMC_KPKEYSTS_KEYFLAG_Pos (4) |
FMC_T::KPKEYSTS: KEYFLAG Position
| #define FMC_KPKEYSTS_KEYLOCK_Msk (0x1ul << FMC_KPKEYSTS_KEYLOCK_Pos) |
FMC_T::KPKEYSTS: KEYLOCK Mask
| #define FMC_KPKEYSTS_KEYLOCK_Pos (1) |
FMC_T::KPKEYSTS: KEYLOCK Position
| #define FMC_KPKEYSTS_KEYMATCH_Msk (0x1ul << FMC_KPKEYSTS_KEYMATCH_Pos) |
FMC_T::KPKEYSTS: KEYMATCH Mask
| #define FMC_KPKEYSTS_KEYMATCH_Pos (2) |
FMC_T::KPKEYSTS: KEYMATCH Position
| #define FMC_KPKEYSTS_SPFLAG_Msk (0x1ul << FMC_KPKEYSTS_SPFLAG_Pos) |
FMC_T::KPKEYSTS: SPFLAG Mask
| #define FMC_KPKEYSTS_SPFLAG_Pos (6) |
FMC_T::KPKEYSTS: SPFLAG Position
| #define FMC_KPKEYTRG_KPKEYGO_Msk (0x1ul << FMC_KPKEYTRG_KPKEYGO_Pos) |
FMC_T::KPKEYTRG: KPKEYGO Mask
| #define FMC_KPKEYTRG_KPKEYGO_Pos (0) |
FMC_T::KPKEYTRG: KPKEYGO Position
| #define FMC_KPKEYTRG_TCEN_Msk (0x1ul << FMC_KPKEYTRG_TCEN_Pos) |
FMC_T::KPKEYTRG: TCEN Mask
| #define FMC_KPKEYTRG_TCEN_Pos (1) |
FMC_T::KPKEYTRG: TCEN Position
| #define FMC_MPADDR_MPADDR_Msk (0xfffffffful << FMC_MPADDR_MPADDR_Pos) |
FMC_T::MPADDR: MPADDR Mask
| #define FMC_MPADDR_MPADDR_Pos (0) |
FMC_T::MPADDR: MPADDR Position
| #define FMC_MPDAT0_ISPDAT0_Msk (0xfffffffful << FMC_MPDAT0_ISPDAT0_Pos) |
FMC_T::MPDAT0: ISPDAT0 Mask
| #define FMC_MPDAT0_ISPDAT0_Pos (0) |
FMC_T::MPDAT0: ISPDAT0 Position
| #define FMC_MPDAT1_ISPDAT1_Msk (0xfffffffful << FMC_MPDAT1_ISPDAT1_Pos) |
FMC_T::MPDAT1: ISPDAT1 Mask
| #define FMC_MPDAT1_ISPDAT1_Pos (0) |
FMC_T::MPDAT1: ISPDAT1 Position
| #define FMC_MPDAT2_ISPDAT2_Msk (0xfffffffful << FMC_MPDAT2_ISPDAT2_Pos) |
FMC_T::MPDAT2: ISPDAT2 Mask
| #define FMC_MPDAT2_ISPDAT2_Pos (0) |
FMC_T::MPDAT2: ISPDAT2 Position
| #define FMC_MPDAT3_ISPDAT3_Msk (0xfffffffful << FMC_MPDAT3_ISPDAT3_Pos) |
FMC_T::MPDAT3: ISPDAT3 Mask
| #define FMC_MPDAT3_ISPDAT3_Pos (0) |
FMC_T::MPDAT3: ISPDAT3 Position
| #define FMC_MPSTS_D0_Msk (0x1ul << FMC_MPSTS_D0_Pos) |
FMC_T::MPSTS: D0 Mask
| #define FMC_MPSTS_D0_Pos (4) |
FMC_T::MPSTS: D0 Position
| #define FMC_MPSTS_D1_Msk (0x1ul << FMC_MPSTS_D1_Pos) |
FMC_T::MPSTS: D1 Mask
| #define FMC_MPSTS_D1_Pos (5) |
FMC_T::MPSTS: D1 Position
| #define FMC_MPSTS_D2_Msk (0x1ul << FMC_MPSTS_D2_Pos) |
FMC_T::MPSTS: D2 Mask
| #define FMC_MPSTS_D2_Pos (6) |
FMC_T::MPSTS: D2 Position
| #define FMC_MPSTS_D3_Msk (0x1ul << FMC_MPSTS_D3_Pos) |
FMC_T::MPSTS: D3 Mask
| #define FMC_MPSTS_D3_Pos (7) |
FMC_T::MPSTS: D3 Position
| #define FMC_MPSTS_ISPFF_Msk (0x1ul << FMC_MPSTS_ISPFF_Pos) |
FMC_T::MPSTS: ISPFF Mask
| #define FMC_MPSTS_ISPFF_Pos (2) |
FMC_T::MPSTS: ISPFF Position
| #define FMC_MPSTS_MPBUSY_Msk (0x1ul << FMC_MPSTS_MPBUSY_Pos) |
FMC_T::MPSTS: MPBUSY Mask
| #define FMC_MPSTS_MPBUSY_Pos (0) |
FMC_T::MPSTS: MPBUSY Position
| #define FMC_MPSTS_PPGO_Msk (0x1ul << FMC_MPSTS_PPGO_Pos) |
FMC_T::MPSTS: PPGO Mask
| #define FMC_MPSTS_PPGO_Pos (1) |
FMC_T::MPSTS: PPGO Position
| #define GPIO_DATMSK_DATMSK0_Msk (0x1ul << GPIO_DATMSK_DATMSK0_Pos) |
GPIO_T::DATMSK: DATMSK0 Mask
Definition at line 440 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK0_Pos (0) |
GPIO_T::DATMSK: DATMSK0 Position
Definition at line 439 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK10_Msk (0x1ul << GPIO_DATMSK_DATMSK10_Pos) |
GPIO_T::DATMSK: DATMSK10 Mask
Definition at line 470 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK10_Pos (10) |
GPIO_T::DATMSK: DATMSK10 Position
Definition at line 469 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK11_Msk (0x1ul << GPIO_DATMSK_DATMSK11_Pos) |
GPIO_T::DATMSK: DATMSK11 Mask
Definition at line 473 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK11_Pos (11) |
GPIO_T::DATMSK: DATMSK11 Position
Definition at line 472 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK12_Msk (0x1ul << GPIO_DATMSK_DATMSK12_Pos) |
GPIO_T::DATMSK: DATMSK12 Mask
Definition at line 476 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK12_Pos (12) |
GPIO_T::DATMSK: DATMSK12 Position
Definition at line 475 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK13_Msk (0x1ul << GPIO_DATMSK_DATMSK13_Pos) |
GPIO_T::DATMSK: DATMSK13 Mask
Definition at line 479 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK13_Pos (13) |
GPIO_T::DATMSK: DATMSK13 Position
Definition at line 478 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK14_Msk (0x1ul << GPIO_DATMSK_DATMSK14_Pos) |
GPIO_T::DATMSK: DATMSK14 Mask
Definition at line 482 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK14_Pos (14) |
GPIO_T::DATMSK: DATMSK14 Position
Definition at line 481 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK15_Msk (0x1ul << GPIO_DATMSK_DATMSK15_Pos) |
GPIO_T::DATMSK: DATMSK15 Mask
Definition at line 485 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK15_Pos (15) |
GPIO_T::DATMSK: DATMSK15 Position
Definition at line 484 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK1_Msk (0x1ul << GPIO_DATMSK_DATMSK1_Pos) |
GPIO_T::DATMSK: DATMSK1 Mask
Definition at line 443 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK1_Pos (1) |
GPIO_T::DATMSK: DATMSK1 Position
Definition at line 442 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK2_Msk (0x1ul << GPIO_DATMSK_DATMSK2_Pos) |
GPIO_T::DATMSK: DATMSK2 Mask
Definition at line 446 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK2_Pos (2) |
GPIO_T::DATMSK: DATMSK2 Position
Definition at line 445 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK3_Msk (0x1ul << GPIO_DATMSK_DATMSK3_Pos) |
GPIO_T::DATMSK: DATMSK3 Mask
Definition at line 449 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK3_Pos (3) |
GPIO_T::DATMSK: DATMSK3 Position
Definition at line 448 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK4_Msk (0x1ul << GPIO_DATMSK_DATMSK4_Pos) |
GPIO_T::DATMSK: DATMSK4 Mask
Definition at line 452 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK4_Pos (4) |
GPIO_T::DATMSK: DATMSK4 Position
Definition at line 451 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK5_Msk (0x1ul << GPIO_DATMSK_DATMSK5_Pos) |
GPIO_T::DATMSK: DATMSK5 Mask
Definition at line 455 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK5_Pos (5) |
GPIO_T::DATMSK: DATMSK5 Position
Definition at line 454 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK6_Msk (0x1ul << GPIO_DATMSK_DATMSK6_Pos) |
GPIO_T::DATMSK: DATMSK6 Mask
Definition at line 458 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK6_Pos (6) |
GPIO_T::DATMSK: DATMSK6 Position
Definition at line 457 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK7_Msk (0x1ul << GPIO_DATMSK_DATMSK7_Pos) |
GPIO_T::DATMSK: DATMSK7 Mask
Definition at line 461 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK7_Pos (7) |
GPIO_T::DATMSK: DATMSK7 Position
Definition at line 460 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK8_Msk (0x1ul << GPIO_DATMSK_DATMSK8_Pos) |
GPIO_T::DATMSK: DATMSK8 Mask
Definition at line 464 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK8_Pos (8) |
GPIO_T::DATMSK: DATMSK8 Position
Definition at line 463 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK9_Msk (0x1ul << GPIO_DATMSK_DATMSK9_Pos) |
GPIO_T::DATMSK: DATMSK9 Mask
Definition at line 467 of file gpio_reg.h.
| #define GPIO_DATMSK_DATMSK9_Pos (9) |
GPIO_T::DATMSK: DATMSK9 Position
Definition at line 466 of file gpio_reg.h.
| #define GPIO_DBCTL_DBCLKSEL_Msk (0xFul << GPIO_DBCTL_DBCLKSEL_Pos) |
GPIO_T::DBCTL: DBCLKSEL Mask
Definition at line 920 of file gpio_reg.h.
| #define GPIO_DBCTL_DBCLKSEL_Pos (0) |
GPIO_T::DBCTL: DBCLKSEL Position
Definition at line 919 of file gpio_reg.h.
| #define GPIO_DBCTL_DBCLKSRC_Msk (1ul << GPIO_DBCTL_DBCLKSRC_Pos) |
GPIO_T::DBCTL: DBCLKSRC Mask
Definition at line 923 of file gpio_reg.h.
| #define GPIO_DBCTL_DBCLKSRC_Pos (4) |
GPIO_T::DBCTL: DBCLKSRC Position
Definition at line 922 of file gpio_reg.h.
| #define GPIO_DBCTL_ICLKON_Msk (1ul << GPIO_DBCTL_ICLKON_Pos) |
GPIO_T::DBCTL: ICLKON Mask
Definition at line 926 of file gpio_reg.h.
| #define GPIO_DBCTL_ICLKON_Pos (5) |
GPIO_T::DBCTL: ICLKON Position
Definition at line 925 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN0_Msk (0x1ul << GPIO_DBEN_DBEN0_Pos) |
GPIO_T::DBEN: DBEN0 Mask
Definition at line 536 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN0_Pos (0) |
GPIO_T::DBEN: DBEN0 Position
Definition at line 535 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN10_Msk (0x1ul << GPIO_DBEN_DBEN10_Pos) |
GPIO_T::DBEN: DBEN10 Mask
Definition at line 566 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN10_Pos (10) |
GPIO_T::DBEN: DBEN10 Position
Definition at line 565 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN11_Msk (0x1ul << GPIO_DBEN_DBEN11_Pos) |
GPIO_T::DBEN: DBEN11 Mask
Definition at line 569 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN11_Pos (11) |
GPIO_T::DBEN: DBEN11 Position
Definition at line 568 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN12_Msk (0x1ul << GPIO_DBEN_DBEN12_Pos) |
GPIO_T::DBEN: DBEN12 Mask
Definition at line 572 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN12_Pos (12) |
GPIO_T::DBEN: DBEN12 Position
Definition at line 571 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN13_Msk (0x1ul << GPIO_DBEN_DBEN13_Pos) |
GPIO_T::DBEN: DBEN13 Mask
Definition at line 575 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN13_Pos (13) |
GPIO_T::DBEN: DBEN13 Position
Definition at line 574 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN14_Msk (0x1ul << GPIO_DBEN_DBEN14_Pos) |
GPIO_T::DBEN: DBEN14 Mask
Definition at line 578 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN14_Pos (14) |
GPIO_T::DBEN: DBEN14 Position
Definition at line 577 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN15_Msk (0x1ul << GPIO_DBEN_DBEN15_Pos) |
GPIO_T::DBEN: DBEN15 Mask
Definition at line 581 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN15_Pos (15) |
GPIO_T::DBEN: DBEN15 Position
Definition at line 580 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN1_Msk (0x1ul << GPIO_DBEN_DBEN1_Pos) |
GPIO_T::DBEN: DBEN1 Mask
Definition at line 539 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN1_Pos (1) |
GPIO_T::DBEN: DBEN1 Position
Definition at line 538 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN2_Msk (0x1ul << GPIO_DBEN_DBEN2_Pos) |
GPIO_T::DBEN: DBEN2 Mask
Definition at line 542 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN2_Pos (2) |
GPIO_T::DBEN: DBEN2 Position
Definition at line 541 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN3_Msk (0x1ul << GPIO_DBEN_DBEN3_Pos) |
GPIO_T::DBEN: DBEN3 Mask
Definition at line 545 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN3_Pos (3) |
GPIO_T::DBEN: DBEN3 Position
Definition at line 544 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN4_Msk (0x1ul << GPIO_DBEN_DBEN4_Pos) |
GPIO_T::DBEN: DBEN4 Mask
Definition at line 548 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN4_Pos (4) |
GPIO_T::DBEN: DBEN4 Position
Definition at line 547 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN5_Msk (0x1ul << GPIO_DBEN_DBEN5_Pos) |
GPIO_T::DBEN: DBEN5 Mask
Definition at line 551 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN5_Pos (5) |
GPIO_T::DBEN: DBEN5 Position
Definition at line 550 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN6_Msk (0x1ul << GPIO_DBEN_DBEN6_Pos) |
GPIO_T::DBEN: DBEN6 Mask
Definition at line 554 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN6_Pos (6) |
GPIO_T::DBEN: DBEN6 Position
Definition at line 553 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN7_Msk (0x1ul << GPIO_DBEN_DBEN7_Pos) |
GPIO_T::DBEN: DBEN7 Mask
Definition at line 557 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN7_Pos (7) |
GPIO_T::DBEN: DBEN7 Position
Definition at line 556 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN8_Msk (0x1ul << GPIO_DBEN_DBEN8_Pos) |
GPIO_T::DBEN: DBEN8 Mask
Definition at line 560 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN8_Pos (8) |
GPIO_T::DBEN: DBEN8 Position
Definition at line 559 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN9_Msk (0x1ul << GPIO_DBEN_DBEN9_Pos) |
GPIO_T::DBEN: DBEN9 Mask
Definition at line 563 of file gpio_reg.h.
| #define GPIO_DBEN_DBEN9_Pos (9) |
GPIO_T::DBEN: DBEN9 Position
Definition at line 562 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF0_Msk (0x1ul << GPIO_DINOFF_DINOFF0_Pos) |
GPIO_T::DINOFF: DINOFF0 Mask
Definition at line 344 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF0_Pos (16) |
GPIO_T::DINOFF: DINOFF0 Position
Definition at line 343 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF10_Msk (0x1ul << GPIO_DINOFF_DINOFF10_Pos) |
GPIO_T::DINOFF: DINOFF10 Mask
Definition at line 374 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF10_Pos (26) |
GPIO_T::DINOFF: DINOFF10 Position
Definition at line 373 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF11_Msk (0x1ul << GPIO_DINOFF_DINOFF11_Pos) |
GPIO_T::DINOFF: DINOFF11 Mask
Definition at line 377 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF11_Pos (27) |
GPIO_T::DINOFF: DINOFF11 Position
Definition at line 376 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF12_Msk (0x1ul << GPIO_DINOFF_DINOFF12_Pos) |
GPIO_T::DINOFF: DINOFF12 Mask
Definition at line 380 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF12_Pos (28) |
GPIO_T::DINOFF: DINOFF12 Position
Definition at line 379 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF13_Msk (0x1ul << GPIO_DINOFF_DINOFF13_Pos) |
GPIO_T::DINOFF: DINOFF13 Mask
Definition at line 383 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF13_Pos (29) |
GPIO_T::DINOFF: DINOFF13 Position
Definition at line 382 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF14_Msk (0x1ul << GPIO_DINOFF_DINOFF14_Pos) |
GPIO_T::DINOFF: DINOFF14 Mask
Definition at line 386 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF14_Pos (30) |
GPIO_T::DINOFF: DINOFF14 Position
Definition at line 385 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF15_Msk (0x1ul << GPIO_DINOFF_DINOFF15_Pos) |
GPIO_T::DINOFF: DINOFF15 Mask
Definition at line 389 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF15_Pos (31) |
GPIO_T::DINOFF: DINOFF15 Position
Definition at line 388 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF1_Msk (0x1ul << GPIO_DINOFF_DINOFF1_Pos) |
GPIO_T::DINOFF: DINOFF1 Mask
Definition at line 347 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF1_Pos (17) |
GPIO_T::DINOFF: DINOFF1 Position
Definition at line 346 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF2_Msk (0x1ul << GPIO_DINOFF_DINOFF2_Pos) |
GPIO_T::DINOFF: DINOFF2 Mask
Definition at line 350 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF2_Pos (18) |
GPIO_T::DINOFF: DINOFF2 Position
Definition at line 349 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF3_Msk (0x1ul << GPIO_DINOFF_DINOFF3_Pos) |
GPIO_T::DINOFF: DINOFF3 Mask
Definition at line 353 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF3_Pos (19) |
GPIO_T::DINOFF: DINOFF3 Position
Definition at line 352 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF4_Msk (0x1ul << GPIO_DINOFF_DINOFF4_Pos) |
GPIO_T::DINOFF: DINOFF4 Mask
Definition at line 356 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF4_Pos (20) |
GPIO_T::DINOFF: DINOFF4 Position
Definition at line 355 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF5_Msk (0x1ul << GPIO_DINOFF_DINOFF5_Pos) |
GPIO_T::DINOFF: DINOFF5 Mask
Definition at line 359 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF5_Pos (21) |
GPIO_T::DINOFF: DINOFF5 Position
Definition at line 358 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF6_Msk (0x1ul << GPIO_DINOFF_DINOFF6_Pos) |
GPIO_T::DINOFF: DINOFF6 Mask
Definition at line 362 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF6_Pos (22) |
GPIO_T::DINOFF: DINOFF6 Position
Definition at line 361 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF7_Msk (0x1ul << GPIO_DINOFF_DINOFF7_Pos) |
GPIO_T::DINOFF: DINOFF7 Mask
Definition at line 365 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF7_Pos (23) |
GPIO_T::DINOFF: DINOFF7 Position
Definition at line 364 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF8_Msk (0x1ul << GPIO_DINOFF_DINOFF8_Pos) |
GPIO_T::DINOFF: DINOFF8 Mask
Definition at line 368 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF8_Pos (24) |
GPIO_T::DINOFF: DINOFF8 Position
Definition at line 367 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF9_Msk (0x1ul << GPIO_DINOFF_DINOFF9_Pos) |
GPIO_T::DINOFF: DINOFF9 Mask
Definition at line 371 of file gpio_reg.h.
| #define GPIO_DINOFF_DINOFF9_Pos (25) |
GPIO_T::DINOFF: DINOFF9 Position
Definition at line 370 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT0_Msk (0x1ul << GPIO_DOUT_DOUT0_Pos) |
GPIO_T::DOUT: DOUT0 Mask
Definition at line 392 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT0_Pos (0) |
GPIO_T::DOUT: DOUT0 Position
Definition at line 391 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT10_Msk (0x1ul << GPIO_DOUT_DOUT10_Pos) |
GPIO_T::DOUT: DOUT10 Mask
Definition at line 422 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT10_Pos (10) |
GPIO_T::DOUT: DOUT10 Position
Definition at line 421 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT11_Msk (0x1ul << GPIO_DOUT_DOUT11_Pos) |
GPIO_T::DOUT: DOUT11 Mask
Definition at line 425 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT11_Pos (11) |
GPIO_T::DOUT: DOUT11 Position
Definition at line 424 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT12_Msk (0x1ul << GPIO_DOUT_DOUT12_Pos) |
GPIO_T::DOUT: DOUT12 Mask
Definition at line 428 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT12_Pos (12) |
GPIO_T::DOUT: DOUT12 Position
Definition at line 427 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT13_Msk (0x1ul << GPIO_DOUT_DOUT13_Pos) |
GPIO_T::DOUT: DOUT13 Mask
Definition at line 431 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT13_Pos (13) |
GPIO_T::DOUT: DOUT13 Position
Definition at line 430 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT14_Msk (0x1ul << GPIO_DOUT_DOUT14_Pos) |
GPIO_T::DOUT: DOUT14 Mask
Definition at line 434 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT14_Pos (14) |
GPIO_T::DOUT: DOUT14 Position
Definition at line 433 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT15_Msk (0x1ul << GPIO_DOUT_DOUT15_Pos) |
GPIO_T::DOUT: DOUT15 Mask
Definition at line 437 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT15_Pos (15) |
GPIO_T::DOUT: DOUT15 Position
Definition at line 436 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT1_Msk (0x1ul << GPIO_DOUT_DOUT1_Pos) |
GPIO_T::DOUT: DOUT1 Mask
Definition at line 395 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT1_Pos (1) |
GPIO_T::DOUT: DOUT1 Position
Definition at line 394 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT2_Msk (0x1ul << GPIO_DOUT_DOUT2_Pos) |
GPIO_T::DOUT: DOUT2 Mask
Definition at line 398 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT2_Pos (2) |
GPIO_T::DOUT: DOUT2 Position
Definition at line 397 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT3_Msk (0x1ul << GPIO_DOUT_DOUT3_Pos) |
GPIO_T::DOUT: DOUT3 Mask
Definition at line 401 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT3_Pos (3) |
GPIO_T::DOUT: DOUT3 Position
Definition at line 400 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT4_Msk (0x1ul << GPIO_DOUT_DOUT4_Pos) |
GPIO_T::DOUT: DOUT4 Mask
Definition at line 404 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT4_Pos (4) |
GPIO_T::DOUT: DOUT4 Position
Definition at line 403 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT5_Msk (0x1ul << GPIO_DOUT_DOUT5_Pos) |
GPIO_T::DOUT: DOUT5 Mask
Definition at line 407 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT5_Pos (5) |
GPIO_T::DOUT: DOUT5 Position
Definition at line 406 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT6_Msk (0x1ul << GPIO_DOUT_DOUT6_Pos) |
GPIO_T::DOUT: DOUT6 Mask
Definition at line 410 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT6_Pos (6) |
GPIO_T::DOUT: DOUT6 Position
Definition at line 409 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT7_Msk (0x1ul << GPIO_DOUT_DOUT7_Pos) |
GPIO_T::DOUT: DOUT7 Mask
Definition at line 413 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT7_Pos (7) |
GPIO_T::DOUT: DOUT7 Position
Definition at line 412 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT8_Msk (0x1ul << GPIO_DOUT_DOUT8_Pos) |
GPIO_T::DOUT: DOUT8 Mask
Definition at line 416 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT8_Pos (8) |
GPIO_T::DOUT: DOUT8 Position
Definition at line 415 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT9_Msk (0x1ul << GPIO_DOUT_DOUT9_Pos) |
GPIO_T::DOUT: DOUT9 Mask
Definition at line 419 of file gpio_reg.h.
| #define GPIO_DOUT_DOUT9_Pos (9) |
GPIO_T::DOUT: DOUT9 Position
Definition at line 418 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN0_Msk (0x1ul << GPIO_INTEN_FLIEN0_Pos) |
GPIO_T::INTEN: FLIEN0 Mask
Definition at line 632 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN0_Pos (0) |
GPIO_T::INTEN: FLIEN0 Position
Definition at line 631 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN10_Msk (0x1ul << GPIO_INTEN_FLIEN10_Pos) |
GPIO_T::INTEN: FLIEN10 Mask
Definition at line 662 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN10_Pos (10) |
GPIO_T::INTEN: FLIEN10 Position
Definition at line 661 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN11_Msk (0x1ul << GPIO_INTEN_FLIEN11_Pos) |
GPIO_T::INTEN: FLIEN11 Mask
Definition at line 665 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN11_Pos (11) |
GPIO_T::INTEN: FLIEN11 Position
Definition at line 664 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN12_Msk (0x1ul << GPIO_INTEN_FLIEN12_Pos) |
GPIO_T::INTEN: FLIEN12 Mask
Definition at line 668 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN12_Pos (12) |
GPIO_T::INTEN: FLIEN12 Position
Definition at line 667 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN13_Msk (0x1ul << GPIO_INTEN_FLIEN13_Pos) |
GPIO_T::INTEN: FLIEN13 Mask
Definition at line 671 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN13_Pos (13) |
GPIO_T::INTEN: FLIEN13 Position
Definition at line 670 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN14_Msk (0x1ul << GPIO_INTEN_FLIEN14_Pos) |
GPIO_T::INTEN: FLIEN14 Mask
Definition at line 674 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN14_Pos (14) |
GPIO_T::INTEN: FLIEN14 Position
Definition at line 673 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN15_Msk (0x1ul << GPIO_INTEN_FLIEN15_Pos) |
GPIO_T::INTEN: FLIEN15 Mask
Definition at line 677 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN15_Pos (15) |
GPIO_T::INTEN: FLIEN15 Position
Definition at line 676 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN1_Msk (0x1ul << GPIO_INTEN_FLIEN1_Pos) |
GPIO_T::INTEN: FLIEN1 Mask
Definition at line 635 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN1_Pos (1) |
GPIO_T::INTEN: FLIEN1 Position
Definition at line 634 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN2_Msk (0x1ul << GPIO_INTEN_FLIEN2_Pos) |
GPIO_T::INTEN: FLIEN2 Mask
Definition at line 638 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN2_Pos (2) |
GPIO_T::INTEN: FLIEN2 Position
Definition at line 637 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN3_Msk (0x1ul << GPIO_INTEN_FLIEN3_Pos) |
GPIO_T::INTEN: FLIEN3 Mask
Definition at line 641 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN3_Pos (3) |
GPIO_T::INTEN: FLIEN3 Position
Definition at line 640 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN4_Msk (0x1ul << GPIO_INTEN_FLIEN4_Pos) |
GPIO_T::INTEN: FLIEN4 Mask
Definition at line 644 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN4_Pos (4) |
GPIO_T::INTEN: FLIEN4 Position
Definition at line 643 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN5_Msk (0x1ul << GPIO_INTEN_FLIEN5_Pos) |
GPIO_T::INTEN: FLIEN5 Mask
Definition at line 647 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN5_Pos (5) |
GPIO_T::INTEN: FLIEN5 Position
Definition at line 646 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN6_Msk (0x1ul << GPIO_INTEN_FLIEN6_Pos) |
GPIO_T::INTEN: FLIEN6 Mask
Definition at line 650 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN6_Pos (6) |
GPIO_T::INTEN: FLIEN6 Position
Definition at line 649 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN7_Msk (0x1ul << GPIO_INTEN_FLIEN7_Pos) |
GPIO_T::INTEN: FLIEN7 Mask
Definition at line 653 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN7_Pos (7) |
GPIO_T::INTEN: FLIEN7 Position
Definition at line 652 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN8_Msk (0x1ul << GPIO_INTEN_FLIEN8_Pos) |
GPIO_T::INTEN: FLIEN8 Mask
Definition at line 656 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN8_Pos (8) |
GPIO_T::INTEN: FLIEN8 Position
Definition at line 655 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN9_Msk (0x1ul << GPIO_INTEN_FLIEN9_Pos) |
GPIO_T::INTEN: FLIEN9 Mask
Definition at line 659 of file gpio_reg.h.
| #define GPIO_INTEN_FLIEN9_Pos (9) |
GPIO_T::INTEN: FLIEN9 Position
Definition at line 658 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN0_Msk (0x1ul << GPIO_INTEN_RHIEN0_Pos) |
GPIO_T::INTEN: RHIEN0 Mask
Definition at line 680 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN0_Pos (16) |
GPIO_T::INTEN: RHIEN0 Position
Definition at line 679 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN10_Msk (0x1ul << GPIO_INTEN_RHIEN10_Pos) |
GPIO_T::INTEN: RHIEN10 Mask
Definition at line 710 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN10_Pos (26) |
GPIO_T::INTEN: RHIEN10 Position
Definition at line 709 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN11_Msk (0x1ul << GPIO_INTEN_RHIEN11_Pos) |
GPIO_T::INTEN: RHIEN11 Mask
Definition at line 713 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN11_Pos (27) |
GPIO_T::INTEN: RHIEN11 Position
Definition at line 712 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN12_Msk (0x1ul << GPIO_INTEN_RHIEN12_Pos) |
GPIO_T::INTEN: RHIEN12 Mask
Definition at line 716 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN12_Pos (28) |
GPIO_T::INTEN: RHIEN12 Position
Definition at line 715 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN13_Msk (0x1ul << GPIO_INTEN_RHIEN13_Pos) |
GPIO_T::INTEN: RHIEN13 Mask
Definition at line 719 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN13_Pos (29) |
GPIO_T::INTEN: RHIEN13 Position
Definition at line 718 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN14_Msk (0x1ul << GPIO_INTEN_RHIEN14_Pos) |
GPIO_T::INTEN: RHIEN14 Mask
Definition at line 722 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN14_Pos (30) |
GPIO_T::INTEN: RHIEN14 Position
Definition at line 721 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN15_Msk (0x1ul << GPIO_INTEN_RHIEN15_Pos) |
GPIO_T::INTEN: RHIEN15 Mask
Definition at line 725 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN15_Pos (31) |
GPIO_T::INTEN: RHIEN15 Position
Definition at line 724 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN1_Msk (0x1ul << GPIO_INTEN_RHIEN1_Pos) |
GPIO_T::INTEN: RHIEN1 Mask
Definition at line 683 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN1_Pos (17) |
GPIO_T::INTEN: RHIEN1 Position
Definition at line 682 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN2_Msk (0x1ul << GPIO_INTEN_RHIEN2_Pos) |
GPIO_T::INTEN: RHIEN2 Mask
Definition at line 686 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN2_Pos (18) |
GPIO_T::INTEN: RHIEN2 Position
Definition at line 685 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN3_Msk (0x1ul << GPIO_INTEN_RHIEN3_Pos) |
GPIO_T::INTEN: RHIEN3 Mask
Definition at line 689 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN3_Pos (19) |
GPIO_T::INTEN: RHIEN3 Position
Definition at line 688 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN4_Msk (0x1ul << GPIO_INTEN_RHIEN4_Pos) |
GPIO_T::INTEN: RHIEN4 Mask
Definition at line 692 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN4_Pos (20) |
GPIO_T::INTEN: RHIEN4 Position
Definition at line 691 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN5_Msk (0x1ul << GPIO_INTEN_RHIEN5_Pos) |
GPIO_T::INTEN: RHIEN5 Mask
Definition at line 695 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN5_Pos (21) |
GPIO_T::INTEN: RHIEN5 Position
Definition at line 694 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN6_Msk (0x1ul << GPIO_INTEN_RHIEN6_Pos) |
GPIO_T::INTEN: RHIEN6 Mask
Definition at line 698 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN6_Pos (22) |
GPIO_T::INTEN: RHIEN6 Position
Definition at line 697 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN7_Msk (0x1ul << GPIO_INTEN_RHIEN7_Pos) |
GPIO_T::INTEN: RHIEN7 Mask
Definition at line 701 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN7_Pos (23) |
GPIO_T::INTEN: RHIEN7 Position
Definition at line 700 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN8_Msk (0x1ul << GPIO_INTEN_RHIEN8_Pos) |
GPIO_T::INTEN: RHIEN8 Mask
Definition at line 704 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN8_Pos (24) |
GPIO_T::INTEN: RHIEN8 Position
Definition at line 703 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN9_Msk (0x1ul << GPIO_INTEN_RHIEN9_Pos) |
GPIO_T::INTEN: RHIEN9 Mask
Definition at line 707 of file gpio_reg.h.
| #define GPIO_INTEN_RHIEN9_Pos (25) |
GPIO_T::INTEN: RHIEN9 Position
Definition at line 706 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC0_Msk (0x1ul << GPIO_INTSRC_INTSRC0_Pos) |
GPIO_T::INTSRC: INTSRC0 Mask
Definition at line 728 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC0_Pos (0) |
GPIO_T::INTSRC: INTSRC0 Position
Definition at line 727 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC10_Msk (0x1ul << GPIO_INTSRC_INTSRC10_Pos) |
GPIO_T::INTSRC: INTSRC10 Mask
Definition at line 758 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC10_Pos (10) |
GPIO_T::INTSRC: INTSRC10 Position
Definition at line 757 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC11_Msk (0x1ul << GPIO_INTSRC_INTSRC11_Pos) |
GPIO_T::INTSRC: INTSRC11 Mask
Definition at line 761 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC11_Pos (11) |
GPIO_T::INTSRC: INTSRC11 Position
Definition at line 760 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC12_Msk (0x1ul << GPIO_INTSRC_INTSRC12_Pos) |
GPIO_T::INTSRC: INTSRC12 Mask
Definition at line 764 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC12_Pos (12) |
GPIO_T::INTSRC: INTSRC12 Position
Definition at line 763 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC13_Msk (0x1ul << GPIO_INTSRC_INTSRC13_Pos) |
GPIO_T::INTSRC: INTSRC13 Mask
Definition at line 767 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC13_Pos (13) |
GPIO_T::INTSRC: INTSRC13 Position
Definition at line 766 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC14_Msk (0x1ul << GPIO_INTSRC_INTSRC14_Pos) |
GPIO_T::INTSRC: INTSRC14 Mask
Definition at line 770 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC14_Pos (14) |
GPIO_T::INTSRC: INTSRC14 Position
Definition at line 769 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC15_Msk (0x1ul << GPIO_INTSRC_INTSRC15_Pos) |
GPIO_T::INTSRC: INTSRC15 Mask
Definition at line 773 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC15_Pos (15) |
GPIO_T::INTSRC: INTSRC15 Position
Definition at line 772 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC1_Msk (0x1ul << GPIO_INTSRC_INTSRC1_Pos) |
GPIO_T::INTSRC: INTSRC1 Mask
Definition at line 731 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC1_Pos (1) |
GPIO_T::INTSRC: INTSRC1 Position
Definition at line 730 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC2_Msk (0x1ul << GPIO_INTSRC_INTSRC2_Pos) |
GPIO_T::INTSRC: INTSRC2 Mask
Definition at line 734 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC2_Pos (2) |
GPIO_T::INTSRC: INTSRC2 Position
Definition at line 733 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC3_Msk (0x1ul << GPIO_INTSRC_INTSRC3_Pos) |
GPIO_T::INTSRC: INTSRC3 Mask
Definition at line 737 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC3_Pos (3) |
GPIO_T::INTSRC: INTSRC3 Position
Definition at line 736 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC4_Msk (0x1ul << GPIO_INTSRC_INTSRC4_Pos) |
GPIO_T::INTSRC: INTSRC4 Mask
Definition at line 740 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC4_Pos (4) |
GPIO_T::INTSRC: INTSRC4 Position
Definition at line 739 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC5_Msk (0x1ul << GPIO_INTSRC_INTSRC5_Pos) |
GPIO_T::INTSRC: INTSRC5 Mask
Definition at line 743 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC5_Pos (5) |
GPIO_T::INTSRC: INTSRC5 Position
Definition at line 742 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC6_Msk (0x1ul << GPIO_INTSRC_INTSRC6_Pos) |
GPIO_T::INTSRC: INTSRC6 Mask
Definition at line 746 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC6_Pos (6) |
GPIO_T::INTSRC: INTSRC6 Position
Definition at line 745 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC7_Msk (0x1ul << GPIO_INTSRC_INTSRC7_Pos) |
GPIO_T::INTSRC: INTSRC7 Mask
Definition at line 749 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC7_Pos (7) |
GPIO_T::INTSRC: INTSRC7 Position
Definition at line 748 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC8_Msk (0x1ul << GPIO_INTSRC_INTSRC8_Pos) |
GPIO_T::INTSRC: INTSRC8 Mask
Definition at line 752 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC8_Pos (8) |
GPIO_T::INTSRC: INTSRC8 Position
Definition at line 751 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC9_Msk (0x1ul << GPIO_INTSRC_INTSRC9_Pos) |
GPIO_T::INTSRC: INTSRC9 Mask
Definition at line 755 of file gpio_reg.h.
| #define GPIO_INTSRC_INTSRC9_Pos (9) |
GPIO_T::INTSRC: INTSRC9 Position
Definition at line 754 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE0_Msk (0x1ul << GPIO_INTTYPE_TYPE0_Pos) |
GPIO_T::INTTYPE: TYPE0 Mask
Definition at line 584 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE0_Pos (0) |
GPIO_T::INTTYPE: TYPE0 Position
Definition at line 583 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE10_Msk (0x1ul << GPIO_INTTYPE_TYPE10_Pos) |
GPIO_T::INTTYPE: TYPE10 Mask
Definition at line 614 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE10_Pos (10) |
GPIO_T::INTTYPE: TYPE10 Position
Definition at line 613 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE11_Msk (0x1ul << GPIO_INTTYPE_TYPE11_Pos) |
GPIO_T::INTTYPE: TYPE11 Mask
Definition at line 617 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE11_Pos (11) |
GPIO_T::INTTYPE: TYPE11 Position
Definition at line 616 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE12_Msk (0x1ul << GPIO_INTTYPE_TYPE12_Pos) |
GPIO_T::INTTYPE: TYPE12 Mask
Definition at line 620 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE12_Pos (12) |
GPIO_T::INTTYPE: TYPE12 Position
Definition at line 619 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE13_Msk (0x1ul << GPIO_INTTYPE_TYPE13_Pos) |
GPIO_T::INTTYPE: TYPE13 Mask
Definition at line 623 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE13_Pos (13) |
GPIO_T::INTTYPE: TYPE13 Position
Definition at line 622 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE14_Msk (0x1ul << GPIO_INTTYPE_TYPE14_Pos) |
GPIO_T::INTTYPE: TYPE14 Mask
Definition at line 626 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE14_Pos (14) |
GPIO_T::INTTYPE: TYPE14 Position
Definition at line 625 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE15_Msk (0x1ul << GPIO_INTTYPE_TYPE15_Pos) |
GPIO_T::INTTYPE: TYPE15 Mask
Definition at line 629 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE15_Pos (15) |
GPIO_T::INTTYPE: TYPE15 Position
Definition at line 628 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE1_Msk (0x1ul << GPIO_INTTYPE_TYPE1_Pos) |
GPIO_T::INTTYPE: TYPE1 Mask
Definition at line 587 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE1_Pos (1) |
GPIO_T::INTTYPE: TYPE1 Position
Definition at line 586 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE2_Msk (0x1ul << GPIO_INTTYPE_TYPE2_Pos) |
GPIO_T::INTTYPE: TYPE2 Mask
Definition at line 590 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE2_Pos (2) |
GPIO_T::INTTYPE: TYPE2 Position
Definition at line 589 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE3_Msk (0x1ul << GPIO_INTTYPE_TYPE3_Pos) |
GPIO_T::INTTYPE: TYPE3 Mask
Definition at line 593 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE3_Pos (3) |
GPIO_T::INTTYPE: TYPE3 Position
Definition at line 592 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE4_Msk (0x1ul << GPIO_INTTYPE_TYPE4_Pos) |
GPIO_T::INTTYPE: TYPE4 Mask
Definition at line 596 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE4_Pos (4) |
GPIO_T::INTTYPE: TYPE4 Position
Definition at line 595 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE5_Msk (0x1ul << GPIO_INTTYPE_TYPE5_Pos) |
GPIO_T::INTTYPE: TYPE5 Mask
Definition at line 599 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE5_Pos (5) |
GPIO_T::INTTYPE: TYPE5 Position
Definition at line 598 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE6_Msk (0x1ul << GPIO_INTTYPE_TYPE6_Pos) |
GPIO_T::INTTYPE: TYPE6 Mask
Definition at line 602 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE6_Pos (6) |
GPIO_T::INTTYPE: TYPE6 Position
Definition at line 601 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE7_Msk (0x1ul << GPIO_INTTYPE_TYPE7_Pos) |
GPIO_T::INTTYPE: TYPE7 Mask
Definition at line 605 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE7_Pos (7) |
GPIO_T::INTTYPE: TYPE7 Position
Definition at line 604 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE8_Msk (0x1ul << GPIO_INTTYPE_TYPE8_Pos) |
GPIO_T::INTTYPE: TYPE8 Mask
Definition at line 608 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE8_Pos (8) |
GPIO_T::INTTYPE: TYPE8 Position
Definition at line 607 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE9_Msk (0x1ul << GPIO_INTTYPE_TYPE9_Pos) |
GPIO_T::INTTYPE: TYPE9 Mask
Definition at line 611 of file gpio_reg.h.
| #define GPIO_INTTYPE_TYPE9_Pos (9) |
GPIO_T::INTTYPE: TYPE9 Position
Definition at line 610 of file gpio_reg.h.
| #define GPIO_MODE_MODE0_Msk (0x3ul << GPIO_MODE_MODE0_Pos) |
GPIO_T::MODE: MODE0 Mask
Definition at line 296 of file gpio_reg.h.
| #define GPIO_MODE_MODE0_Pos (0) |
@addtogroup GPIO_CONST GPIO Bit Field Definition Constant Definitions for GPIO Controller
GPIO_T::MODE: MODE0 Position
Definition at line 295 of file gpio_reg.h.
| #define GPIO_MODE_MODE10_Msk (0x3ul << GPIO_MODE_MODE10_Pos) |
GPIO_T::MODE: MODE10 Mask
Definition at line 326 of file gpio_reg.h.
| #define GPIO_MODE_MODE10_Pos (20) |
GPIO_T::MODE: MODE10 Position
Definition at line 325 of file gpio_reg.h.
| #define GPIO_MODE_MODE11_Msk (0x3ul << GPIO_MODE_MODE11_Pos) |
GPIO_T::MODE: MODE11 Mask
Definition at line 329 of file gpio_reg.h.
| #define GPIO_MODE_MODE11_Pos (22) |
GPIO_T::MODE: MODE11 Position
Definition at line 328 of file gpio_reg.h.
| #define GPIO_MODE_MODE12_Msk (0x3ul << GPIO_MODE_MODE12_Pos) |
GPIO_T::MODE: MODE12 Mask
Definition at line 332 of file gpio_reg.h.
| #define GPIO_MODE_MODE12_Pos (24) |
GPIO_T::MODE: MODE12 Position
Definition at line 331 of file gpio_reg.h.
| #define GPIO_MODE_MODE13_Msk (0x3ul << GPIO_MODE_MODE13_Pos) |
GPIO_T::MODE: MODE13 Mask
Definition at line 335 of file gpio_reg.h.
| #define GPIO_MODE_MODE13_Pos (26) |
GPIO_T::MODE: MODE13 Position
Definition at line 334 of file gpio_reg.h.
| #define GPIO_MODE_MODE14_Msk (0x3ul << GPIO_MODE_MODE14_Pos) |
GPIO_T::MODE: MODE14 Mask
Definition at line 338 of file gpio_reg.h.
| #define GPIO_MODE_MODE14_Pos (28) |
GPIO_T::MODE: MODE14 Position
Definition at line 337 of file gpio_reg.h.
| #define GPIO_MODE_MODE15_Msk (0x3ul << GPIO_MODE_MODE15_Pos) |
GPIO_T::MODE: MODE15 Mask
Definition at line 341 of file gpio_reg.h.
| #define GPIO_MODE_MODE15_Pos (30) |
GPIO_T::MODE: MODE15 Position
Definition at line 340 of file gpio_reg.h.
| #define GPIO_MODE_MODE1_Msk (0x3ul << GPIO_MODE_MODE1_Pos) |
GPIO_T::MODE: MODE1 Mask
Definition at line 299 of file gpio_reg.h.
| #define GPIO_MODE_MODE1_Pos (2) |
GPIO_T::MODE: MODE1 Position
Definition at line 298 of file gpio_reg.h.
| #define GPIO_MODE_MODE2_Msk (0x3ul << GPIO_MODE_MODE2_Pos) |
GPIO_T::MODE: MODE2 Mask
Definition at line 302 of file gpio_reg.h.
| #define GPIO_MODE_MODE2_Pos (4) |
GPIO_T::MODE: MODE2 Position
Definition at line 301 of file gpio_reg.h.
| #define GPIO_MODE_MODE3_Msk (0x3ul << GPIO_MODE_MODE3_Pos) |
GPIO_T::MODE: MODE3 Mask
Definition at line 305 of file gpio_reg.h.
| #define GPIO_MODE_MODE3_Pos (6) |
GPIO_T::MODE: MODE3 Position
Definition at line 304 of file gpio_reg.h.
| #define GPIO_MODE_MODE4_Msk (0x3ul << GPIO_MODE_MODE4_Pos) |
GPIO_T::MODE: MODE4 Mask
Definition at line 308 of file gpio_reg.h.
| #define GPIO_MODE_MODE4_Pos (8) |
GPIO_T::MODE: MODE4 Position
Definition at line 307 of file gpio_reg.h.
| #define GPIO_MODE_MODE5_Msk (0x3ul << GPIO_MODE_MODE5_Pos) |
GPIO_T::MODE: MODE5 Mask
Definition at line 311 of file gpio_reg.h.
| #define GPIO_MODE_MODE5_Pos (10) |
GPIO_T::MODE: MODE5 Position
Definition at line 310 of file gpio_reg.h.
| #define GPIO_MODE_MODE6_Msk (0x3ul << GPIO_MODE_MODE6_Pos) |
GPIO_T::MODE: MODE6 Mask
Definition at line 314 of file gpio_reg.h.
| #define GPIO_MODE_MODE6_Pos (12) |
GPIO_T::MODE: MODE6 Position
Definition at line 313 of file gpio_reg.h.
| #define GPIO_MODE_MODE7_Msk (0x3ul << GPIO_MODE_MODE7_Pos) |
GPIO_T::MODE: MODE7 Mask
Definition at line 317 of file gpio_reg.h.
| #define GPIO_MODE_MODE7_Pos (14) |
GPIO_T::MODE: MODE7 Position
Definition at line 316 of file gpio_reg.h.
| #define GPIO_MODE_MODE8_Msk (0x3ul << GPIO_MODE_MODE8_Pos) |
GPIO_T::MODE: MODE8 Mask
Definition at line 320 of file gpio_reg.h.
| #define GPIO_MODE_MODE8_Pos (16) |
GPIO_T::MODE: MODE8 Position
Definition at line 319 of file gpio_reg.h.
| #define GPIO_MODE_MODE9_Msk (0x3ul << GPIO_MODE_MODE9_Pos) |
GPIO_T::MODE: MODE9 Mask
Definition at line 323 of file gpio_reg.h.
| #define GPIO_MODE_MODE9_Pos (18) |
GPIO_T::MODE: MODE9 Position
Definition at line 322 of file gpio_reg.h.
| #define GPIO_PIN_PIN0_Msk (0x1ul << GPIO_PIN_PIN0_Pos) |
GPIO_T::PIN: PIN0 Mask
Definition at line 488 of file gpio_reg.h.
| #define GPIO_PIN_PIN0_Pos (0) |
GPIO_T::PIN: PIN0 Position
Definition at line 487 of file gpio_reg.h.
| #define GPIO_PIN_PIN10_Msk (0x1ul << GPIO_PIN_PIN10_Pos) |
GPIO_T::PIN: PIN10 Mask
Definition at line 518 of file gpio_reg.h.
| #define GPIO_PIN_PIN10_Pos (10) |
GPIO_T::PIN: PIN10 Position
Definition at line 517 of file gpio_reg.h.
| #define GPIO_PIN_PIN11_Msk (0x1ul << GPIO_PIN_PIN11_Pos) |
GPIO_T::PIN: PIN11 Mask
Definition at line 521 of file gpio_reg.h.
| #define GPIO_PIN_PIN11_Pos (11) |
GPIO_T::PIN: PIN11 Position
Definition at line 520 of file gpio_reg.h.
| #define GPIO_PIN_PIN12_Msk (0x1ul << GPIO_PIN_PIN12_Pos) |
GPIO_T::PIN: PIN12 Mask
Definition at line 524 of file gpio_reg.h.
| #define GPIO_PIN_PIN12_Pos (12) |
GPIO_T::PIN: PIN12 Position
Definition at line 523 of file gpio_reg.h.
| #define GPIO_PIN_PIN13_Msk (0x1ul << GPIO_PIN_PIN13_Pos) |
GPIO_T::PIN: PIN13 Mask
Definition at line 527 of file gpio_reg.h.
| #define GPIO_PIN_PIN13_Pos (13) |
GPIO_T::PIN: PIN13 Position
Definition at line 526 of file gpio_reg.h.
| #define GPIO_PIN_PIN14_Msk (0x1ul << GPIO_PIN_PIN14_Pos) |
GPIO_T::PIN: PIN14 Mask
Definition at line 530 of file gpio_reg.h.
| #define GPIO_PIN_PIN14_Pos (14) |
GPIO_T::PIN: PIN14 Position
Definition at line 529 of file gpio_reg.h.
| #define GPIO_PIN_PIN15_Msk (0x1ul << GPIO_PIN_PIN15_Pos) |
GPIO_T::PIN: PIN15 Mask
Definition at line 533 of file gpio_reg.h.
| #define GPIO_PIN_PIN15_Pos (15) |
GPIO_T::PIN: PIN15 Position
Definition at line 532 of file gpio_reg.h.
| #define GPIO_PIN_PIN1_Msk (0x1ul << GPIO_PIN_PIN1_Pos) |
GPIO_T::PIN: PIN1 Mask
Definition at line 491 of file gpio_reg.h.
| #define GPIO_PIN_PIN1_Pos (1) |
GPIO_T::PIN: PIN1 Position
Definition at line 490 of file gpio_reg.h.
| #define GPIO_PIN_PIN2_Msk (0x1ul << GPIO_PIN_PIN2_Pos) |
GPIO_T::PIN: PIN2 Mask
Definition at line 494 of file gpio_reg.h.
| #define GPIO_PIN_PIN2_Pos (2) |
GPIO_T::PIN: PIN2 Position
Definition at line 493 of file gpio_reg.h.
| #define GPIO_PIN_PIN3_Msk (0x1ul << GPIO_PIN_PIN3_Pos) |
GPIO_T::PIN: PIN3 Mask
Definition at line 497 of file gpio_reg.h.
| #define GPIO_PIN_PIN3_Pos (3) |
GPIO_T::PIN: PIN3 Position
Definition at line 496 of file gpio_reg.h.
| #define GPIO_PIN_PIN4_Msk (0x1ul << GPIO_PIN_PIN4_Pos) |
GPIO_T::PIN: PIN4 Mask
Definition at line 500 of file gpio_reg.h.
| #define GPIO_PIN_PIN4_Pos (4) |
GPIO_T::PIN: PIN4 Position
Definition at line 499 of file gpio_reg.h.
| #define GPIO_PIN_PIN5_Msk (0x1ul << GPIO_PIN_PIN5_Pos) |
GPIO_T::PIN: PIN5 Mask
Definition at line 503 of file gpio_reg.h.
| #define GPIO_PIN_PIN5_Pos (5) |
GPIO_T::PIN: PIN5 Position
Definition at line 502 of file gpio_reg.h.
| #define GPIO_PIN_PIN6_Msk (0x1ul << GPIO_PIN_PIN6_Pos) |
GPIO_T::PIN: PIN6 Mask
Definition at line 506 of file gpio_reg.h.
| #define GPIO_PIN_PIN6_Pos (6) |
GPIO_T::PIN: PIN6 Position
Definition at line 505 of file gpio_reg.h.
| #define GPIO_PIN_PIN7_Msk (0x1ul << GPIO_PIN_PIN7_Pos) |
GPIO_T::PIN: PIN7 Mask
Definition at line 509 of file gpio_reg.h.
| #define GPIO_PIN_PIN7_Pos (7) |
GPIO_T::PIN: PIN7 Position
Definition at line 508 of file gpio_reg.h.
| #define GPIO_PIN_PIN8_Msk (0x1ul << GPIO_PIN_PIN8_Pos) |
GPIO_T::PIN: PIN8 Mask
Definition at line 512 of file gpio_reg.h.
| #define GPIO_PIN_PIN8_Pos (8) |
GPIO_T::PIN: PIN8 Position
Definition at line 511 of file gpio_reg.h.
| #define GPIO_PIN_PIN9_Msk (0x1ul << GPIO_PIN_PIN9_Pos) |
GPIO_T::PIN: PIN9 Mask
Definition at line 515 of file gpio_reg.h.
| #define GPIO_PIN_PIN9_Pos (9) |
GPIO_T::PIN: PIN9 Position
Definition at line 514 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL0_Msk (0x3ul << GPIO_PUSEL_PUSEL0_Pos) |
GPIO_T::PUSEL: PUSEL0 Mask
Definition at line 872 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL0_Pos (0) |
GPIO_T::PUSEL: PUSEL0 Position
Definition at line 871 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL10_Msk (0x3ul << GPIO_PUSEL_PUSEL10_Pos) |
GPIO_T::PUSEL: PUSEL10 Mask
Definition at line 902 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL10_Pos (20) |
GPIO_T::PUSEL: PUSEL10 Position
Definition at line 901 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL11_Msk (0x3ul << GPIO_PUSEL_PUSEL11_Pos) |
GPIO_T::PUSEL: PUSEL11 Mask
Definition at line 905 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL11_Pos (22) |
GPIO_T::PUSEL: PUSEL11 Position
Definition at line 904 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL12_Msk (0x3ul << GPIO_PUSEL_PUSEL12_Pos) |
GPIO_T::PUSEL: PUSEL12 Mask
Definition at line 908 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL12_Pos (24) |
GPIO_T::PUSEL: PUSEL12 Position
Definition at line 907 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL13_Msk (0x3ul << GPIO_PUSEL_PUSEL13_Pos) |
GPIO_T::PUSEL: PUSEL13 Mask
Definition at line 911 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL13_Pos (26) |
GPIO_T::PUSEL: PUSEL13 Position
Definition at line 910 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL14_Msk (0x3ul << GPIO_PUSEL_PUSEL14_Pos) |
GPIO_T::PUSEL: PUSEL14 Mask
Definition at line 914 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL14_Pos (28) |
GPIO_T::PUSEL: PUSEL14 Position
Definition at line 913 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL15_Msk (0x3ul << GPIO_PUSEL_PUSEL15_Pos) |
GPIO_T::PUSEL: PUSEL15 Mask
Definition at line 917 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL15_Pos (30) |
GPIO_T::PUSEL: PUSEL15 Position
Definition at line 916 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL1_Msk (0x3ul << GPIO_PUSEL_PUSEL1_Pos) |
GPIO_T::PUSEL: PUSEL1 Mask
Definition at line 875 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL1_Pos (2) |
GPIO_T::PUSEL: PUSEL1 Position
Definition at line 874 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL2_Msk (0x3ul << GPIO_PUSEL_PUSEL2_Pos) |
GPIO_T::PUSEL: PUSEL2 Mask
Definition at line 878 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL2_Pos (4) |
GPIO_T::PUSEL: PUSEL2 Position
Definition at line 877 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL3_Msk (0x3ul << GPIO_PUSEL_PUSEL3_Pos) |
GPIO_T::PUSEL: PUSEL3 Mask
Definition at line 881 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL3_Pos (6) |
GPIO_T::PUSEL: PUSEL3 Position
Definition at line 880 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL4_Msk (0x3ul << GPIO_PUSEL_PUSEL4_Pos) |
GPIO_T::PUSEL: PUSEL4 Mask
Definition at line 884 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL4_Pos (8) |
GPIO_T::PUSEL: PUSEL4 Position
Definition at line 883 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL5_Msk (0x3ul << GPIO_PUSEL_PUSEL5_Pos) |
GPIO_T::PUSEL: PUSEL5 Mask
Definition at line 887 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL5_Pos (10) |
GPIO_T::PUSEL: PUSEL5 Position
Definition at line 886 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL6_Msk (0x3ul << GPIO_PUSEL_PUSEL6_Pos) |
GPIO_T::PUSEL: PUSEL6 Mask
Definition at line 890 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL6_Pos (12) |
GPIO_T::PUSEL: PUSEL6 Position
Definition at line 889 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL7_Msk (0x3ul << GPIO_PUSEL_PUSEL7_Pos) |
GPIO_T::PUSEL: PUSEL7 Mask
Definition at line 893 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL7_Pos (14) |
GPIO_T::PUSEL: PUSEL7 Position
Definition at line 892 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL8_Msk (0x3ul << GPIO_PUSEL_PUSEL8_Pos) |
GPIO_T::PUSEL: PUSEL8 Mask
Definition at line 896 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL8_Pos (16) |
GPIO_T::PUSEL: PUSEL8 Position
Definition at line 895 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL9_Msk (0x3ul << GPIO_PUSEL_PUSEL9_Pos) |
GPIO_T::PUSEL: PUSEL9 Mask
Definition at line 899 of file gpio_reg.h.
| #define GPIO_PUSEL_PUSEL9_Pos (18) |
GPIO_T::PUSEL: PUSEL9 Position
Definition at line 898 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN0_Msk (0x3ul << GPIO_SLEWCTL_HSREN0_Pos) |
GPIO_T::SLEWCTL: HSREN0 Mask
Definition at line 824 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN0_Pos (0) |
GPIO_T::SLEWCTL: HSREN0 Position
Definition at line 823 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN10_Msk (0x3ul << GPIO_SLEWCTL_HSREN10_Pos) |
GPIO_T::SLEWCTL: HSREN10 Mask
Definition at line 854 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN10_Pos (20) |
GPIO_T::SLEWCTL: HSREN10 Position
Definition at line 853 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN11_Msk (0x3ul << GPIO_SLEWCTL_HSREN11_Pos) |
GPIO_T::SLEWCTL: HSREN11 Mask
Definition at line 857 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN11_Pos (22) |
GPIO_T::SLEWCTL: HSREN11 Position
Definition at line 856 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN12_Msk (0x3ul << GPIO_SLEWCTL_HSREN12_Pos) |
GPIO_T::SLEWCTL: HSREN12 Mask
Definition at line 860 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN12_Pos (24) |
GPIO_T::SLEWCTL: HSREN12 Position
Definition at line 859 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN13_Msk (0x3ul << GPIO_SLEWCTL_HSREN13_Pos) |
GPIO_T::SLEWCTL: HSREN13 Mask
Definition at line 863 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN13_Pos (26) |
GPIO_T::SLEWCTL: HSREN13 Position
Definition at line 862 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN14_Msk (0x3ul << GPIO_SLEWCTL_HSREN14_Pos) |
GPIO_T::SLEWCTL: HSREN14 Mask
Definition at line 866 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN14_Pos (28) |
GPIO_T::SLEWCTL: HSREN14 Position
Definition at line 865 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN15_Msk (0x3ul << GPIO_SLEWCTL_HSREN15_Pos) |
GPIO_T::SLEWCTL: HSREN15 Mask
Definition at line 869 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN15_Pos (30) |
GPIO_T::SLEWCTL: HSREN15 Position
Definition at line 868 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN1_Msk (0x3ul << GPIO_SLEWCTL_HSREN1_Pos) |
GPIO_T::SLEWCTL: HSREN1 Mask
Definition at line 827 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN1_Pos (2) |
GPIO_T::SLEWCTL: HSREN1 Position
Definition at line 826 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN2_Msk (0x3ul << GPIO_SLEWCTL_HSREN2_Pos) |
GPIO_T::SLEWCTL: HSREN2 Mask
Definition at line 830 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN2_Pos (4) |
GPIO_T::SLEWCTL: HSREN2 Position
Definition at line 829 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN3_Msk (0x3ul << GPIO_SLEWCTL_HSREN3_Pos) |
GPIO_T::SLEWCTL: HSREN3 Mask
Definition at line 833 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN3_Pos (6) |
GPIO_T::SLEWCTL: HSREN3 Position
Definition at line 832 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN4_Msk (0x3ul << GPIO_SLEWCTL_HSREN4_Pos) |
GPIO_T::SLEWCTL: HSREN4 Mask
Definition at line 836 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN4_Pos (8) |
GPIO_T::SLEWCTL: HSREN4 Position
Definition at line 835 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN5_Msk (0x3ul << GPIO_SLEWCTL_HSREN5_Pos) |
GPIO_T::SLEWCTL: HSREN5 Mask
Definition at line 839 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN5_Pos (10) |
GPIO_T::SLEWCTL: HSREN5 Position
Definition at line 838 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN6_Msk (0x3ul << GPIO_SLEWCTL_HSREN6_Pos) |
GPIO_T::SLEWCTL: HSREN6 Mask
Definition at line 842 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN6_Pos (12) |
GPIO_T::SLEWCTL: HSREN6 Position
Definition at line 841 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN7_Msk (0x3ul << GPIO_SLEWCTL_HSREN7_Pos) |
GPIO_T::SLEWCTL: HSREN7 Mask
Definition at line 845 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN7_Pos (14) |
GPIO_T::SLEWCTL: HSREN7 Position
Definition at line 844 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN8_Msk (0x3ul << GPIO_SLEWCTL_HSREN8_Pos) |
GPIO_T::SLEWCTL: HSREN8 Mask
Definition at line 848 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN8_Pos (16) |
GPIO_T::SLEWCTL: HSREN8 Position
Definition at line 847 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN9_Msk (0x3ul << GPIO_SLEWCTL_HSREN9_Pos) |
GPIO_T::SLEWCTL: HSREN9 Mask
Definition at line 851 of file gpio_reg.h.
| #define GPIO_SLEWCTL_HSREN9_Pos (18) |
GPIO_T::SLEWCTL: HSREN9 Position
Definition at line 850 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN0_Msk (0x1ul << GPIO_SMTEN_SMTEN0_Pos) |
GPIO_T::SMTEN: SMTEN0 Mask
Definition at line 776 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN0_Pos (0) |
GPIO_T::SMTEN: SMTEN0 Position
Definition at line 775 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN10_Msk (0x1ul << GPIO_SMTEN_SMTEN10_Pos) |
GPIO_T::SMTEN: SMTEN10 Mask
Definition at line 806 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN10_Pos (10) |
GPIO_T::SMTEN: SMTEN10 Position
Definition at line 805 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN11_Msk (0x1ul << GPIO_SMTEN_SMTEN11_Pos) |
GPIO_T::SMTEN: SMTEN11 Mask
Definition at line 809 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN11_Pos (11) |
GPIO_T::SMTEN: SMTEN11 Position
Definition at line 808 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN12_Msk (0x1ul << GPIO_SMTEN_SMTEN12_Pos) |
GPIO_T::SMTEN: SMTEN12 Mask
Definition at line 812 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN12_Pos (12) |
GPIO_T::SMTEN: SMTEN12 Position
Definition at line 811 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN13_Msk (0x1ul << GPIO_SMTEN_SMTEN13_Pos) |
GPIO_T::SMTEN: SMTEN13 Mask
Definition at line 815 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN13_Pos (13) |
GPIO_T::SMTEN: SMTEN13 Position
Definition at line 814 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN14_Msk (0x1ul << GPIO_SMTEN_SMTEN14_Pos) |
GPIO_T::SMTEN: SMTEN14 Mask
Definition at line 818 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN14_Pos (14) |
GPIO_T::SMTEN: SMTEN14 Position
Definition at line 817 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN15_Msk (0x1ul << GPIO_SMTEN_SMTEN15_Pos) |
GPIO_T::SMTEN: SMTEN15 Mask
Definition at line 821 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN15_Pos (15) |
GPIO_T::SMTEN: SMTEN15 Position
Definition at line 820 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN1_Msk (0x1ul << GPIO_SMTEN_SMTEN1_Pos) |
GPIO_T::SMTEN: SMTEN1 Mask
Definition at line 779 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN1_Pos (1) |
GPIO_T::SMTEN: SMTEN1 Position
Definition at line 778 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN2_Msk (0x1ul << GPIO_SMTEN_SMTEN2_Pos) |
GPIO_T::SMTEN: SMTEN2 Mask
Definition at line 782 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN2_Pos (2) |
GPIO_T::SMTEN: SMTEN2 Position
Definition at line 781 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN3_Msk (0x1ul << GPIO_SMTEN_SMTEN3_Pos) |
GPIO_T::SMTEN: SMTEN3 Mask
Definition at line 785 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN3_Pos (3) |
GPIO_T::SMTEN: SMTEN3 Position
Definition at line 784 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN4_Msk (0x1ul << GPIO_SMTEN_SMTEN4_Pos) |
GPIO_T::SMTEN: SMTEN4 Mask
Definition at line 788 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN4_Pos (4) |
GPIO_T::SMTEN: SMTEN4 Position
Definition at line 787 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN5_Msk (0x1ul << GPIO_SMTEN_SMTEN5_Pos) |
GPIO_T::SMTEN: SMTEN5 Mask
Definition at line 791 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN5_Pos (5) |
GPIO_T::SMTEN: SMTEN5 Position
Definition at line 790 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN6_Msk (0x1ul << GPIO_SMTEN_SMTEN6_Pos) |
GPIO_T::SMTEN: SMTEN6 Mask
Definition at line 794 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN6_Pos (6) |
GPIO_T::SMTEN: SMTEN6 Position
Definition at line 793 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN7_Msk (0x1ul << GPIO_SMTEN_SMTEN7_Pos) |
GPIO_T::SMTEN: SMTEN7 Mask
Definition at line 797 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN7_Pos (7) |
GPIO_T::SMTEN: SMTEN7 Position
Definition at line 796 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN8_Msk (0x1ul << GPIO_SMTEN_SMTEN8_Pos) |
GPIO_T::SMTEN: SMTEN8 Mask
Definition at line 800 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN8_Pos (8) |
GPIO_T::SMTEN: SMTEN8 Position
Definition at line 799 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN9_Msk (0x1ul << GPIO_SMTEN_SMTEN9_Pos) |
GPIO_T::SMTEN: SMTEN9 Mask
Definition at line 803 of file gpio_reg.h.
| #define GPIO_SMTEN_SMTEN9_Pos (9) |
GPIO_T::SMTEN: SMTEN9 Position
Definition at line 802 of file gpio_reg.h.
| #define I2C_ADDR0_ADDR_Msk (0x3fful << I2C_ADDR0_ADDR_Pos) |
I2C_T::ADDR0: ADDR Mask
| #define I2C_ADDR0_ADDR_Pos (1) |
I2C_T::ADDR0: ADDR Position
| #define I2C_ADDR0_GC_Msk (0x1ul << I2C_ADDR0_GC_Pos) |
I2C_T::ADDR0: GC Mask
| #define I2C_ADDR0_GC_Pos (0) |
I2C_T::ADDR0: GC Position
| #define I2C_ADDR1_ADDR_Msk (0x3fful << I2C_ADDR1_ADDR_Pos) |
I2C_T::ADDR1: ADDR Mask
| #define I2C_ADDR1_ADDR_Pos (1) |
I2C_T::ADDR1: ADDR Position
| #define I2C_ADDR1_GC_Msk (0x1ul << I2C_ADDR1_GC_Pos) |
I2C_T::ADDR1: GC Mask
| #define I2C_ADDR1_GC_Pos (0) |
I2C_T::ADDR1: GC Position
| #define I2C_ADDR2_ADDR_Msk (0x3fful << I2C_ADDR2_ADDR_Pos) |
I2C_T::ADDR2: ADDR Mask
| #define I2C_ADDR2_ADDR_Pos (1) |
I2C_T::ADDR2: ADDR Position
| #define I2C_ADDR2_GC_Msk (0x1ul << I2C_ADDR2_GC_Pos) |
I2C_T::ADDR2: GC Mask
| #define I2C_ADDR2_GC_Pos (0) |
I2C_T::ADDR2: GC Position
| #define I2C_ADDR3_ADDR_Msk (0x3fful << I2C_ADDR3_ADDR_Pos) |
I2C_T::ADDR3: ADDR Mask
| #define I2C_ADDR3_ADDR_Pos (1) |
I2C_T::ADDR3: ADDR Position
| #define I2C_ADDR3_GC_Msk (0x1ul << I2C_ADDR3_GC_Pos) |
I2C_T::ADDR3: GC Mask
| #define I2C_ADDR3_GC_Pos (0) |
I2C_T::ADDR3: GC Position
| #define I2C_ADDRMSK0_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK0_ADDRMSK_Pos) |
I2C_T::ADDRMSK0: ADDRMSK Mask
| #define I2C_ADDRMSK0_ADDRMSK_Pos (1) |
I2C_T::ADDRMSK0: ADDRMSK Position
| #define I2C_ADDRMSK1_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK1_ADDRMSK_Pos) |
I2C_T::ADDRMSK1: ADDRMSK Mask
| #define I2C_ADDRMSK1_ADDRMSK_Pos (1) |
I2C_T::ADDRMSK1: ADDRMSK Position
| #define I2C_ADDRMSK2_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK2_ADDRMSK_Pos) |
I2C_T::ADDRMSK2: ADDRMSK Mask
| #define I2C_ADDRMSK2_ADDRMSK_Pos (1) |
I2C_T::ADDRMSK2: ADDRMSK Position
| #define I2C_ADDRMSK3_ADDRMSK_Msk (0x3fful << I2C_ADDRMSK3_ADDRMSK_Pos) |
I2C_T::ADDRMSK3: ADDRMSK Mask
| #define I2C_ADDRMSK3_ADDRMSK_Pos (1) |
I2C_T::ADDRMSK3: ADDRMSK Position
| #define I2C_BUSCTL_ACKM9SI_Msk (0x1ul << I2C_BUSCTL_ACKM9SI_Pos) |
I2C_T::BUSCTL: ACKM9SI Mask
| #define I2C_BUSCTL_ACKM9SI_Pos (11) |
I2C_T::BUSCTL: ACKM9SI Position
| #define I2C_BUSCTL_ACKMEN_Msk (0x1ul << I2C_BUSCTL_ACKMEN_Pos) |
I2C_T::BUSCTL: ACKMEN Mask
| #define I2C_BUSCTL_ACKMEN_Pos (0) |
I2C_T::BUSCTL: ACKMEN Position
| #define I2C_BUSCTL_ALERTEN_Msk (0x1ul << I2C_BUSCTL_ALERTEN_Pos) |
I2C_T::BUSCTL: ALERTEN Mask
| #define I2C_BUSCTL_ALERTEN_Pos (4) |
I2C_T::BUSCTL: ALERTEN Position
| #define I2C_BUSCTL_BCDIEN_Msk (0x1ul << I2C_BUSCTL_BCDIEN_Pos) |
I2C_T::BUSCTL: BCDIEN Mask
| #define I2C_BUSCTL_BCDIEN_Pos (12) |
I2C_T::BUSCTL: BCDIEN Position
| #define I2C_BUSCTL_BMDEN_Msk (0x1ul << I2C_BUSCTL_BMDEN_Pos) |
I2C_T::BUSCTL: BMDEN Mask
| #define I2C_BUSCTL_BMDEN_Pos (2) |
I2C_T::BUSCTL: BMDEN Position
| #define I2C_BUSCTL_BMHEN_Msk (0x1ul << I2C_BUSCTL_BMHEN_Pos) |
I2C_T::BUSCTL: BMHEN Mask
| #define I2C_BUSCTL_BMHEN_Pos (3) |
I2C_T::BUSCTL: BMHEN Position
| #define I2C_BUSCTL_BUSEN_Msk (0x1ul << I2C_BUSCTL_BUSEN_Pos) |
I2C_T::BUSCTL: BUSEN Mask
| #define I2C_BUSCTL_BUSEN_Pos (7) |
I2C_T::BUSCTL: BUSEN Position
| #define I2C_BUSCTL_PECCLR_Msk (0x1ul << I2C_BUSCTL_PECCLR_Pos) |
I2C_T::BUSCTL: PECCLR Mask
| #define I2C_BUSCTL_PECCLR_Pos (10) |
I2C_T::BUSCTL: PECCLR Position
| #define I2C_BUSCTL_PECDIEN_Msk (0x1ul << I2C_BUSCTL_PECDIEN_Pos) |
I2C_T::BUSCTL: PECDIEN Mask
| #define I2C_BUSCTL_PECDIEN_Pos (13) |
I2C_T::BUSCTL: PECDIEN Position
| #define I2C_BUSCTL_PECEN_Msk (0x1ul << I2C_BUSCTL_PECEN_Pos) |
I2C_T::BUSCTL: PECEN Mask
| #define I2C_BUSCTL_PECEN_Pos (1) |
I2C_T::BUSCTL: PECEN Position
| #define I2C_BUSCTL_PECTXEN_Msk (0x1ul << I2C_BUSCTL_PECTXEN_Pos) |
I2C_T::BUSCTL: PECTXEN Mask
| #define I2C_BUSCTL_PECTXEN_Pos (8) |
I2C_T::BUSCTL: PECTXEN Position
| #define I2C_BUSCTL_SCTLOEN_Msk (0x1ul << I2C_BUSCTL_SCTLOEN_Pos) |
I2C_T::BUSCTL: SCTLOEN Mask
| #define I2C_BUSCTL_SCTLOEN_Pos (6) |
I2C_T::BUSCTL: SCTLOEN Position
| #define I2C_BUSCTL_SCTLOSTS_Msk (0x1ul << I2C_BUSCTL_SCTLOSTS_Pos) |
I2C_T::BUSCTL: SCTLOSTS Mask
| #define I2C_BUSCTL_SCTLOSTS_Pos (5) |
I2C_T::BUSCTL: SCTLOSTS Position
| #define I2C_BUSCTL_TIDLE_Msk (0x1ul << I2C_BUSCTL_TIDLE_Pos) |
I2C_T::BUSCTL: TIDLE Mask
| #define I2C_BUSCTL_TIDLE_Pos (9) |
I2C_T::BUSCTL: TIDLE Position
| #define I2C_BUSSTS_ALERT_Msk (0x1ul << I2C_BUSSTS_ALERT_Pos) |
I2C_T::BUSSTS: ALERT Mask
| #define I2C_BUSSTS_ALERT_Pos (3) |
I2C_T::BUSSTS: ALERT Position
| #define I2C_BUSSTS_BCDONE_Msk (0x1ul << I2C_BUSSTS_BCDONE_Pos) |
I2C_T::BUSSTS: BCDONE Mask
| #define I2C_BUSSTS_BCDONE_Pos (1) |
I2C_T::BUSSTS: BCDONE Position
| #define I2C_BUSSTS_BUSTO_Msk (0x1ul << I2C_BUSSTS_BUSTO_Pos) |
I2C_T::BUSSTS: BUSTO Mask
| #define I2C_BUSSTS_BUSTO_Pos (5) |
I2C_T::BUSSTS: BUSTO Position
| #define I2C_BUSSTS_BUSY_Msk (0x1ul << I2C_BUSSTS_BUSY_Pos) |
I2C_T::BUSSTS: BUSY Mask
| #define I2C_BUSSTS_BUSY_Pos (0) |
I2C_T::BUSSTS: BUSY Position
| #define I2C_BUSSTS_CLKTO_Msk (0x1ul << I2C_BUSSTS_CLKTO_Pos) |
I2C_T::BUSSTS: CLKTO Mask
| #define I2C_BUSSTS_CLKTO_Pos (6) |
I2C_T::BUSSTS: CLKTO Position
| #define I2C_BUSSTS_PECDONE_Msk (0x1ul << I2C_BUSSTS_PECDONE_Pos) |
I2C_T::BUSSTS: PECDONE Mask
| #define I2C_BUSSTS_PECDONE_Pos (7) |
I2C_T::BUSSTS: PECDONE Position
| #define I2C_BUSSTS_PECERR_Msk (0x1ul << I2C_BUSSTS_PECERR_Pos) |
I2C_T::BUSSTS: PECERR Mask
| #define I2C_BUSSTS_PECERR_Pos (2) |
I2C_T::BUSSTS: PECERR Position
| #define I2C_BUSSTS_SCTLDIN_Msk (0x1ul << I2C_BUSSTS_SCTLDIN_Pos) |
I2C_T::BUSSTS: SCTLDIN Mask
| #define I2C_BUSSTS_SCTLDIN_Pos (4) |
I2C_T::BUSSTS: SCTLDIN Position
| #define I2C_BUSTCTL_BUSTOEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOEN_Pos) |
I2C_T::BUSTCTL: BUSTOEN Mask
| #define I2C_BUSTCTL_BUSTOEN_Pos (0) |
I2C_T::BUSTCTL: BUSTOEN Position
| #define I2C_BUSTCTL_BUSTOIEN_Msk (0x1ul << I2C_BUSTCTL_BUSTOIEN_Pos) |
I2C_T::BUSTCTL: BUSTOIEN Mask
| #define I2C_BUSTCTL_BUSTOIEN_Pos (2) |
I2C_T::BUSTCTL: BUSTOIEN Position
| #define I2C_BUSTCTL_CLKTOEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOEN_Pos) |
I2C_T::BUSTCTL: CLKTOEN Mask
| #define I2C_BUSTCTL_CLKTOEN_Pos (1) |
I2C_T::BUSTCTL: CLKTOEN Position
| #define I2C_BUSTCTL_CLKTOIEN_Msk (0x1ul << I2C_BUSTCTL_CLKTOIEN_Pos) |
I2C_T::BUSTCTL: CLKTOIEN Mask
| #define I2C_BUSTCTL_CLKTOIEN_Pos (3) |
I2C_T::BUSTCTL: CLKTOIEN Position
| #define I2C_BUSTCTL_TORSTEN_Msk (0x1ul << I2C_BUSTCTL_TORSTEN_Pos) |
I2C_T::BUSTCTL: TORSTEN Mask
| #define I2C_BUSTCTL_TORSTEN_Pos (4) |
I2C_T::BUSTCTL: TORSTEN Position
| #define I2C_BUSTOUT_BUSTO_Msk (0xfful << I2C_BUSTOUT_BUSTO_Pos) |
I2C_T::BUSTOUT: BUSTO Mask
| #define I2C_BUSTOUT_BUSTO_Pos (0) |
I2C_T::BUSTOUT: BUSTO Position
| #define I2C_CLKDIV_DIVIDER_Msk (0x3fful << I2C_CLKDIV_DIVIDER_Pos) |
I2C_T::CLKDIV: DIVIDER Mask
| #define I2C_CLKDIV_DIVIDER_Pos (0) |
I2C_T::CLKDIV: DIVIDER Position
| #define I2C_CLKTOUT_CLKTO_Msk (0xfful << I2C_CLKTOUT_CLKTO_Pos) |
I2C_T::CLKTOUT: CLKTO Mask
| #define I2C_CLKTOUT_CLKTO_Pos (0) |
I2C_T::CLKTOUT: CLKTO Position
| #define I2C_CTL0_AA_Msk (0x1ul << I2C_CTL0_AA_Pos) |
| #define I2C_CTL0_AA_Pos (2) |
| #define I2C_CTL0_I2CEN_Msk (0x1ul << I2C_CTL0_I2CEN_Pos) |
| #define I2C_CTL0_INTEN_Msk (0x1ul << I2C_CTL0_INTEN_Pos) |
| #define I2C_CTL0_SI_Msk (0x1ul << I2C_CTL0_SI_Pos) |
| #define I2C_CTL0_STA_Msk (0x1ul << I2C_CTL0_STA_Pos) |
| #define I2C_CTL0_STO_Msk (0x1ul << I2C_CTL0_STO_Pos) |
| #define I2C_CTL1_ADDR10EN_Msk (0x1ul << I2C_CTL1_ADDR10EN_Pos) |
I2C_T::CTL1: ADDR10EN Mask
| #define I2C_CTL1_ADDR10EN_Pos (9) |
I2C_T::CTL1: ADDR10EN Position
| #define I2C_CTL1_PDMARST_Msk (0x1ul << I2C_CTL1_PDMARST_Pos) |
I2C_T::CTL1: PDMARST Mask
| #define I2C_CTL1_PDMARST_Pos (2) |
I2C_T::CTL1: PDMARST Position
| #define I2C_CTL1_PDMASTR_Msk (0x1ul << I2C_CTL1_PDMASTR_Pos) |
I2C_T::CTL1: PDMASTR Mask
| #define I2C_CTL1_PDMASTR_Pos (8) |
I2C_T::CTL1: PDMASTR Position
| #define I2C_CTL1_RXPDMAEN_Msk (0x1ul << I2C_CTL1_RXPDMAEN_Pos) |
I2C_T::CTL1: RXPDMAEN Mask
| #define I2C_CTL1_RXPDMAEN_Pos (1) |
I2C_T::CTL1: RXPDMAEN Position
| #define I2C_CTL1_TXPDMAEN_Msk (0x1ul << I2C_CTL1_TXPDMAEN_Pos) |
I2C_T::CTL1: TXPDMAEN Mask
| #define I2C_CTL1_TXPDMAEN_Pos (0) |
I2C_T::CTL1: TXPDMAEN Position
| #define I2C_DAT_DAT_Msk (0xfful << I2C_DAT_DAT_Pos) |
I2C_T::DAT: DAT Mask
| #define I2C_DAT_DAT_Pos (0) |
I2C_T::DAT: DAT Position
| #define I2C_PKTCRC_PECCRC_Msk (0xfful << I2C_PKTCRC_PECCRC_Pos) |
I2C_T::PKTCRC: PECCRC Mask
| #define I2C_PKTCRC_PECCRC_Pos (0) |
I2C_T::PKTCRC: PECCRC Position
| #define I2C_PKTSIZE_PLDSIZE_Msk (0x1fful << I2C_PKTSIZE_PLDSIZE_Pos) |
I2C_T::PKTSIZE: PLDSIZE Mask
| #define I2C_PKTSIZE_PLDSIZE_Pos (0) |
I2C_T::PKTSIZE: PLDSIZE Position
| #define I2C_STATUS0_STATUS_Msk (0xfful << I2C_STATUS_STATUS0_Pos) |
| #define I2C_STATUS0_STATUS_Pos (0) |
| #define I2C_STATUS1_ADMAT0_Msk (0x1ul << I2C_STATUS1_ADMAT0_Pos) |
I2C_T::STATUS1: ADMAT0 Mask
| #define I2C_STATUS1_ADMAT0_Pos (0) |
I2C_T::STATUS1: ADMAT0 Position
| #define I2C_STATUS1_ADMAT1_Msk (0x1ul << I2C_STATUS1_ADMAT1_Pos) |
I2C_T::STATUS1: ADMAT1 Mask
| #define I2C_STATUS1_ADMAT1_Pos (1) |
I2C_T::STATUS1: ADMAT1 Position
| #define I2C_STATUS1_ADMAT2_Msk (0x1ul << I2C_STATUS1_ADMAT2_Pos) |
I2C_T::STATUS1: ADMAT2 Mask
| #define I2C_STATUS1_ADMAT2_Pos (2) |
I2C_T::STATUS1: ADMAT2 Position
| #define I2C_STATUS1_ADMAT3_Msk (0x1ul << I2C_STATUS1_ADMAT3_Pos) |
I2C_T::STATUS1: ADMAT3 Mask
| #define I2C_STATUS1_ADMAT3_Pos (3) |
I2C_T::STATUS1: ADMAT3 Position
| #define I2C_STATUS1_ONBUSY_Msk (0x1ul << I2C_STATUS1_ONBUSY_Pos) |
I2C_T::STATUS1: ONBUSY Mask
| #define I2C_STATUS1_ONBUSY_Pos (8) |
I2C_T::STATUS1: ONBUSY Position
| #define I2C_TMCTL_HTCTL_Msk (0x1fful << I2C_TMCTL_HTCTL_Pos) |
I2C_T::TMCTL: HTCTL Mask
| #define I2C_TMCTL_HTCTL_Pos (16) |
I2C_T::TMCTL: HTCTL Position
| #define I2C_TMCTL_STCTL_Msk (0x1fful << I2C_TMCTL_STCTL_Pos) |
I2C_T::TMCTL: STCTL Mask
| #define I2C_TMCTL_STCTL_Pos (0) |
I2C_T::TMCTL: STCTL Position
| #define I2C_TOCTL_TOCDIV4_Msk (0x1ul << I2C_TOCTL_TOCDIV4_Pos) |
I2C_T::TOCTL: TOCDIV4 Mask
| #define I2C_TOCTL_TOCDIV4_Pos (1) |
I2C_T::TOCTL: TOCDIV4 Position
| #define I2C_TOCTL_TOCEN_Msk (0x1ul << I2C_TOCTL_TOCEN_Pos) |
I2C_T::TOCTL: TOCEN Mask
| #define I2C_TOCTL_TOCEN_Pos (2) |
I2C_T::TOCTL: TOCEN Position
| #define I2C_TOCTL_TOIF_Msk (0x1ul << I2C_TOCTL_TOIF_Pos) |
I2C_T::TOCTL: TOIF Mask
| #define I2C_TOCTL_TOIF_Pos (0) |
I2C_T::TOCTL: TOIF Position
| #define I2C_WKCTL_NHDBUSEN_Msk (0x1ul << I2C_WKCTL_NHDBUSEN_Pos) |
I2C_T::WKCTL: NHDBUSEN Mask
| #define I2C_WKCTL_NHDBUSEN_Pos (7) |
I2C_T::WKCTL: NHDBUSEN Position
| #define I2C_WKCTL_WKEN_Msk (0x1ul << I2C_WKCTL_WKEN_Pos) |
I2C_T::WKCTL: WKEN Mask
| #define I2C_WKCTL_WKEN_Pos (0) |
I2C_T::WKCTL: WKEN Position
| #define I2C_WKSTS_WKAKDONE_Msk (0x1ul << I2C_WKSTS_WKAKDONE_Pos) |
I2C_T::WKSTS: WKAKDONE Mask
| #define I2C_WKSTS_WKAKDONE_Pos (1) |
I2C_T::WKSTS: WKAKDONE Position
| #define I2C_WKSTS_WKIF_Msk (0x1ul << I2C_WKSTS_WKIF_Pos) |
I2C_T::WKSTS: WKIF Mask
| #define I2C_WKSTS_WKIF_Pos (0) |
I2C_T::WKSTS: WKIF Position
| #define I2C_WKSTS_WRSTSWK_Msk (0x1ul << I2C_WKSTS_WRSTSWK_Pos) |
I2C_T::WKSTS: WRSTSWK Mask
| #define I2C_WKSTS_WRSTSWK_Pos (2) |
I2C_T::WKSTS: WRSTSWK Position
| #define I2S_CLKDIV_BCLKDIV_Msk (0x1fful << I2S_CLKDIV_BCLKDIV_Pos) |
I2S_T::CLKDIV: BCLKDIV Mask
| #define I2S_CLKDIV_BCLKDIV_Pos (8) |
I2S_T::CLKDIV: BCLKDIV Position
| #define I2S_CLKDIV_MCLKDIV_Msk (0x3ful << I2S_CLKDIV_MCLKDIV_Pos) |
I2S_T::CLKDIV: MCLKDIV Mask
| #define I2S_CLKDIV_MCLKDIV_Pos (0) |
I2S_T::CLKDIV: MCLKDIV Position
| #define I2S_CTL0_CHWIDTH_Msk (0x3ul << I2S_CTL0_CHWIDTH_Pos) |
I2S_T::CTL0: CHWIDTH Mask
| #define I2S_CTL0_CHWIDTH_Pos (28) |
I2S_T::CTL0: CHWIDTH Position
| #define I2S_CTL0_DATWIDTH_Msk (0x3ul << I2S_CTL0_DATWIDTH_Pos) |
I2S_T::CTL0: DATWIDTH Mask
| #define I2S_CTL0_DATWIDTH_Pos (4) |
I2S_T::CTL0: DATWIDTH Position
| #define I2S_CTL0_FORMAT_Msk (0x7ul << I2S_CTL0_FORMAT_Pos) |
I2S_T::CTL0: FORMAT Mask
| #define I2S_CTL0_FORMAT_Pos (24) |
I2S_T::CTL0: FORMAT Position
| #define I2S_CTL0_I2SEN_Msk (0x1ul << I2S_CTL0_I2SEN_Pos) |
I2S_T::CTL0: I2SEN Mask
| #define I2S_CTL0_I2SEN_Pos (0) |
@addtogroup I2S_CONST I2S Bit Field Definition Constant Definitions for I2S Controller
I2S_T::CTL0: I2SEN Position
| #define I2S_CTL0_MCLKEN_Msk (0x1ul << I2S_CTL0_MCLKEN_Pos) |
I2S_T::CTL0: MCLKEN Mask
| #define I2S_CTL0_MCLKEN_Pos (15) |
I2S_T::CTL0: MCLKEN Position
| #define I2S_CTL0_MONO_Msk (0x1ul << I2S_CTL0_MONO_Pos) |
I2S_T::CTL0: MONO Mask
| #define I2S_CTL0_MONO_Pos (6) |
I2S_T::CTL0: MONO Position
| #define I2S_CTL0_MUTE_Msk (0x1ul << I2S_CTL0_MUTE_Pos) |
I2S_T::CTL0: MUTE Mask
| #define I2S_CTL0_MUTE_Pos (3) |
I2S_T::CTL0: MUTE Position
| #define I2S_CTL0_ORDER_Msk (0x1ul << I2S_CTL0_ORDER_Pos) |
I2S_T::CTL0: ORDER Mask
| #define I2S_CTL0_ORDER_Pos (7) |
I2S_T::CTL0: ORDER Position
| #define I2S_CTL0_PCMSYNC_Msk (0x1ul << I2S_CTL0_PCMSYNC_Pos) |
I2S_T::CTL0: PCMSYNC Mask
| #define I2S_CTL0_PCMSYNC_Pos (27) |
I2S_T::CTL0: PCMSYNC Position
| #define I2S_CTL0_RXEN_Msk (0x1ul << I2S_CTL0_RXEN_Pos) |
I2S_T::CTL0: RXEN Mask
| #define I2S_CTL0_RXEN_Pos (2) |
I2S_T::CTL0: RXEN Position
| #define I2S_CTL0_RXFBCLR_Msk (0x1ul << I2S_CTL0_RXFBCLR_Pos) |
I2S_T::CTL0: RXFBCLR Mask
| #define I2S_CTL0_RXFBCLR_Pos (19) |
I2S_T::CTL0: RXFBCLR Position
| #define I2S_CTL0_RXLCH_Msk (0x1ul << I2S_CTL0_RXLCH_Pos) |
I2S_T::CTL0: RXLCH Mask
| #define I2S_CTL0_RXLCH_Pos (23) |
I2S_T::CTL0: RXLCH Position
| #define I2S_CTL0_RXPDMAEN_Msk (0x1ul << I2S_CTL0_RXPDMAEN_Pos) |
I2S_T::CTL0: RXPDMAEN Mask
| #define I2S_CTL0_RXPDMAEN_Pos (21) |
I2S_T::CTL0: RXPDMAEN Position
| #define I2S_CTL0_SLAVE_Msk (0x1ul << I2S_CTL0_SLAVE_Pos) |
I2S_T::CTL0: SLAVE Mask
| #define I2S_CTL0_SLAVE_Pos (8) |
I2S_T::CTL0: SLAVE Position
| #define I2S_CTL0_TDMCHNUM_Msk (0x3ul << I2S_CTL0_TDMCHNUM_Pos) |
I2S_T::CTL0: TDMCHNUM Mask
| #define I2S_CTL0_TDMCHNUM_Pos (30) |
I2S_T::CTL0: TDMCHNUM Position
| #define I2S_CTL0_TXEN_Msk (0x1ul << I2S_CTL0_TXEN_Pos) |
I2S_T::CTL0: TXEN Mask
| #define I2S_CTL0_TXEN_Pos (1) |
I2S_T::CTL0: TXEN Position
| #define I2S_CTL0_TXFBCLR_Msk (0x1ul << I2S_CTL0_TXFBCLR_Pos) |
I2S_T::CTL0: TXFBCLR Mask
| #define I2S_CTL0_TXFBCLR_Pos (18) |
I2S_T::CTL0: TXFBCLR Position
| #define I2S_CTL0_TXPDMAEN_Msk (0x1ul << I2S_CTL0_TXPDMAEN_Pos) |
I2S_T::CTL0: TXPDMAEN Mask
| #define I2S_CTL0_TXPDMAEN_Pos (20) |
I2S_T::CTL0: TXPDMAEN Position
| #define I2S_CTL1_CH0ZCEN_Msk (0x1ul << I2S_CTL1_CH0ZCEN_Pos) |
I2S_T::CTL1: CH0ZCEN Mask
| #define I2S_CTL1_CH0ZCEN_Pos (0) |
I2S_T::CTL1: CH0ZCEN Position
| #define I2S_CTL1_CH1ZCEN_Msk (0x1ul << I2S_CTL1_CH1ZCEN_Pos) |
I2S_T::CTL1: CH1ZCEN Mask
| #define I2S_CTL1_CH1ZCEN_Pos (1) |
I2S_T::CTL1: CH1ZCEN Position
| #define I2S_CTL1_CH2ZCEN_Msk (0x1ul << I2S_CTL1_CH2ZCEN_Pos) |
I2S_T::CTL1: CH2ZCEN Mask
| #define I2S_CTL1_CH2ZCEN_Pos (2) |
I2S_T::CTL1: CH2ZCEN Position
| #define I2S_CTL1_CH3ZCEN_Msk (0x1ul << I2S_CTL1_CH3ZCEN_Pos) |
I2S_T::CTL1: CH3ZCEN Mask
| #define I2S_CTL1_CH3ZCEN_Pos (3) |
I2S_T::CTL1: CH3ZCEN Position
| #define I2S_CTL1_CH4ZCEN_Msk (0x1ul << I2S_CTL1_CH4ZCEN_Pos) |
I2S_T::CTL1: CH4ZCEN Mask
| #define I2S_CTL1_CH4ZCEN_Pos (4) |
I2S_T::CTL1: CH4ZCEN Position
| #define I2S_CTL1_CH5ZCEN_Msk (0x1ul << I2S_CTL1_CH5ZCEN_Pos) |
I2S_T::CTL1: CH5ZCEN Mask
| #define I2S_CTL1_CH5ZCEN_Pos (5) |
I2S_T::CTL1: CH5ZCEN Position
| #define I2S_CTL1_CH6ZCEN_Msk (0x1ul << I2S_CTL1_CH6ZCEN_Pos) |
I2S_T::CTL1: CH6ZCEN Mask
| #define I2S_CTL1_CH6ZCEN_Pos (6) |
I2S_T::CTL1: CH6ZCEN Position
| #define I2S_CTL1_CH7ZCEN_Msk (0x1ul << I2S_CTL1_CH7ZCEN_Pos) |
I2S_T::CTL1: CH7ZCEN Mask
| #define I2S_CTL1_CH7ZCEN_Pos (7) |
I2S_T::CTL1: CH7ZCEN Position
| #define I2S_CTL1_PB16ORD_Msk (0x1ul << I2S_CTL1_PB16ORD_Pos) |
I2S_T::CTL1: PB16ORD Mask
| #define I2S_CTL1_PB16ORD_Pos (25) |
I2S_T::CTL1: PB16ORD Position
| #define I2S_CTL1_PBWIDTH_Msk (0x1ul << I2S_CTL1_PBWIDTH_Pos) |
I2S_T::CTL1: PBWIDTH Mask
| #define I2S_CTL1_PBWIDTH_Pos (24) |
I2S_T::CTL1: PBWIDTH Position
| #define I2S_CTL1_RXTH_Msk (0xful << I2S_CTL1_RXTH_Pos) |
I2S_T::CTL1: RXTH Mask
| #define I2S_CTL1_RXTH_Pos (16) |
I2S_T::CTL1: RXTH Position
| #define I2S_CTL1_TXTH_Msk (0xful << I2S_CTL1_TXTH_Pos) |
I2S_T::CTL1: TXTH Mask
| #define I2S_CTL1_TXTH_Pos (8) |
I2S_T::CTL1: TXTH Position
| #define I2S_IEN_CH0ZCIEN_Msk (0x1ul << I2S_IEN_CH0ZCIEN_Pos) |
I2S_T::IEN: CH0ZCIEN Mask
| #define I2S_IEN_CH0ZCIEN_Pos (16) |
I2S_T::IEN: CH0ZCIEN Position
| #define I2S_IEN_CH1ZCIEN_Msk (0x1ul << I2S_IEN_CH1ZCIEN_Pos) |
I2S_T::IEN: CH1ZCIEN Mask
| #define I2S_IEN_CH1ZCIEN_Pos (17) |
I2S_T::IEN: CH1ZCIEN Position
| #define I2S_IEN_CH2ZCIEN_Msk (0x1ul << I2S_IEN_CH2ZCIEN_Pos) |
I2S_T::IEN: CH2ZCIEN Mask
| #define I2S_IEN_CH2ZCIEN_Pos (18) |
I2S_T::IEN: CH2ZCIEN Position
| #define I2S_IEN_CH3ZCIEN_Msk (0x1ul << I2S_IEN_CH3ZCIEN_Pos) |
I2S_T::IEN: CH3ZCIEN Mask
| #define I2S_IEN_CH3ZCIEN_Pos (19) |
I2S_T::IEN: CH3ZCIEN Position
| #define I2S_IEN_CH4ZCIEN_Msk (0x1ul << I2S_IEN_CH4ZCIEN_Pos) |
I2S_T::IEN: CH4ZCIEN Mask
| #define I2S_IEN_CH4ZCIEN_Pos (20) |
I2S_T::IEN: CH4ZCIEN Position
| #define I2S_IEN_CH5ZCIEN_Msk (0x1ul << I2S_IEN_CH5ZCIEN_Pos) |
I2S_T::IEN: CH5ZCIEN Mask
| #define I2S_IEN_CH5ZCIEN_Pos (21) |
I2S_T::IEN: CH5ZCIEN Position
| #define I2S_IEN_CH6ZCIEN_Msk (0x1ul << I2S_IEN_CH6ZCIEN_Pos) |
I2S_T::IEN: CH6ZCIEN Mask
| #define I2S_IEN_CH6ZCIEN_Pos (22) |
I2S_T::IEN: CH6ZCIEN Position
| #define I2S_IEN_CH7ZCIEN_Msk (0x1ul << I2S_IEN_CH7ZCIEN_Pos) |
I2S_T::IEN: CH7ZCIEN Mask
| #define I2S_IEN_CH7ZCIEN_Pos (23) |
I2S_T::IEN: CH7ZCIEN Position
| #define I2S_IEN_RXOVFIEN_Msk (0x1ul << I2S_IEN_RXOVFIEN_Pos) |
I2S_T::IEN: RXOVFIEN Mask
| #define I2S_IEN_RXOVFIEN_Pos (1) |
I2S_T::IEN: RXOVFIEN Position
| #define I2S_IEN_RXTHIEN_Msk (0x1ul << I2S_IEN_RXTHIEN_Pos) |
I2S_T::IEN: RXTHIEN Mask
| #define I2S_IEN_RXTHIEN_Pos (2) |
I2S_T::IEN: RXTHIEN Position
| #define I2S_IEN_RXUDFIEN_Msk (0x1ul << I2S_IEN_RXUDFIEN_Pos) |
I2S_T::IEN: RXUDFIEN Mask
| #define I2S_IEN_RXUDFIEN_Pos (0) |
I2S_T::IEN: RXUDFIEN Position
| #define I2S_IEN_TXOVFIEN_Msk (0x1ul << I2S_IEN_TXOVFIEN_Pos) |
I2S_T::IEN: TXOVFIEN Mask
| #define I2S_IEN_TXOVFIEN_Pos (9) |
I2S_T::IEN: TXOVFIEN Position
| #define I2S_IEN_TXTHIEN_Msk (0x1ul << I2S_IEN_TXTHIEN_Pos) |
I2S_T::IEN: TXTHIEN Mask
| #define I2S_IEN_TXTHIEN_Pos (10) |
I2S_T::IEN: TXTHIEN Position
| #define I2S_IEN_TXUDFIEN_Msk (0x1ul << I2S_IEN_TXUDFIEN_Pos) |
I2S_T::IEN: TXUDFIEN Mask
| #define I2S_IEN_TXUDFIEN_Pos (8) |
I2S_T::IEN: TXUDFIEN Position
| #define I2S_RXFIFO_RXFIFO_Msk (0xfffffffful << I2S_RXFIFO_RXFIFO_Pos) |
I2S_T::RXFIFO: RXFIFO Mask
| #define I2S_RXFIFO_RXFIFO_Pos (0) |
I2S_T::RXFIFO: RXFIFO Position
| #define I2S_STATUS0_DATACH_Msk (0x7ul << I2S_STATUS0_DATACH_Pos) |
I2S_T::STATUS0: DATACH Mask
| #define I2S_STATUS0_DATACH_Pos (3) |
I2S_T::STATUS0: DATACH Position
| #define I2S_STATUS0_I2SINT_Msk (0x1ul << I2S_STATUS0_I2SINT_Pos) |
I2S_T::STATUS0: I2SINT Mask
| #define I2S_STATUS0_I2SINT_Pos (0) |
I2S_T::STATUS0: I2SINT Position
| #define I2S_STATUS0_I2SRXINT_Msk (0x1ul << I2S_STATUS0_I2SRXINT_Pos) |
I2S_T::STATUS0: I2SRXINT Mask
| #define I2S_STATUS0_I2SRXINT_Pos (1) |
I2S_T::STATUS0: I2SRXINT Position
| #define I2S_STATUS0_I2STXINT_Msk (0x1ul << I2S_STATUS0_I2STXINT_Pos) |
I2S_T::STATUS0: I2STXINT Mask
| #define I2S_STATUS0_I2STXINT_Pos (2) |
I2S_T::STATUS0: I2STXINT Position
| #define I2S_STATUS0_RXEMPTY_Msk (0x1ul << I2S_STATUS0_RXEMPTY_Pos) |
I2S_T::STATUS0: RXEMPTY Mask
| #define I2S_STATUS0_RXEMPTY_Pos (12) |
I2S_T::STATUS0: RXEMPTY Position
| #define I2S_STATUS0_RXFULL_Msk (0x1ul << I2S_STATUS0_RXFULL_Pos) |
I2S_T::STATUS0: RXFULL Mask
| #define I2S_STATUS0_RXFULL_Pos (11) |
I2S_T::STATUS0: RXFULL Position
| #define I2S_STATUS0_RXOVIF_Msk (0x1ul << I2S_STATUS0_RXOVIF_Pos) |
I2S_T::STATUS0: RXOVIF Mask
| #define I2S_STATUS0_RXOVIF_Pos (9) |
I2S_T::STATUS0: RXOVIF Position
| #define I2S_STATUS0_RXTHIF_Msk (0x1ul << I2S_STATUS0_RXTHIF_Pos) |
I2S_T::STATUS0: RXTHIF Mask
| #define I2S_STATUS0_RXTHIF_Pos (10) |
I2S_T::STATUS0: RXTHIF Position
| #define I2S_STATUS0_RXUDIF_Msk (0x1ul << I2S_STATUS0_RXUDIF_Pos) |
I2S_T::STATUS0: RXUDIF Mask
| #define I2S_STATUS0_RXUDIF_Pos (8) |
I2S_T::STATUS0: RXUDIF Position
| #define I2S_STATUS0_TXBUSY_Msk (0x1ul << I2S_STATUS0_TXBUSY_Pos) |
I2S_T::STATUS0: TXBUSY Mask
| #define I2S_STATUS0_TXBUSY_Pos (21) |
I2S_T::STATUS0: TXBUSY Position
| #define I2S_STATUS0_TXEMPTY_Msk (0x1ul << I2S_STATUS0_TXEMPTY_Pos) |
I2S_T::STATUS0: TXEMPTY Mask
| #define I2S_STATUS0_TXEMPTY_Pos (20) |
I2S_T::STATUS0: TXEMPTY Position
| #define I2S_STATUS0_TXFULL_Msk (0x1ul << I2S_STATUS0_TXFULL_Pos) |
I2S_T::STATUS0: TXFULL Mask
| #define I2S_STATUS0_TXFULL_Pos (19) |
I2S_T::STATUS0: TXFULL Position
| #define I2S_STATUS0_TXOVIF_Msk (0x1ul << I2S_STATUS0_TXOVIF_Pos) |
I2S_T::STATUS0: TXOVIF Mask
| #define I2S_STATUS0_TXOVIF_Pos (17) |
I2S_T::STATUS0: TXOVIF Position
| #define I2S_STATUS0_TXTHIF_Msk (0x1ul << I2S_STATUS0_TXTHIF_Pos) |
I2S_T::STATUS0: TXTHIF Mask
| #define I2S_STATUS0_TXTHIF_Pos (18) |
I2S_T::STATUS0: TXTHIF Position
| #define I2S_STATUS0_TXUDIF_Msk (0x1ul << I2S_STATUS0_TXUDIF_Pos) |
I2S_T::STATUS0: TXUDIF Mask
| #define I2S_STATUS0_TXUDIF_Pos (16) |
I2S_T::STATUS0: TXUDIF Position
| #define I2S_STATUS1_CH0ZCIF_Msk (0x1ul << I2S_STATUS1_CH0ZCIF_Pos) |
I2S_T::STATUS1: CH0ZCIF Mask
| #define I2S_STATUS1_CH0ZCIF_Pos (0) |
I2S_T::STATUS1: CH0ZCIF Position
| #define I2S_STATUS1_CH1ZCIF_Msk (0x1ul << I2S_STATUS1_CH1ZCIF_Pos) |
I2S_T::STATUS1: CH1ZCIF Mask
| #define I2S_STATUS1_CH1ZCIF_Pos (1) |
I2S_T::STATUS1: CH1ZCIF Position
| #define I2S_STATUS1_CH2ZCIF_Msk (0x1ul << I2S_STATUS1_CH2ZCIF_Pos) |
I2S_T::STATUS1: CH2ZCIF Mask
| #define I2S_STATUS1_CH2ZCIF_Pos (2) |
I2S_T::STATUS1: CH2ZCIF Position
| #define I2S_STATUS1_CH3ZCIF_Msk (0x1ul << I2S_STATUS1_CH3ZCIF_Pos) |
I2S_T::STATUS1: CH3ZCIF Mask
| #define I2S_STATUS1_CH3ZCIF_Pos (3) |
I2S_T::STATUS1: CH3ZCIF Position
| #define I2S_STATUS1_CH4ZCIF_Msk (0x1ul << I2S_STATUS1_CH4ZCIF_Pos) |
I2S_T::STATUS1: CH4ZCIF Mask
| #define I2S_STATUS1_CH4ZCIF_Pos (4) |
I2S_T::STATUS1: CH4ZCIF Position
| #define I2S_STATUS1_CH5ZCIF_Msk (0x1ul << I2S_STATUS1_CH5ZCIF_Pos) |
I2S_T::STATUS1: CH5ZCIF Mask
| #define I2S_STATUS1_CH5ZCIF_Pos (5) |
I2S_T::STATUS1: CH5ZCIF Position
| #define I2S_STATUS1_CH6ZCIF_Msk (0x1ul << I2S_STATUS1_CH6ZCIF_Pos) |
I2S_T::STATUS1: CH6ZCIF Mask
| #define I2S_STATUS1_CH6ZCIF_Pos (6) |
I2S_T::STATUS1: CH6ZCIF Position
| #define I2S_STATUS1_CH7ZCIF_Msk (0x1ul << I2S_STATUS1_CH7ZCIF_Pos) |
I2S_T::STATUS1: CH7ZCIF Mask
| #define I2S_STATUS1_CH7ZCIF_Pos (7) |
I2S_T::STATUS1: CH7ZCIF Position
| #define I2S_STATUS1_RXCNT_Msk (0x1ful << I2S_STATUS1_RXCNT_Pos) |
I2S_T::STATUS1: RXCNT Mask
| #define I2S_STATUS1_RXCNT_Pos (16) |
I2S_T::STATUS1: RXCNT Position
| #define I2S_STATUS1_TXCNT_Msk (0x1ful << I2S_STATUS1_TXCNT_Pos) |
I2S_T::STATUS1: TXCNT Mask
| #define I2S_STATUS1_TXCNT_Pos (8) |
I2S_T::STATUS1: TXCNT Position
| #define I2S_TXFIFO_TXFIFO_Msk (0xfffffffful << I2S_TXFIFO_TXFIFO_Pos) |
I2S_T::TXFIFO: TXFIFO Mask
| #define I2S_TXFIFO_TXFIFO_Pos (0) |
I2S_T::TXFIFO: TXFIFO Position
| #define OPA_CALCTL_CALCLK0_Msk (0x3ul << OPA_CALCTL_CALCLK0_Pos) |
OPA_T::CALCTL: CALCLK0 Mask
| #define OPA_CALCTL_CALCLK0_Pos (4) |
OPA_T::CALCTL: CALCLK0 Position
| #define OPA_CALCTL_CALCLK1_Msk (0x3ul << OPA_CALCTL_CALCLK1_Pos) |
OPA_T::CALCTL: CALCLK1 Mask
| #define OPA_CALCTL_CALCLK1_Pos (6) |
OPA_T::CALCTL: CALCLK1 Position
| #define OPA_CALCTL_CALCLK2_Msk (0x3ul << OPA_CALCTL_CALCLK2_Pos) |
OPA_T::CALCTL: CALCLK2 Mask
| #define OPA_CALCTL_CALCLK2_Pos (8) |
OPA_T::CALCTL: CALCLK2 Position
| #define OPA_CALCTL_CALRVS0_Msk (0x1ul << OPA_CALCTL_CALRVS0_Pos) |
OPA_T::CALCTL: CALRVS0 Mask
| #define OPA_CALCTL_CALRVS0_Pos (16) |
OPA_T::CALCTL: CALRVS0 Position
| #define OPA_CALCTL_CALRVS1_Msk (0x1ul << OPA_CALCTL_CALRVS1_Pos) |
OPA_T::CALCTL: CALRVS1 Mask
| #define OPA_CALCTL_CALRVS1_Pos (17) |
OPA_T::CALCTL: CALRVS1 Position
| #define OPA_CALCTL_CALRVS2_Msk (0x1ul << OPA_CALCTL_CALRVS2_Pos) |
OPA_T::CALCTL: CALRVS2 Mask
| #define OPA_CALCTL_CALRVS2_Pos (18) |
OPA_T::CALCTL: CALRVS2 Position
| #define OPA_CALCTL_CALTRG0_Msk (0x1ul << OPA_CALCTL_CALTRG0_Pos) |
OPA_T::CALCTL: CALTRG0 Mask
| #define OPA_CALCTL_CALTRG0_Pos (0) |
OPA_T::CALCTL: CALTRG0 Position
| #define OPA_CALCTL_CALTRG1_Msk (0x1ul << OPA_CALCTL_CALTRG1_Pos) |
OPA_T::CALCTL: CALTRG1 Mask
| #define OPA_CALCTL_CALTRG1_Pos (1) |
OPA_T::CALCTL: CALTRG1 Position
| #define OPA_CALCTL_CALTRG2_Msk (0x1ul << OPA_CALCTL_CALTRG2_Pos) |
OPA_T::CALCTL: CALTRG2 Mask
| #define OPA_CALCTL_CALTRG2_Pos (2) |
OPA_T::CALCTL: CALTRG2 Position
| #define OPA_CALST_CALNS0_Msk (0x1ul << OPA_CALST_CALNS0_Pos) |
OPA_T::CALST: CALNS0 Mask
| #define OPA_CALST_CALNS0_Pos (1) |
OPA_T::CALST: CALNS0 Position
| #define OPA_CALST_CALNS1_Msk (0x1ul << OPA_CALST_CALNS1_Pos) |
OPA_T::CALST: CALNS1 Mask
| #define OPA_CALST_CALNS1_Pos (5) |
OPA_T::CALST: CALNS1 Position
| #define OPA_CALST_CALNS2_Msk (0x1ul << OPA_CALST_CALNS2_Pos) |
OPA_T::CALST: CALNS2 Mask
| #define OPA_CALST_CALNS2_Pos (9) |
OPA_T::CALST: CALNS2 Position
| #define OPA_CALST_CALPS0_Msk (0x1ul << OPA_CALST_CALPS0_Pos) |
OPA_T::CALST: CALPS0 Mask
| #define OPA_CALST_CALPS0_Pos (2) |
OPA_T::CALST: CALPS0 Position
| #define OPA_CALST_CALPS1_Msk (0x1ul << OPA_CALST_CALPS1_Pos) |
OPA_T::CALST: CALPS1 Mask
| #define OPA_CALST_CALPS1_Pos (6) |
OPA_T::CALST: CALPS1 Position
| #define OPA_CALST_CALPS2_Msk (0x1ul << OPA_CALST_CALPS2_Pos) |
OPA_T::CALST: CALPS2 Mask
| #define OPA_CALST_CALPS2_Pos (10) |
OPA_T::CALST: CALPS2 Position
| #define OPA_CALST_DONE0_Msk (0x1ul << OPA_CALST_DONE0_Pos) |
OPA_T::CALST: DONE0 Mask
| #define OPA_CALST_DONE0_Pos (0) |
OPA_T::CALST: DONE0 Position
| #define OPA_CALST_DONE1_Msk (0x1ul << OPA_CALST_DONE1_Pos) |
OPA_T::CALST: DONE1 Mask
| #define OPA_CALST_DONE1_Pos (4) |
OPA_T::CALST: DONE1 Position
| #define OPA_CALST_DONE2_Msk (0x1ul << OPA_CALST_DONE2_Pos) |
OPA_T::CALST: DONE2 Mask
| #define OPA_CALST_DONE2_Pos (8) |
OPA_T::CALST: DONE2 Position
| #define OPA_CTL_OPDOEN0_Msk (0x1ul << OPA_CTL_OPDOEN0_Pos) |
OPA_T::CTL: OPDOEN0 Mask
| #define OPA_CTL_OPDOEN0_Pos (4) |
OPA_T::CTL: OPDOEN0 Position
| #define OPA_CTL_OPDOEN1_Msk (0x1ul << OPA_CTL_OPDOEN1_Pos) |
OPA_T::CTL: OPDOEN1 Mask
| #define OPA_CTL_OPDOEN1_Pos (5) |
OPA_T::CTL: OPDOEN1 Position
| #define OPA_CTL_OPDOEN2_Msk (0x1ul << OPA_CTL_OPDOEN2_Pos) |
OPA_T::CTL: OPDOEN2 Mask
| #define OPA_CTL_OPDOEN2_Pos (6) |
OPA_T::CTL: OPDOEN2 Position
| #define OPA_CTL_OPDOIEN0_Msk (0x1ul << OPA_CTL_OPDOIEN0_Pos) |
OPA_T::CTL: OPDOIEN0 Mask
| #define OPA_CTL_OPDOIEN0_Pos (8) |
OPA_T::CTL: OPDOIEN0 Position
| #define OPA_CTL_OPDOIEN1_Msk (0x1ul << OPA_CTL_OPDOIEN1_Pos) |
OPA_T::CTL: OPDOIEN1 Mask
| #define OPA_CTL_OPDOIEN1_Pos (9) |
OPA_T::CTL: OPDOIEN1 Position
| #define OPA_CTL_OPDOIEN2_Msk (0x1ul << OPA_CTL_OPDOIEN2_Pos) |
OPA_T::CTL: OPDOIEN2 Mask
| #define OPA_CTL_OPDOIEN2_Pos (10) |
OPA_T::CTL: OPDOIEN2 Position
| #define OPA_CTL_OPEN0_Msk (0x1ul << OPA_CTL_OPEN0_Pos) |
OPA_T::CTL: OPEN0 Mask
| #define OPA_CTL_OPEN0_Pos (0) |
@addtogroup OPA_CONST OPA Bit Field Definition Constant Definitions for OPA Controller
OPA_T::CTL: OPEN0 Position
| #define OPA_CTL_OPEN1_Msk (0x1ul << OPA_CTL_OPEN1_Pos) |
OPA_T::CTL: OPEN1 Mask
| #define OPA_CTL_OPEN1_Pos (1) |
OPA_T::CTL: OPEN1 Position
| #define OPA_CTL_OPEN2_Msk (0x1ul << OPA_CTL_OPEN2_Pos) |
OPA_T::CTL: OPEN2 Mask
| #define OPA_CTL_OPEN2_Pos (2) |
OPA_T::CTL: OPEN2 Position
| #define OPA_STATUS_OPDO0_Msk (0x1ul << OPA_STATUS_OPDO0_Pos) |
OPA_T::STATUS: OPDO0 Mask
| #define OPA_STATUS_OPDO0_Pos (0) |
OPA_T::STATUS: OPDO0 Position
| #define OPA_STATUS_OPDO1_Msk (0x1ul << OPA_STATUS_OPDO1_Pos) |
OPA_T::STATUS: OPDO1 Mask
| #define OPA_STATUS_OPDO1_Pos (1) |
OPA_T::STATUS: OPDO1 Position
| #define OPA_STATUS_OPDO2_Msk (0x1ul << OPA_STATUS_OPDO2_Pos) |
OPA_T::STATUS: OPDO2 Mask
| #define OPA_STATUS_OPDO2_Pos (2) |
OPA_T::STATUS: OPDO2 Position
| #define OPA_STATUS_OPDOIF0_Msk (0x1ul << OPA_STATUS_OPDOIF0_Pos) |
OPA_T::STATUS: OPDOIF0 Mask
| #define OPA_STATUS_OPDOIF0_Pos (4) |
OPA_T::STATUS: OPDOIF0 Position
| #define OPA_STATUS_OPDOIF1_Msk (0x1ul << OPA_STATUS_OPDOIF1_Pos) |
OPA_T::STATUS: OPDOIF1 Mask
| #define OPA_STATUS_OPDOIF1_Pos (5) |
OPA_T::STATUS: OPDOIF1 Position
| #define OPA_STATUS_OPDOIF2_Msk (0x1ul << OPA_STATUS_OPDOIF2_Pos) |
OPA_T::STATUS: OPDOIF2 Mask
| #define OPA_STATUS_OPDOIF2_Pos (6) |
OPA_T::STATUS: OPDOIF2 Position
| #define OTG_CTL_BUSREQ_Msk (0x1ul << OTG_CTL_BUSREQ_Pos) |
OTG_T::CTL: BUSREQ Mask
| #define OTG_CTL_BUSREQ_Pos (1) |
OTG_T::CTL: BUSREQ Position
| #define OTG_CTL_HNPREQEN_Msk (0x1ul << OTG_CTL_HNPREQEN_Pos) |
OTG_T::CTL: HNPREQEN Mask
| #define OTG_CTL_HNPREQEN_Pos (2) |
OTG_T::CTL: HNPREQEN Position
| #define OTG_CTL_OTGEN_Msk (0x1ul << OTG_CTL_OTGEN_Pos) |
OTG_T::CTL: OTGEN Mask
| #define OTG_CTL_OTGEN_Pos (4) |
OTG_T::CTL: OTGEN Position
| #define OTG_CTL_VBUSDROP_Msk (0x1ul << OTG_CTL_VBUSDROP_Pos) |
OTG_T::CTL: VBUSDROP Mask
| #define OTG_CTL_VBUSDROP_Pos (0) |
@addtogroup OTG_CONST OTG Bit Field Definition Constant Definitions for OTG Controller
OTG_T::CTL: VBUSDROP Position
| #define OTG_CTL_WKEN_Msk (0x1ul << OTG_CTL_WKEN_Pos) |
OTG_T::CTL: WKEN Mask
| #define OTG_CTL_WKEN_Pos (5) |
OTG_T::CTL: WKEN Position
| #define OTG_INTEN_AVLDCHGIEN_Msk (0x1ul << OTG_INTEN_AVLDCHGIEN_Pos) |
OTG_T::INTEN: AVLDCHGIEN Mask
| #define OTG_INTEN_AVLDCHGIEN_Pos (9) |
OTG_T::INTEN: AVLDCHGIEN Position
| #define OTG_INTEN_BVLDCHGIEN_Msk (0x1ul << OTG_INTEN_BVLDCHGIEN_Pos) |
OTG_T::INTEN: BVLDCHGIEN Mask
| #define OTG_INTEN_BVLDCHGIEN_Pos (8) |
OTG_T::INTEN: BVLDCHGIEN Position
| #define OTG_INTEN_GOIDLEIEN_Msk (0x1ul << OTG_INTEN_GOIDLEIEN_Pos) |
OTG_T::INTEN: GOIDLEIEN Mask
| #define OTG_INTEN_GOIDLEIEN_Pos (4) |
OTG_T::INTEN: GOIDLEIEN Position
| #define OTG_INTEN_HNPFIEN_Msk (0x1ul << OTG_INTEN_HNPFIEN_Pos) |
OTG_T::INTEN: HNPFIEN Mask
| #define OTG_INTEN_HNPFIEN_Pos (3) |
OTG_T::INTEN: HNPFIEN Position
| #define OTG_INTEN_HOSTIEN_Msk (0x1ul << OTG_INTEN_HOSTIEN_Pos) |
OTG_T::INTEN: HOSTIEN Mask
| #define OTG_INTEN_HOSTIEN_Pos (7) |
OTG_T::INTEN: HOSTIEN Position
| #define OTG_INTEN_IDCHGIEN_Msk (0x1ul << OTG_INTEN_IDCHGIEN_Pos) |
OTG_T::INTEN: IDCHGIEN Mask
| #define OTG_INTEN_IDCHGIEN_Pos (5) |
OTG_T::INTEN: IDCHGIEN Position
| #define OTG_INTEN_PDEVIEN_Msk (0x1ul << OTG_INTEN_PDEVIEN_Pos) |
OTG_T::INTEN: PDEVIEN Mask
| #define OTG_INTEN_PDEVIEN_Pos (6) |
OTG_T::INTEN: PDEVIEN Position
| #define OTG_INTEN_ROLECHGIEN_Msk (0x1ul << OTG_INTEN_ROLECHGIEN_Pos) |
OTG_T::INTEN: ROLECHGIEN Mask
| #define OTG_INTEN_ROLECHGIEN_Pos (0) |
OTG_T::INTEN: ROLECHGIEN Position
| #define OTG_INTEN_SECHGIEN_Msk (0x1ul << OTG_INTEN_SECHGIEN_Pos) |
OTG_T::INTEN: SECHGIEN Mask
| #define OTG_INTEN_SECHGIEN_Pos (11) |
OTG_T::INTEN: SECHGIEN Position
| #define OTG_INTEN_SRPDETIEN_Msk (0x1ul << OTG_INTEN_SRPDETIEN_Pos) |
OTG_T::INTEN: SRPDETIEN Mask
| #define OTG_INTEN_SRPDETIEN_Pos (13) |
OTG_T::INTEN: SRPDETIEN Position
| #define OTG_INTEN_SRPFIEN_Msk (0x1ul << OTG_INTEN_SRPFIEN_Pos) |
OTG_T::INTEN: SRPFIEN Mask
| #define OTG_INTEN_SRPFIEN_Pos (2) |
OTG_T::INTEN: SRPFIEN Position
| #define OTG_INTEN_VBCHGIEN_Msk (0x1ul << OTG_INTEN_VBCHGIEN_Pos) |
OTG_T::INTEN: VBCHGIEN Mask
| #define OTG_INTEN_VBCHGIEN_Pos (10) |
OTG_T::INTEN: VBCHGIEN Position
| #define OTG_INTEN_VBEIEN_Msk (0x1ul << OTG_INTEN_VBEIEN_Pos) |
OTG_T::INTEN: VBEIEN Mask
| #define OTG_INTEN_VBEIEN_Pos (1) |
OTG_T::INTEN: VBEIEN Position
| #define OTG_INTSTS_AVLDCHGIF_Msk (0x1ul << OTG_INTSTS_AVLDCHGIF_Pos) |
OTG_T::INTSTS: AVLDCHGIF Mask
| #define OTG_INTSTS_AVLDCHGIF_Pos (9) |
OTG_T::INTSTS: AVLDCHGIF Position
| #define OTG_INTSTS_BVLDCHGIF_Msk (0x1ul << OTG_INTSTS_BVLDCHGIF_Pos) |
OTG_T::INTSTS: BVLDCHGIF Mask
| #define OTG_INTSTS_BVLDCHGIF_Pos (8) |
OTG_T::INTSTS: BVLDCHGIF Position
| #define OTG_INTSTS_GOIDLEIF_Msk (0x1ul << OTG_INTSTS_GOIDLEIF_Pos) |
OTG_T::INTSTS: GOIDLEIF Mask
| #define OTG_INTSTS_GOIDLEIF_Pos (4) |
OTG_T::INTSTS: GOIDLEIF Position
| #define OTG_INTSTS_HNPFIF_Msk (0x1ul << OTG_INTSTS_HNPFIF_Pos) |
OTG_T::INTSTS: HNPFIF Mask
| #define OTG_INTSTS_HNPFIF_Pos (3) |
OTG_T::INTSTS: HNPFIF Position
| #define OTG_INTSTS_HOSTIF_Msk (0x1ul << OTG_INTSTS_HOSTIF_Pos) |
OTG_T::INTSTS: HOSTIF Mask
| #define OTG_INTSTS_HOSTIF_Pos (7) |
OTG_T::INTSTS: HOSTIF Position
| #define OTG_INTSTS_IDCHGIF_Msk (0x1ul << OTG_INTSTS_IDCHGIF_Pos) |
OTG_T::INTSTS: IDCHGIF Mask
| #define OTG_INTSTS_IDCHGIF_Pos (5) |
OTG_T::INTSTS: IDCHGIF Position
| #define OTG_INTSTS_PDEVIF_Msk (0x1ul << OTG_INTSTS_PDEVIF_Pos) |
OTG_T::INTSTS: PDEVIF Mask
| #define OTG_INTSTS_PDEVIF_Pos (6) |
OTG_T::INTSTS: PDEVIF Position
| #define OTG_INTSTS_ROLECHGIF_Msk (0x1ul << OTG_INTSTS_ROLECHGIF_Pos) |
OTG_T::INTSTS: ROLECHGIF Mask
| #define OTG_INTSTS_ROLECHGIF_Pos (0) |
OTG_T::INTSTS: ROLECHGIF Position
| #define OTG_INTSTS_SECHGIF_Msk (0x1ul << OTG_INTSTS_SECHGIF_Pos) |
OTG_T::INTSTS: SECHGIF Mask
| #define OTG_INTSTS_SECHGIF_Pos (11) |
OTG_T::INTSTS: SECHGIF Position
| #define OTG_INTSTS_SRPDETIF_Msk (0x1ul << OTG_INTSTS_SRPDETIF_Pos) |
OTG_T::INTSTS: SRPDETIF Mask
| #define OTG_INTSTS_SRPDETIF_Pos (13) |
OTG_T::INTSTS: SRPDETIF Position
| #define OTG_INTSTS_SRPFIF_Msk (0x1ul << OTG_INTSTS_SRPFIF_Pos) |
OTG_T::INTSTS: SRPFIF Mask
| #define OTG_INTSTS_SRPFIF_Pos (2) |
OTG_T::INTSTS: SRPFIF Position
| #define OTG_INTSTS_VBCHGIF_Msk (0x1ul << OTG_INTSTS_VBCHGIF_Pos) |
OTG_T::INTSTS: VBCHGIF Mask
| #define OTG_INTSTS_VBCHGIF_Pos (10) |
OTG_T::INTSTS: VBCHGIF Position
| #define OTG_INTSTS_VBEIF_Msk (0x1ul << OTG_INTSTS_VBEIF_Pos) |
OTG_T::INTSTS: VBEIF Mask
| #define OTG_INTSTS_VBEIF_Pos (1) |
OTG_T::INTSTS: VBEIF Position
| #define OTG_PHYCTL_IDDETEN_Msk (0x1ul << OTG_PHYCTL_IDDETEN_Pos) |
OTG_T::PHYCTL: IDDETEN Mask
| #define OTG_PHYCTL_IDDETEN_Pos (1) |
OTG_T::PHYCTL: IDDETEN Position
| #define OTG_PHYCTL_OTGPHYEN_Msk (0x1ul << OTG_PHYCTL_OTGPHYEN_Pos) |
OTG_T::PHYCTL: OTGPHYEN Mask
| #define OTG_PHYCTL_OTGPHYEN_Pos (0) |
OTG_T::PHYCTL: OTGPHYEN Position
| #define OTG_PHYCTL_VBENPOL_Msk (0x1ul << OTG_PHYCTL_VBENPOL_Pos) |
OTG_T::PHYCTL: VBENPOL Mask
| #define OTG_PHYCTL_VBENPOL_Pos (4) |
OTG_T::PHYCTL: VBENPOL Position
| #define OTG_PHYCTL_VBSTSPOL_Msk (0x1ul << OTG_PHYCTL_VBSTSPOL_Pos) |
OTG_T::PHYCTL: VBSTSPOL Mask
| #define OTG_PHYCTL_VBSTSPOL_Pos (5) |
OTG_T::PHYCTL: VBSTSPOL Position
| #define OTG_STATUS_ASHOST_Msk (0x1ul << OTG_STATUS_ASHOST_Pos) |
OTG_T::STATUS: ASHOST Mask
| #define OTG_STATUS_ASHOST_Pos (7) |
OTG_T::STATUS: ASHOST Position
| #define OTG_STATUS_ASPERI_Msk (0x1ul << OTG_STATUS_ASPERI_Pos) |
OTG_T::STATUS: ASPERI Mask
| #define OTG_STATUS_ASPERI_Pos (6) |
OTG_T::STATUS: ASPERI Position
| #define OTG_STATUS_AVLD_Msk (0x1ul << OTG_STATUS_AVLD_Pos) |
OTG_T::STATUS: AVLD Mask
| #define OTG_STATUS_AVLD_Pos (4) |
OTG_T::STATUS: AVLD Position
| #define OTG_STATUS_BVLD_Msk (0x1ul << OTG_STATUS_BVLD_Pos) |
OTG_T::STATUS: BVLD Mask
| #define OTG_STATUS_BVLD_Pos (3) |
OTG_T::STATUS: BVLD Position
| #define OTG_STATUS_IDSTS_Msk (0x1ul << OTG_STATUS_IDSTS_Pos) |
OTG_T::STATUS: IDSTS Mask
| #define OTG_STATUS_IDSTS_Pos (1) |
OTG_T::STATUS: IDSTS Position
| #define OTG_STATUS_OVERCUR_Msk (0x1ul << OTG_STATUS_OVERCUR_Pos) |
OTG_T::STATUS: OVERCUR Mask
| #define OTG_STATUS_OVERCUR_Pos (0) |
OTG_T::STATUS: OVERCUR Position
| #define OTG_STATUS_SESSEND_Msk (0x1ul << OTG_STATUS_SESSEND_Pos) |
OTG_T::STATUS: SESSEND Mask
| #define OTG_STATUS_SESSEND_Pos (2) |
OTG_T::STATUS: SESSEND Position
| #define OTG_STATUS_VBUSVLD_Msk (0x1ul << OTG_STATUS_VBUSVLD_Pos) |
OTG_T::STATUS: VBUSVLD Mask
| #define OTG_STATUS_VBUSVLD_Pos (5) |
OTG_T::STATUS: VBUSVLD Position
| #define PDMA_ABTSTS_ABTIF0_Msk (0x1ul << PDMA_ABTSTS_ABTIF0_Pos) |
PDMA_T::ABTSTS: ABTIF0 Mask
Definition at line 685 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF0_Pos (0) |
PDMA_T::ABTSTS: ABTIF0 Position
Definition at line 684 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF10_Msk (0x1ul << PDMA_ABTSTS_ABTIF10_Pos) |
PDMA_T::ABTSTS: ABTIF10 Mask
Definition at line 715 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF10_Pos (10) |
PDMA_T::ABTSTS: ABTIF10 Position
Definition at line 714 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF11_Msk (0x1ul << PDMA_ABTSTS_ABTIF11_Pos) |
PDMA_T::ABTSTS: ABTIF11 Mask
Definition at line 718 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF11_Pos (11) |
PDMA_T::ABTSTS: ABTIF11 Position
Definition at line 717 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF12_Msk (0x1ul << PDMA_ABTSTS_ABTIF12_Pos) |
PDMA_T::ABTSTS: ABTIF12 Mask
Definition at line 721 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF12_Pos (12) |
PDMA_T::ABTSTS: ABTIF12 Position
Definition at line 720 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF13_Msk (0x1ul << PDMA_ABTSTS_ABTIF13_Pos) |
PDMA_T::ABTSTS: ABTIF13 Mask
Definition at line 724 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF13_Pos (13) |
PDMA_T::ABTSTS: ABTIF13 Position
Definition at line 723 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF14_Msk (0x1ul << PDMA_ABTSTS_ABTIF14_Pos) |
PDMA_T::ABTSTS: ABTIF14 Mask
Definition at line 727 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF14_Pos (14) |
PDMA_T::ABTSTS: ABTIF14 Position
Definition at line 726 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF15_Msk (0x1ul << PDMA_ABTSTS_ABTIF15_Pos) |
PDMA_T::ABTSTS: ABTIF15 Mask
Definition at line 730 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF15_Pos (15) |
PDMA_T::ABTSTS: ABTIF15 Position
Definition at line 729 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF1_Msk (0x1ul << PDMA_ABTSTS_ABTIF1_Pos) |
PDMA_T::ABTSTS: ABTIF1 Mask
Definition at line 688 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF1_Pos (1) |
PDMA_T::ABTSTS: ABTIF1 Position
Definition at line 687 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF2_Msk (0x1ul << PDMA_ABTSTS_ABTIF2_Pos) |
PDMA_T::ABTSTS: ABTIF2 Mask
Definition at line 691 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF2_Pos (2) |
PDMA_T::ABTSTS: ABTIF2 Position
Definition at line 690 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF3_Msk (0x1ul << PDMA_ABTSTS_ABTIF3_Pos) |
PDMA_T::ABTSTS: ABTIF3 Mask
Definition at line 694 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF3_Pos (3) |
PDMA_T::ABTSTS: ABTIF3 Position
Definition at line 693 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF4_Msk (0x1ul << PDMA_ABTSTS_ABTIF4_Pos) |
PDMA_T::ABTSTS: ABTIF4 Mask
Definition at line 697 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF4_Pos (4) |
PDMA_T::ABTSTS: ABTIF4 Position
Definition at line 696 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF5_Msk (0x1ul << PDMA_ABTSTS_ABTIF5_Pos) |
PDMA_T::ABTSTS: ABTIF5 Mask
Definition at line 700 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF5_Pos (5) |
PDMA_T::ABTSTS: ABTIF5 Position
Definition at line 699 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF6_Msk (0x1ul << PDMA_ABTSTS_ABTIF6_Pos) |
PDMA_T::ABTSTS: ABTIF6 Mask
Definition at line 703 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF6_Pos (6) |
PDMA_T::ABTSTS: ABTIF6 Position
Definition at line 702 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF7_Msk (0x1ul << PDMA_ABTSTS_ABTIF7_Pos) |
PDMA_T::ABTSTS: ABTIF7 Mask
Definition at line 706 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF7_Pos (7) |
PDMA_T::ABTSTS: ABTIF7 Position
Definition at line 705 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF8_Msk (0x1ul << PDMA_ABTSTS_ABTIF8_Pos) |
PDMA_T::ABTSTS: ABTIF8 Mask
Definition at line 709 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF8_Pos (8) |
PDMA_T::ABTSTS: ABTIF8 Position
Definition at line 708 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF9_Msk (0x1ul << PDMA_ABTSTS_ABTIF9_Pos) |
PDMA_T::ABTSTS: ABTIF9 Mask
Definition at line 712 of file pdma_reg.h.
| #define PDMA_ABTSTS_ABTIF9_Pos (9) |
PDMA_T::ABTSTS: ABTIF9 Position
Definition at line 711 of file pdma_reg.h.
| #define PDMA_AICTLn_DAICNT_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) |
PDMA_T::AICTLn: DAICNT Mask
Definition at line 874 of file pdma_reg.h.
| #define PDMA_AICTLn_DAICNT_Pos (16) |
PDMA_T::AICTLn: DAICNT Position
Definition at line 873 of file pdma_reg.h.
| #define PDMA_AICTLn_SAICNT_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) |
PDMA_T::AICTLn: SAICNT Mask
Definition at line 871 of file pdma_reg.h.
| #define PDMA_AICTLn_SAICNT_Pos (0) |
PDMA_T::AICTLn: SAICNT Position
Definition at line 870 of file pdma_reg.h.
| #define PDMA_ALIGN_ALIGNn_Msk (0xfffful << PDMA_ALIGN_ALIGNn_Pos) |
PDMA_T::ALIGN: ALIGNn Mask
Definition at line 781 of file pdma_reg.h.
| #define PDMA_ALIGN_ALIGNn_Pos (0) |
PDMA_T::ALIGN: ALIGNn Position
Definition at line 780 of file pdma_reg.h.
| #define PDMA_ASOCRn_DASOL_Msk (0xfffful << PDMA_ASOCRn_DASOL_Pos) |
PDMA_T::ASOCRn: DASOL Mask
Definition at line 865 of file pdma_reg.h.
| #define PDMA_ASOCRn_DASOL_Pos (16) |
PDMA_T::ASOCRn: DASOL Position
Definition at line 864 of file pdma_reg.h.
| #define PDMA_ASOCRn_SASOL_Msk (0xfffful << PDMA_ASOCRn_SASOL_Pos) |
PDMA_T::ASOCRn: SASOL Mask
Definition at line 862 of file pdma_reg.h.
| #define PDMA_ASOCRn_SASOL_Pos (0) |
PDMA_T::ASOCRn: SASOL Position
Definition at line 861 of file pdma_reg.h.
| #define PDMA_CHCTL_CHENn_Msk (0xfffful << PDMA_CHCTL_CHENn_Pos) |
PDMA_T::CHCTL: CHENn Mask
Definition at line 649 of file pdma_reg.h.
| #define PDMA_CHCTL_CHENn_Pos (0) |
PDMA_T::CHCTL: CHENn Position
Definition at line 648 of file pdma_reg.h.
| #define PDMA_CHRST_CHnRST_Msk (0xfffful << PDMA_CHRST_CHnRST_Pos) |
PDMA_T::CHRST: CHnRST Mask
Definition at line 808 of file pdma_reg.h.
| #define PDMA_CHRST_CHnRST_Pos (0) |
PDMA_T::CHRST: CHnRST Position
Definition at line 807 of file pdma_reg.h.
| #define PDMA_CURSCAT_CURADDR_Msk (0xfffffffful << PDMA_CURSCAT_CURADDR_Pos) |
PDMA_T::CURSCAT: CURADDR Mask
Definition at line 646 of file pdma_reg.h.
| #define PDMA_CURSCAT_CURADDR_Pos (0) |
PDMA_T::CURSCAT: CURADDR Position
Definition at line 645 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_BURSIZE_Msk (0x7ul << PDMA_DSCT_CTL_BURSIZE_Pos) |
PDMA_T::DSCT_CTL: BURSIZE Mask
Definition at line 610 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_BURSIZE_Pos (4) |
PDMA_T::DSCT_CTL: BURSIZE Position
Definition at line 609 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_DAINC_Msk (0x3ul << PDMA_DSCT_CTL_DAINC_Pos) |
PDMA_T::DSCT_CTL: DAINC Mask
Definition at line 619 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_DAINC_Pos (10) |
PDMA_T::DSCT_CTL: DAINC Position
Definition at line 618 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_OPMODE_Msk (0x3ul << PDMA_DSCT_CTL_OPMODE_Pos) |
PDMA_T::DSCT_CTL: OPMODE Mask
Definition at line 604 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_OPMODE_Pos (0) |
@addtogroup PDMA_CONST PDMA Bit Field Definition Constant Definitions for PDMA Controller
PDMA_T::DSCT_CTL: OPMODE Position
Definition at line 603 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_SAINC_Msk (0x3ul << PDMA_DSCT_CTL_SAINC_Pos) |
PDMA_T::DSCT_CTL: SAINC Mask
Definition at line 616 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_SAINC_Pos (8) |
PDMA_T::DSCT_CTL: SAINC Position
Definition at line 615 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_STRIDEEN_Msk (0x1ul << PDMA_DSCT_CTL_STRIDEEN_Pos) |
PDMA_T::DSCT_CTL: STRIDEEN Mask
Definition at line 628 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_STRIDEEN_Pos (15) |
PDMA_T::DSCT_CTL: STRIDEEN Position
Definition at line 627 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_TBINTDIS_Msk (0x1ul << PDMA_DSCT_CTL_TBINTDIS_Pos) |
PDMA_T::DSCT_CTL: TBINTDIS Mask
Definition at line 613 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_TBINTDIS_Pos (7) |
PDMA_T::DSCT_CTL: TBINTDIS Position
Definition at line 612 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_TXACK_Msk (0x1ul << PDMA_DSCT_CTL_TXACK_Pos) |
PDMA_T::DSCT_CTL: TXACK Mask
Definition at line 625 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_TXACK_Pos (14) |
PDMA_T::DSCT_CTL: TXACK Position
Definition at line 624 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_TXCNT_Msk (0xfffful << PDMA_DSCT_CTL_TXCNT_Pos) |
PDMA_T::DSCT_CTL: TXCNT Mask
Definition at line 631 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_TXCNT_Pos (16) |
PDMA_T::DSCT_CTL: TXCNT Position
Definition at line 630 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_TXTYPE_Msk (0x1ul << PDMA_DSCT_CTL_TXTYPE_Pos) |
PDMA_T::DSCT_CTL: TXTYPE Mask
Definition at line 607 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_TXTYPE_Pos (2) |
PDMA_T::DSCT_CTL: TXTYPE Position
Definition at line 606 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_TXWIDTH_Msk (0x3ul << PDMA_DSCT_CTL_TXWIDTH_Pos) |
PDMA_T::DSCT_CTL: TXWIDTH Mask
Definition at line 622 of file pdma_reg.h.
| #define PDMA_DSCT_CTL_TXWIDTH_Pos (12) |
PDMA_T::DSCT_CTL: TXWIDTH Position
Definition at line 621 of file pdma_reg.h.
| #define PDMA_DSCT_DA_DA_Msk (0xfffffffful << PDMA_DSCT_DA_DA_Pos) |
PDMA_T::DSCT_DA: DA Mask
Definition at line 637 of file pdma_reg.h.
| #define PDMA_DSCT_DA_DA_Pos (0) |
PDMA_T::DSCT_DA: DA Position
Definition at line 636 of file pdma_reg.h.
| #define PDMA_DSCT_NEXT_EXENEXT_Msk (0xfffful << PDMA_DSCT_NEXT_EXENEXT_Pos) |
PDMA_T::DSCT_FIRST: NEXT Mask
Definition at line 643 of file pdma_reg.h.
| #define PDMA_DSCT_NEXT_EXENEXT_Pos (16) |
PDMA_T::DSCT_FIRST: NEXT Position
Definition at line 642 of file pdma_reg.h.
| #define PDMA_DSCT_NEXT_NEXT_Msk (0xfffful << PDMA_DSCT_NEXT_NEXT_Pos) |
PDMA_T::DSCT_NEXT: NEXT Mask
Definition at line 640 of file pdma_reg.h.
| #define PDMA_DSCT_NEXT_NEXT_Pos (0) |
PDMA_T::DSCT_NEXT: NEXT Position
Definition at line 639 of file pdma_reg.h.
| #define PDMA_DSCT_SA_SA_Msk (0xfffffffful << PDMA_DSCT_SA_SA_Pos) |
PDMA_T::DSCT_SA: SA Mask
Definition at line 634 of file pdma_reg.h.
| #define PDMA_DSCT_SA_SA_Pos (0) |
PDMA_T::DSCT_SA: SA Position
Definition at line 633 of file pdma_reg.h.
| #define PDMA_INTEN_INTENn_Msk (0xfffful << PDMA_INTEN_INTENn_Pos) |
PDMA_T::INTEN: INTENn Mask
Definition at line 667 of file pdma_reg.h.
| #define PDMA_INTEN_INTENn_Pos (0) |
PDMA_T::INTEN: INTENn Position
Definition at line 666 of file pdma_reg.h.
| #define PDMA_INTSTS_ABTIF_Msk (0x1ul << PDMA_INTSTS_ABTIF_Pos) |
PDMA_T::INTSTS: ABTIF Mask
Definition at line 670 of file pdma_reg.h.
| #define PDMA_INTSTS_ABTIF_Pos (0) |
PDMA_T::INTSTS: ABTIF Position
Definition at line 669 of file pdma_reg.h.
| #define PDMA_INTSTS_ALIGNF_Msk (0x1ul << PDMA_INTSTS_ALIGNF_Pos) |
PDMA_T::INTSTS: ALIGNF Mask
Definition at line 676 of file pdma_reg.h.
| #define PDMA_INTSTS_ALIGNF_Pos (2) |
PDMA_T::INTSTS: ALIGNF Position
Definition at line 675 of file pdma_reg.h.
| #define PDMA_INTSTS_REQTOF0_Msk (0x1ul << PDMA_INTSTS_REQTOF0_Pos) |
PDMA_T::INTSTS: REQTOF0 Mask
Definition at line 679 of file pdma_reg.h.
| #define PDMA_INTSTS_REQTOF0_Pos (8) |
PDMA_T::INTSTS: REQTOF0 Position
Definition at line 678 of file pdma_reg.h.
| #define PDMA_INTSTS_REQTOF1_Msk (0x1ul << PDMA_INTSTS_REQTOF1_Pos) |
PDMA_T::INTSTS: REQTOF1 Mask
Definition at line 682 of file pdma_reg.h.
| #define PDMA_INTSTS_REQTOF1_Pos (9) |
PDMA_T::INTSTS: REQTOF1 Position
Definition at line 681 of file pdma_reg.h.
| #define PDMA_INTSTS_TDIF_Msk (0x1ul << PDMA_INTSTS_TDIF_Pos) |
PDMA_T::INTSTS: TDIF Mask
Definition at line 673 of file pdma_reg.h.
| #define PDMA_INTSTS_TDIF_Pos (1) |
PDMA_T::INTSTS: TDIF Position
Definition at line 672 of file pdma_reg.h.
| #define PDMA_PAUSE_PAUSEn_Msk (0xfffful << PDMA_PAUSE_PAUSEn_Pos) |
PDMA_T::PAUSE: PAUSEn Mask
Definition at line 652 of file pdma_reg.h.
| #define PDMA_PAUSE_PAUSEn_Pos (0) |
PDMA_T::PAUSE: PAUSEn Position
Definition at line 651 of file pdma_reg.h.
| #define PDMA_PRICLR_FPRICLRn_Msk (0xfffful << PDMA_PRICLR_FPRICLRn_Pos) |
PDMA_T::PRICLR: FPRICLRn Mask
Definition at line 664 of file pdma_reg.h.
| #define PDMA_PRICLR_FPRICLRn_Pos (0) |
PDMA_T::PRICLR: FPRICLRn Position
Definition at line 663 of file pdma_reg.h.
| #define PDMA_PRISET_FPRISETn_Msk (0xfffful << PDMA_PRISET_FPRISETn_Pos) |
PDMA_T::PRISET: FPRISETn Mask
Definition at line 661 of file pdma_reg.h.
| #define PDMA_PRISET_FPRISETn_Pos (0) |
PDMA_T::PRISET: FPRISETn Position
Definition at line 660 of file pdma_reg.h.
| #define PDMA_RCNTn_RCNT_Msk (0xfffful << PDMA_STCRn_RCNT_Pos) |
PDMA_T::RCNTn: RCNT Mask
Definition at line 868 of file pdma_reg.h.
| #define PDMA_RCNTn_RCNT_Pos (0) |
PDMA_T::RCNTn: RCNT Position
Definition at line 867 of file pdma_reg.h.
| #define PDMA_REQSEL0_3_REQSRC0_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC0_Pos) |
PDMA_T::REQSEL0_3: REQSRC0 Mask
Definition at line 811 of file pdma_reg.h.
| #define PDMA_REQSEL0_3_REQSRC0_Pos (0) |
PDMA_T::REQSEL0_3: REQSRC0 Position
Definition at line 810 of file pdma_reg.h.
| #define PDMA_REQSEL0_3_REQSRC1_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC1_Pos) |
PDMA_T::REQSEL0_3: REQSRC1 Mask
Definition at line 814 of file pdma_reg.h.
| #define PDMA_REQSEL0_3_REQSRC1_Pos (8) |
PDMA_T::REQSEL0_3: REQSRC1 Position
Definition at line 813 of file pdma_reg.h.
| #define PDMA_REQSEL0_3_REQSRC2_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC2_Pos) |
PDMA_T::REQSEL0_3: REQSRC2 Mask
Definition at line 817 of file pdma_reg.h.
| #define PDMA_REQSEL0_3_REQSRC2_Pos (16) |
PDMA_T::REQSEL0_3: REQSRC2 Position
Definition at line 816 of file pdma_reg.h.
| #define PDMA_REQSEL0_3_REQSRC3_Msk (0x7ful << PDMA_REQSEL0_3_REQSRC3_Pos) |
PDMA_T::REQSEL0_3: REQSRC3 Mask
Definition at line 820 of file pdma_reg.h.
| #define PDMA_REQSEL0_3_REQSRC3_Pos (24) |
PDMA_T::REQSEL0_3: REQSRC3 Position
Definition at line 819 of file pdma_reg.h.
| #define PDMA_REQSEL12_15_REQSRC12_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC12_Pos) |
PDMA_T::REQSEL12_15: REQSRC12 Mask
Definition at line 847 of file pdma_reg.h.
| #define PDMA_REQSEL12_15_REQSRC12_Pos (0) |
PDMA_T::REQSEL12_15: REQSRC12 Position
Definition at line 846 of file pdma_reg.h.
| #define PDMA_REQSEL12_15_REQSRC13_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC13_Pos) |
PDMA_T::REQSEL12_15: REQSRC13 Mask
Definition at line 850 of file pdma_reg.h.
| #define PDMA_REQSEL12_15_REQSRC13_Pos (8) |
PDMA_T::REQSEL12_15: REQSRC13 Position
Definition at line 849 of file pdma_reg.h.
| #define PDMA_REQSEL12_15_REQSRC14_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC14_Pos) |
PDMA_T::REQSEL12_15: REQSRC14 Mask
Definition at line 853 of file pdma_reg.h.
| #define PDMA_REQSEL12_15_REQSRC14_Pos (16) |
PDMA_T::REQSEL12_15: REQSRC14 Position
Definition at line 852 of file pdma_reg.h.
| #define PDMA_REQSEL12_15_REQSRC15_Msk (0x7ful << PDMA_REQSEL12_15_REQSRC15_Pos) |
PDMA_T::REQSEL12_15: REQSRC15 Mask
Definition at line 856 of file pdma_reg.h.
| #define PDMA_REQSEL12_15_REQSRC15_Pos (24) |
PDMA_T::REQSEL12_15: REQSRC15 Position
Definition at line 855 of file pdma_reg.h.
| #define PDMA_REQSEL4_7_REQSRC4_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC4_Pos) |
PDMA_T::REQSEL4_7: REQSRC4 Mask
Definition at line 823 of file pdma_reg.h.
| #define PDMA_REQSEL4_7_REQSRC4_Pos (0) |
PDMA_T::REQSEL4_7: REQSRC4 Position
Definition at line 822 of file pdma_reg.h.
| #define PDMA_REQSEL4_7_REQSRC5_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC5_Pos) |
PDMA_T::REQSEL4_7: REQSRC5 Mask
Definition at line 826 of file pdma_reg.h.
| #define PDMA_REQSEL4_7_REQSRC5_Pos (8) |
PDMA_T::REQSEL4_7: REQSRC5 Position
Definition at line 825 of file pdma_reg.h.
| #define PDMA_REQSEL4_7_REQSRC6_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC6_Pos) |
PDMA_T::REQSEL4_7: REQSRC6 Mask
Definition at line 829 of file pdma_reg.h.
| #define PDMA_REQSEL4_7_REQSRC6_Pos (16) |
PDMA_T::REQSEL4_7: REQSRC6 Position
Definition at line 828 of file pdma_reg.h.
| #define PDMA_REQSEL4_7_REQSRC7_Msk (0x7ful << PDMA_REQSEL4_7_REQSRC7_Pos) |
PDMA_T::REQSEL4_7: REQSRC7 Mask
Definition at line 832 of file pdma_reg.h.
| #define PDMA_REQSEL4_7_REQSRC7_Pos (24) |
PDMA_T::REQSEL4_7: REQSRC7 Position
Definition at line 831 of file pdma_reg.h.
| #define PDMA_REQSEL8_11_REQSRC10_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC10_Pos) |
PDMA_T::REQSEL8_11: REQSRC10 Mask
Definition at line 841 of file pdma_reg.h.
| #define PDMA_REQSEL8_11_REQSRC10_Pos (16) |
PDMA_T::REQSEL8_11: REQSRC10 Position
Definition at line 840 of file pdma_reg.h.
| #define PDMA_REQSEL8_11_REQSRC11_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC11_Pos) |
PDMA_T::REQSEL8_11: REQSRC11 Mask
Definition at line 844 of file pdma_reg.h.
| #define PDMA_REQSEL8_11_REQSRC11_Pos (24) |
PDMA_T::REQSEL8_11: REQSRC11 Position
Definition at line 843 of file pdma_reg.h.
| #define PDMA_REQSEL8_11_REQSRC8_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC8_Pos) |
PDMA_T::REQSEL8_11: REQSRC8 Mask
Definition at line 835 of file pdma_reg.h.
| #define PDMA_REQSEL8_11_REQSRC8_Pos (0) |
PDMA_T::REQSEL8_11: REQSRC8 Position
Definition at line 834 of file pdma_reg.h.
| #define PDMA_REQSEL8_11_REQSRC9_Msk (0x7ful << PDMA_REQSEL8_11_REQSRC9_Pos) |
PDMA_T::REQSEL8_11: REQSRC9 Mask
Definition at line 838 of file pdma_reg.h.
| #define PDMA_REQSEL8_11_REQSRC9_Pos (8) |
PDMA_T::REQSEL8_11: REQSRC9 Position
Definition at line 837 of file pdma_reg.h.
| #define PDMA_SCATBA_SCATBA_Msk (0xfffful << PDMA_SCATBA_SCATBA_Pos) |
PDMA_T::SCATBA: SCATBA Mask
Definition at line 799 of file pdma_reg.h.
| #define PDMA_SCATBA_SCATBA_Pos (16) |
PDMA_T::SCATBA: SCATBA Position
Definition at line 798 of file pdma_reg.h.
| #define PDMA_STCRn_STC_Msk (0xfffful << PDMA_STCRn_STC_Pos) |
PDMA_T::STCRn: STC Mask
Definition at line 859 of file pdma_reg.h.
| #define PDMA_STCRn_STC_Pos (0) |
PDMA_T::STCRn: STC Position
Definition at line 858 of file pdma_reg.h.
| #define PDMA_SWREQ_SWREQn_Msk (0xfffful << PDMA_SWREQ_SWREQn_Pos) |
PDMA_T::SWREQ: SWREQn Mask
Definition at line 655 of file pdma_reg.h.
| #define PDMA_SWREQ_SWREQn_Pos (0) |
PDMA_T::SWREQ: SWREQn Position
Definition at line 654 of file pdma_reg.h.
| #define PDMA_TACTSTS_TXACTFn_Msk (0xfffful << PDMA_TACTSTS_TXACTFn_Pos) |
PDMA_T::TACTSTS: TXACTFn Mask
Definition at line 784 of file pdma_reg.h.
| #define PDMA_TACTSTS_TXACTFn_Pos (0) |
PDMA_T::TACTSTS: TXACTFn Position
Definition at line 783 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF0_Msk (0x1ul << PDMA_TDSTS_TDIF0_Pos) |
PDMA_T::TDSTS: TDIF0 Mask
Definition at line 733 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF0_Pos (0) |
PDMA_T::TDSTS: TDIF0 Position
Definition at line 732 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF10_Msk (0x1ul << PDMA_TDSTS_TDIF10_Pos) |
PDMA_T::TDSTS: TDIF10 Mask
Definition at line 763 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF10_Pos (10) |
PDMA_T::TDSTS: TDIF10 Position
Definition at line 762 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF11_Msk (0x1ul << PDMA_TDSTS_TDIF11_Pos) |
PDMA_T::TDSTS: TDIF11 Mask
Definition at line 766 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF11_Pos (11) |
PDMA_T::TDSTS: TDIF11 Position
Definition at line 765 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF12_Msk (0x1ul << PDMA_TDSTS_TDIF12_Pos) |
PDMA_T::TDSTS: TDIF12 Mask
Definition at line 769 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF12_Pos (12) |
PDMA_T::TDSTS: TDIF12 Position
Definition at line 768 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF13_Msk (0x1ul << PDMA_TDSTS_TDIF13_Pos) |
PDMA_T::TDSTS: TDIF13 Mask
Definition at line 772 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF13_Pos (13) |
PDMA_T::TDSTS: TDIF13 Position
Definition at line 771 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF14_Msk (0x1ul << PDMA_TDSTS_TDIF14_Pos) |
PDMA_T::TDSTS: TDIF14 Mask
Definition at line 775 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF14_Pos (14) |
PDMA_T::TDSTS: TDIF14 Position
Definition at line 774 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF15_Msk (0x1ul << PDMA_TDSTS_TDIF15_Pos) |
PDMA_T::TDSTS: TDIF15 Mask
Definition at line 778 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF15_Pos (15) |
PDMA_T::TDSTS: TDIF15 Position
Definition at line 777 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF1_Msk (0x1ul << PDMA_TDSTS_TDIF1_Pos) |
PDMA_T::TDSTS: TDIF1 Mask
Definition at line 736 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF1_Pos (1) |
PDMA_T::TDSTS: TDIF1 Position
Definition at line 735 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF2_Msk (0x1ul << PDMA_TDSTS_TDIF2_Pos) |
PDMA_T::TDSTS: TDIF2 Mask
Definition at line 739 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF2_Pos (2) |
PDMA_T::TDSTS: TDIF2 Position
Definition at line 738 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF3_Msk (0x1ul << PDMA_TDSTS_TDIF3_Pos) |
PDMA_T::TDSTS: TDIF3 Mask
Definition at line 742 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF3_Pos (3) |
PDMA_T::TDSTS: TDIF3 Position
Definition at line 741 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF4_Msk (0x1ul << PDMA_TDSTS_TDIF4_Pos) |
PDMA_T::TDSTS: TDIF4 Mask
Definition at line 745 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF4_Pos (4) |
PDMA_T::TDSTS: TDIF4 Position
Definition at line 744 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF5_Msk (0x1ul << PDMA_TDSTS_TDIF5_Pos) |
PDMA_T::TDSTS: TDIF5 Mask
Definition at line 748 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF5_Pos (5) |
PDMA_T::TDSTS: TDIF5 Position
Definition at line 747 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF6_Msk (0x1ul << PDMA_TDSTS_TDIF6_Pos) |
PDMA_T::TDSTS: TDIF6 Mask
Definition at line 751 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF6_Pos (6) |
PDMA_T::TDSTS: TDIF6 Position
Definition at line 750 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF7_Msk (0x1ul << PDMA_TDSTS_TDIF7_Pos) |
PDMA_T::TDSTS: TDIF7 Mask
Definition at line 754 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF7_Pos (7) |
PDMA_T::TDSTS: TDIF7 Position
Definition at line 753 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF8_Msk (0x1ul << PDMA_TDSTS_TDIF8_Pos) |
PDMA_T::TDSTS: TDIF8 Mask
Definition at line 757 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF8_Pos (8) |
PDMA_T::TDSTS: TDIF8 Position
Definition at line 756 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF9_Msk (0x1ul << PDMA_TDSTS_TDIF9_Pos) |
PDMA_T::TDSTS: TDIF9 Mask
Definition at line 760 of file pdma_reg.h.
| #define PDMA_TDSTS_TDIF9_Pos (9) |
PDMA_T::TDSTS: TDIF9 Position
Definition at line 759 of file pdma_reg.h.
| #define PDMA_TOC0_1_TOC0_Msk (0xfffful << PDMA_TOC0_1_TOC0_Pos) |
PDMA_T::TOC0_1: TOC0 Mask
Definition at line 802 of file pdma_reg.h.
| #define PDMA_TOC0_1_TOC0_Pos (0) |
PDMA_T::TOC0_1: TOC0 Position
Definition at line 801 of file pdma_reg.h.
| #define PDMA_TOC0_1_TOC1_Msk (0xfffful << PDMA_TOC0_1_TOC1_Pos) |
PDMA_T::TOC0_1: TOC1 Mask
Definition at line 805 of file pdma_reg.h.
| #define PDMA_TOC0_1_TOC1_Pos (16) |
PDMA_T::TOC0_1: TOC1 Position
Definition at line 804 of file pdma_reg.h.
| #define PDMA_TOUTEN_TOUTENn_Msk (0x3ul << PDMA_TOUTEN_TOUTENn_Pos) |
PDMA_T::TOUTEN: TOUTENn Mask
Definition at line 793 of file pdma_reg.h.
| #define PDMA_TOUTEN_TOUTENn_Pos (0) |
PDMA_T::TOUTEN: TOUTENn Position
Definition at line 792 of file pdma_reg.h.
| #define PDMA_TOUTIEN_TOUTIENn_Msk (0x3ul << PDMA_TOUTIEN_TOUTIENn_Pos) |
PDMA_T::TOUTIEN: TOUTIENn Mask
Definition at line 796 of file pdma_reg.h.
| #define PDMA_TOUTIEN_TOUTIENn_Pos (0) |
PDMA_T::TOUTIEN: TOUTIENn Position
Definition at line 795 of file pdma_reg.h.
| #define PDMA_TOUTPSC_TOUTPSC0_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC0_Pos) |
PDMA_T::TOUTPSC: TOUTPSC0 Mask
Definition at line 787 of file pdma_reg.h.
| #define PDMA_TOUTPSC_TOUTPSC0_Pos (0) |
PDMA_T::TOUTPSC: TOUTPSC0 Position
Definition at line 786 of file pdma_reg.h.
| #define PDMA_TOUTPSC_TOUTPSC1_Msk (0x7ul << PDMA_TOUTPSC_TOUTPSC1_Pos) |
PDMA_T::TOUTPSC: TOUTPSC1 Mask
Definition at line 790 of file pdma_reg.h.
| #define PDMA_TOUTPSC_TOUTPSC1_Pos (4) |
PDMA_T::TOUTPSC: TOUTPSC1 Position
Definition at line 789 of file pdma_reg.h.
| #define PDMA_TRGSTS_REQSTSn_Msk (0xfffful << PDMA_TRGSTS_REQSTSn_Pos) |
PDMA_T::TRGSTS: REQSTSn Mask
Definition at line 658 of file pdma_reg.h.
| #define PDMA_TRGSTS_REQSTSn_Pos (0) |
PDMA_T::TRGSTS: REQSTSn Position
Definition at line 657 of file pdma_reg.h.
| #define QEI_CNT_CNT_Msk (0xfffffffful << QEI_CNT_CNT_Pos) |
QEI_T::CNT: CNT Mask
| #define QEI_CNT_CNT_Pos (0) |
@addtogroup QEI_CONST QEI Bit Field Definition Constant Definitions for QEI Controller
QEI_T::CNT: CNT Position
| #define QEI_CNTCMP_CNTCMP_Msk (0xfffffffful << QEI_CNTCMP_CNTCMP_Pos) |
QEI_T::CNTCMP: CNTCMP Mask
| #define QEI_CNTCMP_CNTCMP_Pos (0) |
QEI_T::CNTCMP: CNTCMP Position
| #define QEI_CNTHOLD_CNTHOLD_Msk (0xfffffffful << QEI_CNTHOLD_CNTHOLD_Pos) |
QEI_T::CNTHOLD: CNTHOLD Mask
| #define QEI_CNTHOLD_CNTHOLD_Pos (0) |
QEI_T::CNTHOLD: CNTHOLD Position
| #define QEI_CNTLATCH_CNTLATCH_Msk (0xfffffffful << QEI_CNTLATCH_CNTLATCH_Pos) |
QEI_T::CNTLATCH: CNTLATCH Mask
| #define QEI_CNTLATCH_CNTLATCH_Pos (0) |
QEI_T::CNTLATCH: CNTLATCH Position
| #define QEI_CNTMAX_CNTMAX_Msk (0xfffffffful << QEI_CNTMAX_CNTMAX_Pos) |
QEI_T::CNTMAX: CNTMAX Mask
| #define QEI_CNTMAX_CNTMAX_Pos (0) |
QEI_T::CNTMAX: CNTMAX Position
| #define QEI_CTL_CHAEN_Msk (0x1ul << QEI_CTL_CHAEN_Pos) |
QEI_T::CTL: CHAEN Mask
| #define QEI_CTL_CHAEN_Pos (4) |
QEI_T::CTL: CHAEN Position
| #define QEI_CTL_CHAINV_Msk (0x1ul << QEI_CTL_CHAINV_Pos) |
QEI_T::CTL: CHAINV Mask
| #define QEI_CTL_CHAINV_Pos (12) |
QEI_T::CTL: CHAINV Position
| #define QEI_CTL_CHBEN_Msk (0x1ul << QEI_CTL_CHBEN_Pos) |
QEI_T::CTL: CHBEN Mask
| #define QEI_CTL_CHBEN_Pos (5) |
QEI_T::CTL: CHBEN Position
| #define QEI_CTL_CHBINV_Msk (0x1ul << QEI_CTL_CHBINV_Pos) |
QEI_T::CTL: CHBINV Mask
| #define QEI_CTL_CHBINV_Pos (13) |
QEI_T::CTL: CHBINV Position
| #define QEI_CTL_CMPEN_Msk (0x1ul << QEI_CTL_CMPEN_Pos) |
QEI_T::CTL: CMPEN Mask
| #define QEI_CTL_CMPEN_Pos (28) |
QEI_T::CTL: CMPEN Position
| #define QEI_CTL_CMPIEN_Msk (0x1ul << QEI_CTL_CMPIEN_Pos) |
QEI_T::CTL: CMPIEN Mask
| #define QEI_CTL_CMPIEN_Pos (18) |
QEI_T::CTL: CMPIEN Position
| #define QEI_CTL_DIRIEN_Msk (0x1ul << QEI_CTL_DIRIEN_Pos) |
QEI_T::CTL: DIRIEN Mask
| #define QEI_CTL_DIRIEN_Pos (17) |
QEI_T::CTL: DIRIEN Position
| #define QEI_CTL_HOLDCNT_Msk (0x1ul << QEI_CTL_HOLDCNT_Pos) |
QEI_T::CTL: HOLDCNT Mask
| #define QEI_CTL_HOLDCNT_Pos (24) |
QEI_T::CTL: HOLDCNT Position
| #define QEI_CTL_HOLDTMR0_Msk (0x1ul << QEI_CTL_HOLDTMR0_Pos) |
QEI_T::CTL: HOLDTMR0 Mask
| #define QEI_CTL_HOLDTMR0_Pos (20) |
QEI_T::CTL: HOLDTMR0 Position
| #define QEI_CTL_HOLDTMR1_Msk (0x1ul << QEI_CTL_HOLDTMR1_Pos) |
QEI_T::CTL: HOLDTMR1 Mask
| #define QEI_CTL_HOLDTMR1_Pos (21) |
QEI_T::CTL: HOLDTMR1 Position
| #define QEI_CTL_HOLDTMR2_Msk (0x1ul << QEI_CTL_HOLDTMR2_Pos) |
QEI_T::CTL: HOLDTMR2 Mask
| #define QEI_CTL_HOLDTMR2_Pos (22) |
QEI_T::CTL: HOLDTMR2 Position
| #define QEI_CTL_HOLDTMR3_Msk (0x1ul << QEI_CTL_HOLDTMR3_Pos) |
QEI_T::CTL: HOLDTMR3 Mask
| #define QEI_CTL_HOLDTMR3_Pos (23) |
QEI_T::CTL: HOLDTMR3 Position
| #define QEI_CTL_IDXEN_Msk (0x1ul << QEI_CTL_IDXEN_Pos) |
QEI_T::CTL: IDXEN Mask
| #define QEI_CTL_IDXEN_Pos (6) |
QEI_T::CTL: IDXEN Position
| #define QEI_CTL_IDXIEN_Msk (0x1ul << QEI_CTL_IDXIEN_Pos) |
QEI_T::CTL: IDXIEN Mask
| #define QEI_CTL_IDXIEN_Pos (19) |
QEI_T::CTL: IDXIEN Position
| #define QEI_CTL_IDXINV_Msk (0x1ul << QEI_CTL_IDXINV_Pos) |
QEI_T::CTL: IDXINV Mask
| #define QEI_CTL_IDXINV_Pos (14) |
QEI_T::CTL: IDXINV Position
| #define QEI_CTL_IDXLATEN_Msk (0x1ul << QEI_CTL_IDXLATEN_Pos) |
QEI_T::CTL: IDXLATEN Mask
| #define QEI_CTL_IDXLATEN_Pos (25) |
QEI_T::CTL: IDXLATEN Position
| #define QEI_CTL_IDXRLDEN_Msk (0x1ul << QEI_CTL_IDXRLDEN_Pos) |
QEI_T::CTL: IDXRLDEN Mask
| #define QEI_CTL_IDXRLDEN_Pos (27) |
QEI_T::CTL: IDXRLDEN Position
| #define QEI_CTL_MODE_Msk (0x3ul << QEI_CTL_MODE_Pos) |
QEI_T::CTL: MODE Mask
| #define QEI_CTL_MODE_Pos (8) |
QEI_T::CTL: MODE Position
| #define QEI_CTL_NFCLKSEL_Msk (0x7ul << QEI_CTL_NFCLKSEL_Pos) |
QEI_T::CTL: NFCLKSEL Mask
| #define QEI_CTL_NFCLKSEL_Pos (0) |
QEI_T::CTL: NFCLKSEL Position
| #define QEI_CTL_NFDIS_Msk (0x1ul << QEI_CTL_NFDIS_Pos) |
QEI_T::CTL: NFDIS Mask
| #define QEI_CTL_NFDIS_Pos (3) |
QEI_T::CTL: NFDIS Position
| #define QEI_CTL_OVUNIEN_Msk (0x1ul << QEI_CTL_OVUNIEN_Pos) |
QEI_T::CTL: OVUNIEN Mask
| #define QEI_CTL_OVUNIEN_Pos (16) |
QEI_T::CTL: OVUNIEN Position
| #define QEI_CTL_QEIEN_Msk (0x1ul << QEI_CTL_QEIEN_Pos) |
QEI_T::CTL: QEIEN Mask
| #define QEI_CTL_QEIEN_Pos (29) |
QEI_T::CTL: QEIEN Position
| #define QEI_STATUS_CMPF_Msk (0x1ul << QEI_STATUS_CMPF_Pos) |
QEI_T::STATUS: CMPF Mask
| #define QEI_STATUS_CMPF_Pos (1) |
QEI_T::STATUS: CMPF Position
| #define QEI_STATUS_DIRCHGF_Msk (0x1ul << QEI_STATUS_DIRCHGF_Pos) |
QEI_T::STATUS: DIRCHGF Mask
| #define QEI_STATUS_DIRCHGF_Pos (3) |
QEI_T::STATUS: DIRCHGF Position
| #define QEI_STATUS_DIRF_Msk (0x1ul << QEI_STATUS_DIRF_Pos) |
QEI_T::STATUS: DIRF Mask
| #define QEI_STATUS_DIRF_Pos (8) |
QEI_T::STATUS: DIRF Position
| #define QEI_STATUS_IDXF_Msk (0x1ul << QEI_STATUS_IDXF_Pos) |
QEI_T::STATUS: IDXF Mask
| #define QEI_STATUS_IDXF_Pos (0) |
QEI_T::STATUS: IDXF Position
| #define QEI_STATUS_OVUNF_Msk (0x1ul << QEI_STATUS_OVUNF_Pos) |
QEI_T::STATUS: OVUNF Mask
| #define QEI_STATUS_OVUNF_Pos (2) |
QEI_T::STATUS: OVUNF Position
| #define QSPI_CLKDIV_DIVIDER_Msk (0x1fful << QSPI_CLKDIV_DIVIDER_Pos) |
QSPI_T::CLKDIV: DIVIDER Mask
Definition at line 434 of file qspi_reg.h.
| #define QSPI_CLKDIV_DIVIDER_Pos (0) |
QSPI_T::CLKDIV: DIVIDER Position
Definition at line 433 of file qspi_reg.h.
| #define QSPI_CTL_CLKPOL_Msk (0x1ul << QSPI_CTL_CLKPOL_Pos) |
QSPI_T::CTL: CLKPOL Mask
Definition at line 395 of file qspi_reg.h.
| #define QSPI_CTL_CLKPOL_Pos (3) |
QSPI_T::CTL: CLKPOL Position
Definition at line 394 of file qspi_reg.h.
| #define QSPI_CTL_DATDIR_Msk (0x1ul << QSPI_CTL_DATDIR_Pos) |
QSPI_T::CTL: DATDIR Mask
Definition at line 425 of file qspi_reg.h.
| #define QSPI_CTL_DATDIR_Pos (20) |
QSPI_T::CTL: DATDIR Position
Definition at line 424 of file qspi_reg.h.
| #define QSPI_CTL_DUALIOEN_Msk (0x1ul << QSPI_CTL_DUALIOEN_Pos) |
QSPI_T::CTL: DUALIOEN Mask
Definition at line 428 of file qspi_reg.h.
| #define QSPI_CTL_DUALIOEN_Pos (21) |
QSPI_T::CTL: DUALIOEN Position
Definition at line 427 of file qspi_reg.h.
| #define QSPI_CTL_DWIDTH_Msk (0x1ful << QSPI_CTL_DWIDTH_Pos) |
QSPI_T::CTL: DWIDTH Mask
Definition at line 401 of file qspi_reg.h.
| #define QSPI_CTL_DWIDTH_Pos (8) |
QSPI_T::CTL: DWIDTH Position
Definition at line 400 of file qspi_reg.h.
| #define QSPI_CTL_HALFDPX_Msk (0x1ul << QSPI_CTL_HALFDPX_Pos) |
QSPI_T::CTL: HALFDPX Mask
Definition at line 407 of file qspi_reg.h.
| #define QSPI_CTL_HALFDPX_Pos (14) |
QSPI_T::CTL: HALFDPX Position
Definition at line 406 of file qspi_reg.h.
| #define QSPI_CTL_LSB_Msk (0x1ul << QSPI_CTL_LSB_Pos) |
QSPI_T::CTL: LSB Mask
Definition at line 404 of file qspi_reg.h.
| #define QSPI_CTL_LSB_Pos (13) |
QSPI_T::CTL: LSB Position
Definition at line 403 of file qspi_reg.h.
| #define QSPI_CTL_QSPIEN_Msk (0x1ul << QSPI_CTL_QSPIEN_Pos) |
QSPI_T::CTL: QSPIEN Mask
Definition at line 386 of file qspi_reg.h.
| #define QSPI_CTL_QSPIEN_Pos (0) |
@addtogroup QSPI_CONST QSPI Bit Field Definition Constant Definitions for QSPI Controller
QSPI_T::CTL: QSPIEN Position
Definition at line 385 of file qspi_reg.h.
| #define QSPI_CTL_QUADIOEN_Msk (0x1ul << QSPI_CTL_QUADIOEN_Pos) |
QSPI_T::CTL: QUADIOEN Mask
Definition at line 431 of file qspi_reg.h.
| #define QSPI_CTL_QUADIOEN_Pos (22) |
QSPI_T::CTL: QUADIOEN Position
Definition at line 430 of file qspi_reg.h.
| #define QSPI_CTL_REORDER_Msk (0x1ul << QSPI_CTL_REORDER_Pos) |
QSPI_T::CTL: REORDER Mask
Definition at line 422 of file qspi_reg.h.
| #define QSPI_CTL_REORDER_Pos (19) |
QSPI_T::CTL: REORDER Position
Definition at line 421 of file qspi_reg.h.
| #define QSPI_CTL_RXNEG_Msk (0x1ul << QSPI_CTL_RXNEG_Pos) |
QSPI_T::CTL: RXNEG Mask
Definition at line 389 of file qspi_reg.h.
| #define QSPI_CTL_RXNEG_Pos (1) |
QSPI_T::CTL: RXNEG Position
Definition at line 388 of file qspi_reg.h.
| #define QSPI_CTL_RXONLY_Msk (0x1ul << QSPI_CTL_RXONLY_Pos) |
QSPI_T::CTL: RXONLY Mask
Definition at line 410 of file qspi_reg.h.
| #define QSPI_CTL_RXONLY_Pos (15) |
QSPI_T::CTL: RXONLY Position
Definition at line 409 of file qspi_reg.h.
| #define QSPI_CTL_SLAVE_Msk (0x1ul << QSPI_CTL_SLAVE_Pos) |
QSPI_T::CTL: SLAVE Mask
Definition at line 419 of file qspi_reg.h.
| #define QSPI_CTL_SLAVE_Pos (18) |
QSPI_T::CTL: SLAVE Position
Definition at line 418 of file qspi_reg.h.
| #define QSPI_CTL_SUSPITV_Msk (0xful << QSPI_CTL_SUSPITV_Pos) |
QSPI_T::CTL: SUSPITV Mask
Definition at line 398 of file qspi_reg.h.
| #define QSPI_CTL_SUSPITV_Pos (4) |
QSPI_T::CTL: SUSPITV Position
Definition at line 397 of file qspi_reg.h.
| #define QSPI_CTL_TWOBIT_Msk (0x1ul << QSPI_CTL_TWOBIT_Pos) |
QSPI_T::CTL: TWOBIT Mask
Definition at line 413 of file qspi_reg.h.
| #define QSPI_CTL_TWOBIT_Pos (16) |
QSPI_T::CTL: TWOBIT Position
Definition at line 412 of file qspi_reg.h.
| #define QSPI_CTL_TXNEG_Msk (0x1ul << QSPI_CTL_TXNEG_Pos) |
QSPI_T::CTL: TXNEG Mask
Definition at line 392 of file qspi_reg.h.
| #define QSPI_CTL_TXNEG_Pos (2) |
QSPI_T::CTL: TXNEG Position
Definition at line 391 of file qspi_reg.h.
| #define QSPI_CTL_UNITIEN_Msk (0x1ul << QSPI_CTL_UNITIEN_Pos) |
QSPI_T::CTL: UNITIEN Mask
Definition at line 416 of file qspi_reg.h.
| #define QSPI_CTL_UNITIEN_Pos (17) |
QSPI_T::CTL: UNITIEN Position
Definition at line 415 of file qspi_reg.h.
| #define QSPI_FIFOCTL_RXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_RXFBCLR_Pos) |
QSPI_T::FIFOCTL: RXFBCLR Mask
Definition at line 503 of file qspi_reg.h.
| #define QSPI_FIFOCTL_RXFBCLR_Pos (8) |
QSPI_T::FIFOCTL: RXFBCLR Position
Definition at line 502 of file qspi_reg.h.
| #define QSPI_FIFOCTL_RXOVIEN_Msk (0x1ul << QSPI_FIFOCTL_RXOVIEN_Pos) |
QSPI_T::FIFOCTL: RXOVIEN Mask
Definition at line 494 of file qspi_reg.h.
| #define QSPI_FIFOCTL_RXOVIEN_Pos (5) |
QSPI_T::FIFOCTL: RXOVIEN Position
Definition at line 493 of file qspi_reg.h.
| #define QSPI_FIFOCTL_RXRST_Msk (0x1ul << QSPI_FIFOCTL_RXRST_Pos) |
QSPI_T::FIFOCTL: RXRST Mask
Definition at line 479 of file qspi_reg.h.
| #define QSPI_FIFOCTL_RXRST_Pos (0) |
QSPI_T::FIFOCTL: RXRST Position
Definition at line 478 of file qspi_reg.h.
| #define QSPI_FIFOCTL_RXTH_Msk (0x7ul << QSPI_FIFOCTL_RXTH_Pos) |
QSPI_T::FIFOCTL: RXTH Mask
Definition at line 509 of file qspi_reg.h.
| #define QSPI_FIFOCTL_RXTH_Pos (24) |
QSPI_T::FIFOCTL: RXTH Position
Definition at line 508 of file qspi_reg.h.
| #define QSPI_FIFOCTL_RXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTHIEN_Pos) |
QSPI_T::FIFOCTL: RXTHIEN Mask
Definition at line 485 of file qspi_reg.h.
| #define QSPI_FIFOCTL_RXTHIEN_Pos (2) |
QSPI_T::FIFOCTL: RXTHIEN Position
Definition at line 484 of file qspi_reg.h.
| #define QSPI_FIFOCTL_RXTOIEN_Msk (0x1ul << QSPI_FIFOCTL_RXTOIEN_Pos) |
QSPI_T::FIFOCTL: RXTOIEN Mask
Definition at line 491 of file qspi_reg.h.
| #define QSPI_FIFOCTL_RXTOIEN_Pos (4) |
QSPI_T::FIFOCTL: RXTOIEN Position
Definition at line 490 of file qspi_reg.h.
| #define QSPI_FIFOCTL_TXFBCLR_Msk (0x1ul << QSPI_FIFOCTL_TXFBCLR_Pos) |
QSPI_T::FIFOCTL: TXFBCLR Mask
Definition at line 506 of file qspi_reg.h.
| #define QSPI_FIFOCTL_TXFBCLR_Pos (9) |
QSPI_T::FIFOCTL: TXFBCLR Position
Definition at line 505 of file qspi_reg.h.
| #define QSPI_FIFOCTL_TXRST_Msk (0x1ul << QSPI_FIFOCTL_TXRST_Pos) |
QSPI_T::FIFOCTL: TXRST Mask
Definition at line 482 of file qspi_reg.h.
| #define QSPI_FIFOCTL_TXRST_Pos (1) |
QSPI_T::FIFOCTL: TXRST Position
Definition at line 481 of file qspi_reg.h.
| #define QSPI_FIFOCTL_TXTH_Msk (0x7ul << QSPI_FIFOCTL_TXTH_Pos) |
QSPI_T::FIFOCTL: TXTH Mask
Definition at line 512 of file qspi_reg.h.
| #define QSPI_FIFOCTL_TXTH_Pos (28) |
QSPI_T::FIFOCTL: TXTH Position
Definition at line 511 of file qspi_reg.h.
| #define QSPI_FIFOCTL_TXTHIEN_Msk (0x1ul << QSPI_FIFOCTL_TXTHIEN_Pos) |
QSPI_T::FIFOCTL: TXTHIEN Mask
Definition at line 488 of file qspi_reg.h.
| #define QSPI_FIFOCTL_TXTHIEN_Pos (3) |
QSPI_T::FIFOCTL: TXTHIEN Position
Definition at line 487 of file qspi_reg.h.
| #define QSPI_FIFOCTL_TXUFIEN_Msk (0x1ul << QSPI_FIFOCTL_TXUFIEN_Pos) |
QSPI_T::FIFOCTL: TXUFIEN Mask
Definition at line 500 of file qspi_reg.h.
| #define QSPI_FIFOCTL_TXUFIEN_Pos (7) |
QSPI_T::FIFOCTL: TXUFIEN Position
Definition at line 499 of file qspi_reg.h.
| #define QSPI_FIFOCTL_TXUFPOL_Msk (0x1ul << QSPI_FIFOCTL_TXUFPOL_Pos) |
QSPI_T::FIFOCTL: TXUFPOL Mask
Definition at line 497 of file qspi_reg.h.
| #define QSPI_FIFOCTL_TXUFPOL_Pos (6) |
QSPI_T::FIFOCTL: TXUFPOL Position
Definition at line 496 of file qspi_reg.h.
| #define QSPI_PDMACTL_PDMARST_Msk (0x1ul << QSPI_PDMACTL_PDMARST_Pos) |
QSPI_T::PDMACTL: PDMARST Mask
Definition at line 476 of file qspi_reg.h.
| #define QSPI_PDMACTL_PDMARST_Pos (2) |
QSPI_T::PDMACTL: PDMARST Position
Definition at line 475 of file qspi_reg.h.
| #define QSPI_PDMACTL_RXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_RXPDMAEN_Pos) |
QSPI_T::PDMACTL: RXPDMAEN Mask
Definition at line 473 of file qspi_reg.h.
| #define QSPI_PDMACTL_RXPDMAEN_Pos (1) |
QSPI_T::PDMACTL: RXPDMAEN Position
Definition at line 472 of file qspi_reg.h.
| #define QSPI_PDMACTL_TXPDMAEN_Msk (0x1ul << QSPI_PDMACTL_TXPDMAEN_Pos) |
QSPI_T::PDMACTL: TXPDMAEN Mask
Definition at line 470 of file qspi_reg.h.
| #define QSPI_PDMACTL_TXPDMAEN_Pos (0) |
QSPI_T::PDMACTL: TXPDMAEN Position
Definition at line 469 of file qspi_reg.h.
| #define QSPI_RX_RX_Msk (0xfffffffful << QSPI_RX_RX_Pos) |
QSPI_T::RX: RX Mask
Definition at line 581 of file qspi_reg.h.
| #define QSPI_RX_RX_Pos (0) |
QSPI_T::RX: RX Position
Definition at line 580 of file qspi_reg.h.
| #define QSPI_SSCTL_AUTOSS_Msk (0x1ul << QSPI_SSCTL_AUTOSS_Pos) |
QSPI_T::SSCTL: AUTOSS Mask
Definition at line 443 of file qspi_reg.h.
| #define QSPI_SSCTL_AUTOSS_Pos (3) |
QSPI_T::SSCTL: AUTOSS Position
Definition at line 442 of file qspi_reg.h.
| #define QSPI_SSCTL_SLV3WIRE_Msk (0x1ul << QSPI_SSCTL_SLV3WIRE_Pos) |
QSPI_T::SSCTL: SLV3WIRE Mask
Definition at line 446 of file qspi_reg.h.
| #define QSPI_SSCTL_SLV3WIRE_Pos (4) |
QSPI_T::SSCTL: SLV3WIRE Position
Definition at line 445 of file qspi_reg.h.
| #define QSPI_SSCTL_SLVBEIEN_Msk (0x1ul << QSPI_SSCTL_SLVBEIEN_Pos) |
QSPI_T::SSCTL: SLVBEIEN Mask
Definition at line 455 of file qspi_reg.h.
| #define QSPI_SSCTL_SLVBEIEN_Pos (8) |
QSPI_T::SSCTL: SLVBEIEN Position
Definition at line 454 of file qspi_reg.h.
| #define QSPI_SSCTL_SLVTOCNT_Msk (0xfffful << QSPI_SSCTL_SLVTOCNT_Pos) |
QSPI_T::SSCTL: SLVTOCNT Mask
Definition at line 467 of file qspi_reg.h.
| #define QSPI_SSCTL_SLVTOCNT_Pos (16) |
QSPI_T::SSCTL: SLVTOCNT Position
Definition at line 466 of file qspi_reg.h.
| #define QSPI_SSCTL_SLVTOIEN_Msk (0x1ul << QSPI_SSCTL_SLVTOIEN_Pos) |
QSPI_T::SSCTL: SLVTOIEN Mask
Definition at line 449 of file qspi_reg.h.
| #define QSPI_SSCTL_SLVTOIEN_Pos (5) |
QSPI_T::SSCTL: SLVTOIEN Position
Definition at line 448 of file qspi_reg.h.
| #define QSPI_SSCTL_SLVTORST_Msk (0x1ul << QSPI_SSCTL_SLVTORST_Pos) |
QSPI_T::SSCTL: SLVTORST Mask
Definition at line 452 of file qspi_reg.h.
| #define QSPI_SSCTL_SLVTORST_Pos (6) |
QSPI_T::SSCTL: SLVTORST Position
Definition at line 451 of file qspi_reg.h.
| #define QSPI_SSCTL_SLVURIEN_Msk (0x1ul << QSPI_SSCTL_SLVURIEN_Pos) |
QSPI_T::SSCTL: SLVURIEN Mask
Definition at line 458 of file qspi_reg.h.
| #define QSPI_SSCTL_SLVURIEN_Pos (9) |
QSPI_T::SSCTL: SLVURIEN Position
Definition at line 457 of file qspi_reg.h.
| #define QSPI_SSCTL_SS_Msk (0x1ul << QSPI_SSCTL_SS_Pos) |
QSPI_T::SSCTL: SS Mask
Definition at line 437 of file qspi_reg.h.
| #define QSPI_SSCTL_SS_Pos (0) |
QSPI_T::SSCTL: SS Position
Definition at line 436 of file qspi_reg.h.
| #define QSPI_SSCTL_SSACTIEN_Msk (0x1ul << QSPI_SSCTL_SSACTIEN_Pos) |
QSPI_T::SSCTL: SSACTIEN Mask
Definition at line 461 of file qspi_reg.h.
| #define QSPI_SSCTL_SSACTIEN_Pos (12) |
QSPI_T::SSCTL: SSACTIEN Position
Definition at line 460 of file qspi_reg.h.
| #define QSPI_SSCTL_SSACTPOL_Msk (0x1ul << QSPI_SSCTL_SSACTPOL_Pos) |
QSPI_T::SSCTL: SSACTPOL Mask
Definition at line 440 of file qspi_reg.h.
| #define QSPI_SSCTL_SSACTPOL_Pos (2) |
QSPI_T::SSCTL: SSACTPOL Position
Definition at line 439 of file qspi_reg.h.
| #define QSPI_SSCTL_SSINAIEN_Msk (0x1ul << QSPI_SSCTL_SSINAIEN_Pos) |
QSPI_T::SSCTL: SSINAIEN Mask
Definition at line 464 of file qspi_reg.h.
| #define QSPI_SSCTL_SSINAIEN_Pos (13) |
QSPI_T::SSCTL: SSINAIEN Position
Definition at line 463 of file qspi_reg.h.
| #define QSPI_STATUS_BUSY_Msk (0x1ul << QSPI_STATUS_BUSY_Pos) |
QSPI_T::STATUS: BUSY Mask
Definition at line 515 of file qspi_reg.h.
| #define QSPI_STATUS_BUSY_Pos (0) |
QSPI_T::STATUS: BUSY Position
Definition at line 514 of file qspi_reg.h.
| #define QSPI_STATUS_QSPIENSTS_Msk (0x1ul << QSPI_STATUS_QSPIENSTS_Pos) |
QSPI_T::STATUS: QSPIENSTS Mask
Definition at line 554 of file qspi_reg.h.
| #define QSPI_STATUS_QSPIENSTS_Pos (15) |
QSPI_T::STATUS: QSPIENSTS Position
Definition at line 553 of file qspi_reg.h.
| #define QSPI_STATUS_RXCNT_Msk (0xful << QSPI_STATUS_RXCNT_Pos) |
QSPI_T::STATUS: RXCNT Mask
Definition at line 572 of file qspi_reg.h.
| #define QSPI_STATUS_RXCNT_Pos (24) |
QSPI_T::STATUS: RXCNT Position
Definition at line 571 of file qspi_reg.h.
| #define QSPI_STATUS_RXEMPTY_Msk (0x1ul << QSPI_STATUS_RXEMPTY_Pos) |
QSPI_T::STATUS: RXEMPTY Mask
Definition at line 539 of file qspi_reg.h.
| #define QSPI_STATUS_RXEMPTY_Pos (8) |
QSPI_T::STATUS: RXEMPTY Position
Definition at line 538 of file qspi_reg.h.
| #define QSPI_STATUS_RXFULL_Msk (0x1ul << QSPI_STATUS_RXFULL_Pos) |
QSPI_T::STATUS: RXFULL Mask
Definition at line 542 of file qspi_reg.h.
| #define QSPI_STATUS_RXFULL_Pos (9) |
QSPI_T::STATUS: RXFULL Position
Definition at line 541 of file qspi_reg.h.
| #define QSPI_STATUS_RXOVIF_Msk (0x1ul << QSPI_STATUS_RXOVIF_Pos) |
QSPI_T::STATUS: RXOVIF Mask
Definition at line 548 of file qspi_reg.h.
| #define QSPI_STATUS_RXOVIF_Pos (11) |
QSPI_T::STATUS: RXOVIF Position
Definition at line 547 of file qspi_reg.h.
| #define QSPI_STATUS_RXTHIF_Msk (0x1ul << QSPI_STATUS_RXTHIF_Pos) |
QSPI_T::STATUS: RXTHIF Mask
Definition at line 545 of file qspi_reg.h.
| #define QSPI_STATUS_RXTHIF_Pos (10) |
QSPI_T::STATUS: RXTHIF Position
Definition at line 544 of file qspi_reg.h.
| #define QSPI_STATUS_RXTOIF_Msk (0x1ul << QSPI_STATUS_RXTOIF_Pos) |
QSPI_T::STATUS: RXTOIF Mask
Definition at line 551 of file qspi_reg.h.
| #define QSPI_STATUS_RXTOIF_Pos (12) |
QSPI_T::STATUS: RXTOIF Position
Definition at line 550 of file qspi_reg.h.
| #define QSPI_STATUS_SLVBEIF_Msk (0x1ul << QSPI_STATUS_SLVBEIF_Pos) |
QSPI_T::STATUS: SLVBEIF Mask
Definition at line 533 of file qspi_reg.h.
| #define QSPI_STATUS_SLVBEIF_Pos (6) |
QSPI_T::STATUS: SLVBEIF Position
Definition at line 532 of file qspi_reg.h.
| #define QSPI_STATUS_SLVTOIF_Msk (0x1ul << QSPI_STATUS_SLVTOIF_Pos) |
QSPI_T::STATUS: SLVTOIF Mask
Definition at line 530 of file qspi_reg.h.
| #define QSPI_STATUS_SLVTOIF_Pos (5) |
QSPI_T::STATUS: SLVTOIF Position
Definition at line 529 of file qspi_reg.h.
| #define QSPI_STATUS_SLVURIF_Msk (0x1ul << QSPI_STATUS_SLVURIF_Pos) |
QSPI_T::STATUS: SLVURIF Mask
Definition at line 536 of file qspi_reg.h.
| #define QSPI_STATUS_SLVURIF_Pos (7) |
QSPI_T::STATUS: SLVURIF Position
Definition at line 535 of file qspi_reg.h.
| #define QSPI_STATUS_SSACTIF_Msk (0x1ul << QSPI_STATUS_SSACTIF_Pos) |
QSPI_T::STATUS: SSACTIF Mask
Definition at line 521 of file qspi_reg.h.
| #define QSPI_STATUS_SSACTIF_Pos (2) |
QSPI_T::STATUS: SSACTIF Position
Definition at line 520 of file qspi_reg.h.
| #define QSPI_STATUS_SSINAIF_Msk (0x1ul << QSPI_STATUS_SSINAIF_Pos) |
QSPI_T::STATUS: SSINAIF Mask
Definition at line 524 of file qspi_reg.h.
| #define QSPI_STATUS_SSINAIF_Pos (3) |
QSPI_T::STATUS: SSINAIF Position
Definition at line 523 of file qspi_reg.h.
| #define QSPI_STATUS_SSLINE_Msk (0x1ul << QSPI_STATUS_SSLINE_Pos) |
QSPI_T::STATUS: SSLINE Mask
Definition at line 527 of file qspi_reg.h.
| #define QSPI_STATUS_SSLINE_Pos (4) |
QSPI_T::STATUS: SSLINE Position
Definition at line 526 of file qspi_reg.h.
| #define QSPI_STATUS_TXCNT_Msk (0xful << QSPI_STATUS_TXCNT_Pos) |
QSPI_T::STATUS: TXCNT Mask
Definition at line 575 of file qspi_reg.h.
| #define QSPI_STATUS_TXCNT_Pos (28) |
QSPI_T::STATUS: TXCNT Position
Definition at line 574 of file qspi_reg.h.
| #define QSPI_STATUS_TXEMPTY_Msk (0x1ul << QSPI_STATUS_TXEMPTY_Pos) |
QSPI_T::STATUS: TXEMPTY Mask
Definition at line 557 of file qspi_reg.h.
| #define QSPI_STATUS_TXEMPTY_Pos (16) |
QSPI_T::STATUS: TXEMPTY Position
Definition at line 556 of file qspi_reg.h.
| #define QSPI_STATUS_TXFULL_Msk (0x1ul << QSPI_STATUS_TXFULL_Pos) |
QSPI_T::STATUS: TXFULL Mask
Definition at line 560 of file qspi_reg.h.
| #define QSPI_STATUS_TXFULL_Pos (17) |
QSPI_T::STATUS: TXFULL Position
Definition at line 559 of file qspi_reg.h.
| #define QSPI_STATUS_TXRXRST_Msk (0x1ul << QSPI_STATUS_TXRXRST_Pos) |
QSPI_T::STATUS: TXRXRST Mask
Definition at line 569 of file qspi_reg.h.
| #define QSPI_STATUS_TXRXRST_Pos (23) |
QSPI_T::STATUS: TXRXRST Position
Definition at line 568 of file qspi_reg.h.
| #define QSPI_STATUS_TXTHIF_Msk (0x1ul << QSPI_STATUS_TXTHIF_Pos) |
QSPI_T::STATUS: TXTHIF Mask
Definition at line 563 of file qspi_reg.h.
| #define QSPI_STATUS_TXTHIF_Pos (18) |
QSPI_T::STATUS: TXTHIF Position
Definition at line 562 of file qspi_reg.h.
| #define QSPI_STATUS_TXUFIF_Msk (0x1ul << QSPI_STATUS_TXUFIF_Pos) |
QSPI_T::STATUS: TXUFIF Mask
Definition at line 566 of file qspi_reg.h.
| #define QSPI_STATUS_TXUFIF_Pos (19) |
QSPI_T::STATUS: TXUFIF Position
Definition at line 565 of file qspi_reg.h.
| #define QSPI_STATUS_UNITIF_Msk (0x1ul << QSPI_STATUS_UNITIF_Pos) |
QSPI_T::STATUS: UNITIF Mask
Definition at line 518 of file qspi_reg.h.
| #define QSPI_STATUS_UNITIF_Pos (1) |
QSPI_T::STATUS: UNITIF Position
Definition at line 517 of file qspi_reg.h.
| #define QSPI_TX_TX_Msk (0xfffffffful << QSPI_TX_TX_Pos) |
QSPI_T::TX: TX Mask
Definition at line 578 of file qspi_reg.h.
| #define QSPI_TX_TX_Pos (0) |
QSPI_T::TX: TX Position
Definition at line 577 of file qspi_reg.h.
| #define RTC_CAL_DAY_Msk (0xful << RTC_CAL_DAY_Pos) |
RTC_T::CAL: DAY Mask
| #define RTC_CAL_DAY_Pos (0) |
RTC_T::CAL: DAY Position
| #define RTC_CAL_MON_Msk (0xful << RTC_CAL_MON_Pos) |
RTC_T::CAL: MON Mask
| #define RTC_CAL_MON_Pos (8) |
RTC_T::CAL: MON Position
| #define RTC_CAL_TENDAY_Msk (0x3ul << RTC_CAL_TENDAY_Pos) |
RTC_T::CAL: TENDAY Mask
| #define RTC_CAL_TENDAY_Pos (4) |
RTC_T::CAL: TENDAY Position
| #define RTC_CAL_TENMON_Msk (0x1ul << RTC_CAL_TENMON_Pos) |
RTC_T::CAL: TENMON Mask
| #define RTC_CAL_TENMON_Pos (12) |
RTC_T::CAL: TENMON Position
| #define RTC_CAL_TENYEAR_Msk (0xful << RTC_CAL_TENYEAR_Pos) |
RTC_T::CAL: TENYEAR Mask
| #define RTC_CAL_TENYEAR_Pos (20) |
RTC_T::CAL: TENYEAR Position
| #define RTC_CAL_YEAR_Msk (0xful << RTC_CAL_YEAR_Pos) |
RTC_T::CAL: YEAR Mask
| #define RTC_CAL_YEAR_Pos (16) |
RTC_T::CAL: YEAR Position
| #define RTC_CALM_DAY_Msk (0xful << RTC_CALM_DAY_Pos) |
RTC_T::CALM: DAY Mask
| #define RTC_CALM_DAY_Pos (0) |
RTC_T::CALM: DAY Position
| #define RTC_CALM_MON_Msk (0xful << RTC_CALM_MON_Pos) |
RTC_T::CALM: MON Mask
| #define RTC_CALM_MON_Pos (8) |
RTC_T::CALM: MON Position
| #define RTC_CALM_TENDAY_Msk (0x3ul << RTC_CALM_TENDAY_Pos) |
RTC_T::CALM: TENDAY Mask
| #define RTC_CALM_TENDAY_Pos (4) |
RTC_T::CALM: TENDAY Position
| #define RTC_CALM_TENMON_Msk (0x1ul << RTC_CALM_TENMON_Pos) |
RTC_T::CALM: TENMON Mask
| #define RTC_CALM_TENMON_Pos (12) |
RTC_T::CALM: TENMON Position
| #define RTC_CALM_TENYEAR_Msk (0xful << RTC_CALM_TENYEAR_Pos) |
RTC_T::CALM: TENYEAR Mask
| #define RTC_CALM_TENYEAR_Pos (20) |
RTC_T::CALM: TENYEAR Position
| #define RTC_CALM_YEAR_Msk (0xful << RTC_CALM_YEAR_Pos) |
RTC_T::CALM: YEAR Mask
| #define RTC_CALM_YEAR_Pos (16) |
RTC_T::CALM: YEAR Position
| #define RTC_CAMSK_MDAY_Msk (0x1ul << RTC_CAMSK_MDAY_Pos) |
RTC_T::CAMSK: MDAY Mask
| #define RTC_CAMSK_MDAY_Pos (0) |
RTC_T::CAMSK: MDAY Position
| #define RTC_CAMSK_MMON_Msk (0x1ul << RTC_CAMSK_MMON_Pos) |
RTC_T::CAMSK: MMON Mask
| #define RTC_CAMSK_MMON_Pos (2) |
RTC_T::CAMSK: MMON Position
| #define RTC_CAMSK_MTENDAY_Msk (0x1ul << RTC_CAMSK_MTENDAY_Pos) |
RTC_T::CAMSK: MTENDAY Mask
| #define RTC_CAMSK_MTENDAY_Pos (1) |
RTC_T::CAMSK: MTENDAY Position
| #define RTC_CAMSK_MTENMON_Msk (0x1ul << RTC_CAMSK_MTENMON_Pos) |
RTC_T::CAMSK: MTENMON Mask
| #define RTC_CAMSK_MTENMON_Pos (3) |
RTC_T::CAMSK: MTENMON Position
| #define RTC_CAMSK_MTENYEAR_Msk (0x1ul << RTC_CAMSK_MTENYEAR_Pos) |
RTC_T::CAMSK: MTENYEAR Mask
| #define RTC_CAMSK_MTENYEAR_Pos (5) |
RTC_T::CAMSK: MTENYEAR Position
| #define RTC_CAMSK_MYEAR_Msk (0x1ul << RTC_CAMSK_MYEAR_Pos) |
RTC_T::CAMSK: MYEAR Mask
| #define RTC_CAMSK_MYEAR_Pos (4) |
RTC_T::CAMSK: MYEAR Position
| #define RTC_CLKFMT_24HEN_Msk (0x1ul << RTC_CLKFMT_24HEN_Pos) |
RTC_T::CLKFMT: 24HEN Mask
| #define RTC_CLKFMT_24HEN_Pos (0) |
RTC_T::CLKFMT: 24HEN Position
| #define RTC_FREQADJ_FCR_BUSY_Msk (0x1ul << RTC_FREQADJ_FCR_BUSY_Pos) |
RTC_T::FREQADJ: FCR_BUSY Mask
| #define RTC_FREQADJ_FCR_BUSY_Pos (31) |
RTC_T::FREQADJ: FCR_BUSY Position
| #define RTC_FREQADJ_FRACTION_Msk (0x3ful << RTC_FREQADJ_FRACTION_Pos) |
RTC_T::FREQADJ: FRACTION Mask
| #define RTC_FREQADJ_FRACTION_Pos (0) |
RTC_T::FREQADJ: FRACTION Position
| #define RTC_FREQADJ_FREQADJ_Msk (0x3ffffful << RTC_FREQADJ_FREQADJ_Pos) |
RTC_T::FREQADJ: FREQADJ Mask
| #define RTC_FREQADJ_FREQADJ_Pos (0) |
RTC_T::FREQADJ: FREQADJ Position
| #define RTC_FREQADJ_INTEGER_Msk (0x1ful << RTC_FREQADJ_INTEGER_Pos) |
RTC_T::FREQADJ: INTEGER Mask
| #define RTC_FREQADJ_INTEGER_Pos (8) |
RTC_T::FREQADJ: INTEGER Position
| #define RTC_GPIOCTL0_CTLSEL0_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL0_Pos) |
RTC_T::GPIOCTL0: CTLSEL0 Mask
| #define RTC_GPIOCTL0_CTLSEL0_Pos (3) |
RTC_T::GPIOCTL0: CTLSEL0 Position
| #define RTC_GPIOCTL0_CTLSEL1_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL1_Pos) |
RTC_T::GPIOCTL0: CTLSEL1 Mask
| #define RTC_GPIOCTL0_CTLSEL1_Pos (11) |
RTC_T::GPIOCTL0: CTLSEL1 Position
| #define RTC_GPIOCTL0_CTLSEL2_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL2_Pos) |
RTC_T::GPIOCTL0: CTLSEL2 Mask
| #define RTC_GPIOCTL0_CTLSEL2_Pos (19) |
RTC_T::GPIOCTL0: CTLSEL2 Position
| #define RTC_GPIOCTL0_CTLSEL3_Msk (0x1ul << RTC_GPIOCTL0_CTLSEL3_Pos) |
RTC_T::GPIOCTL0: CTLSEL3 Mask
| #define RTC_GPIOCTL0_CTLSEL3_Pos (27) |
RTC_T::GPIOCTL0: CTLSEL3 Position
| #define RTC_GPIOCTL0_DOUT0_Msk (0x1ul << RTC_GPIOCTL0_DOUT0_Pos) |
RTC_T::GPIOCTL0: DOUT0 Mask
| #define RTC_GPIOCTL0_DOUT0_Pos (2) |
RTC_T::GPIOCTL0: DOUT0 Position
| #define RTC_GPIOCTL0_DOUT1_Msk (0x1ul << RTC_GPIOCTL0_DOUT1_Pos) |
RTC_T::GPIOCTL0: DOUT1 Mask
| #define RTC_GPIOCTL0_DOUT1_Pos (10) |
RTC_T::GPIOCTL0: DOUT1 Position
| #define RTC_GPIOCTL0_DOUT2_Msk (0x1ul << RTC_GPIOCTL0_DOUT2_Pos) |
RTC_T::GPIOCTL0: DOUT2 Mask
| #define RTC_GPIOCTL0_DOUT2_Pos (18) |
RTC_T::GPIOCTL0: DOUT2 Position
| #define RTC_GPIOCTL0_DOUT3_Msk (0x1ul << RTC_GPIOCTL0_DOUT3_Pos) |
RTC_T::GPIOCTL0: DOUT3 Mask
| #define RTC_GPIOCTL0_DOUT3_Pos (26) |
RTC_T::GPIOCTL0: DOUT3 Position
| #define RTC_GPIOCTL0_OPMODE0_Msk (0x3ul << RTC_GPIOCTL0_OPMODE0_Pos) |
RTC_T::GPIOCTL0: OPMODE0 Mask
| #define RTC_GPIOCTL0_OPMODE0_Pos (0) |
RTC_T::GPIOCTL0: OPMODE0 Position
| #define RTC_GPIOCTL0_OPMODE1_Msk (0x3ul << RTC_GPIOCTL0_OPMODE1_Pos) |
RTC_T::GPIOCTL0: OPMODE1 Mask
| #define RTC_GPIOCTL0_OPMODE1_Pos (8) |
RTC_T::GPIOCTL0: OPMODE1 Position
| #define RTC_GPIOCTL0_OPMODE2_Msk (0x3ul << RTC_GPIOCTL0_OPMODE2_Pos) |
RTC_T::GPIOCTL0: OPMODE2 Mask
| #define RTC_GPIOCTL0_OPMODE2_Pos (16) |
RTC_T::GPIOCTL0: OPMODE2 Position
| #define RTC_GPIOCTL0_OPMODE3_Msk (0x3ul << RTC_GPIOCTL0_OPMODE3_Pos) |
RTC_T::GPIOCTL0: OPMODE3 Mask
| #define RTC_GPIOCTL0_OPMODE3_Pos (24) |
RTC_T::GPIOCTL0: OPMODE3 Position
| #define RTC_GPIOCTL0_PUSEL0_Msk (0x3ul << RTC_GPIOCTL0_PUSEL0_Pos) |
RTC_T::GPIOCTL0: PUSEL0 Mask
| #define RTC_GPIOCTL0_PUSEL0_Pos (4) |
RTC_T::GPIOCTL0: PUSEL0 Position
| #define RTC_GPIOCTL0_PUSEL1_Msk (0x3ul << RTC_GPIOCTL0_PUSEL1_Pos) |
RTC_T::GPIOCTL0: PUSEL1 Mask
| #define RTC_GPIOCTL0_PUSEL1_Pos (12) |
RTC_T::GPIOCTL0: PUSEL1 Position
| #define RTC_GPIOCTL0_PUSEL2_Msk (0x3ul << RTC_GPIOCTL0_PUSEL2_Pos) |
RTC_T::GPIOCTL0: PUSEL2 Mask
| #define RTC_GPIOCTL0_PUSEL2_Pos (20) |
RTC_T::GPIOCTL0: PUSEL2 Position
| #define RTC_GPIOCTL0_PUSEL3_Msk (0x3ul << RTC_GPIOCTL0_PUSEL3_Pos) |
RTC_T::GPIOCTL0: PUSEL3 Mask
| #define RTC_GPIOCTL0_PUSEL3_Pos (28) |
RTC_T::GPIOCTL0: PUSEL3 Position
| #define RTC_GPIOCTL1_CTLSEL4_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL4_Pos) |
RTC_T::GPIOCTL1: CTLSEL4 Mask
| #define RTC_GPIOCTL1_CTLSEL4_Pos (3) |
RTC_T::GPIOCTL1: CTLSEL4 Position
| #define RTC_GPIOCTL1_CTLSEL5_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL5_Pos) |
RTC_T::GPIOCTL1: CTLSEL5 Mask
| #define RTC_GPIOCTL1_CTLSEL5_Pos (11) |
RTC_T::GPIOCTL1: CTLSEL5 Position
| #define RTC_GPIOCTL1_CTLSEL6_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL6_Pos) |
RTC_T::GPIOCTL1: CTLSEL6 Mask
| #define RTC_GPIOCTL1_CTLSEL6_Pos (19) |
RTC_T::GPIOCTL1: CTLSEL6 Position
| #define RTC_GPIOCTL1_CTLSEL7_Msk (0x1ul << RTC_GPIOCTL1_CTLSEL7_Pos) |
RTC_T::GPIOCTL1: CTLSEL7 Mask
| #define RTC_GPIOCTL1_CTLSEL7_Pos (27) |
RTC_T::GPIOCTL1: CTLSEL7 Position
| #define RTC_GPIOCTL1_DOUT4_Msk (0x1ul << RTC_GPIOCTL1_DOUT4_Pos) |
RTC_T::GPIOCTL1: DOUT4 Mask
| #define RTC_GPIOCTL1_DOUT4_Pos (2) |
RTC_T::GPIOCTL1: DOUT4 Position
| #define RTC_GPIOCTL1_DOUT5_Msk (0x1ul << RTC_GPIOCTL1_DOUT5_Pos) |
RTC_T::GPIOCTL1: DOUT5 Mask
| #define RTC_GPIOCTL1_DOUT5_Pos (10) |
RTC_T::GPIOCTL1: DOUT5 Position
| #define RTC_GPIOCTL1_DOUT6_Msk (0x1ul << RTC_GPIOCTL1_DOUT6_Pos) |
RTC_T::GPIOCTL1: DOUT6 Mask
| #define RTC_GPIOCTL1_DOUT6_Pos (18) |
RTC_T::GPIOCTL1: DOUT6 Position
| #define RTC_GPIOCTL1_DOUT7_Msk (0x1ul << RTC_GPIOCTL1_DOUT7_Pos) |
RTC_T::GPIOCTL1: DOUT7 Mask
| #define RTC_GPIOCTL1_DOUT7_Pos (26) |
RTC_T::GPIOCTL1: DOUT7 Position
| #define RTC_GPIOCTL1_OPMODE4_Msk (0x3ul << RTC_GPIOCTL1_OPMODE4_Pos) |
RTC_T::GPIOCTL1: OPMODE4 Mask
| #define RTC_GPIOCTL1_OPMODE4_Pos (0) |
RTC_T::GPIOCTL1: OPMODE4 Position
| #define RTC_GPIOCTL1_OPMODE5_Msk (0x3ul << RTC_GPIOCTL1_OPMODE5_Pos) |
RTC_T::GPIOCTL1: OPMODE5 Mask
| #define RTC_GPIOCTL1_OPMODE5_Pos (8) |
RTC_T::GPIOCTL1: OPMODE5 Position
| #define RTC_GPIOCTL1_OPMODE6_Msk (0x3ul << RTC_GPIOCTL1_OPMODE6_Pos) |
RTC_T::GPIOCTL1: OPMODE6 Mask
| #define RTC_GPIOCTL1_OPMODE6_Pos (16) |
RTC_T::GPIOCTL1: OPMODE6 Position
| #define RTC_GPIOCTL1_OPMODE7_Msk (0x3ul << RTC_GPIOCTL1_OPMODE7_Pos) |
RTC_T::GPIOCTL1: OPMODE7 Mask
| #define RTC_GPIOCTL1_OPMODE7_Pos (24) |
RTC_T::GPIOCTL1: OPMODE7 Position
| #define RTC_GPIOCTL1_PUSEL4_Msk (0x3ul << RTC_GPIOCTL1_PUSEL4_Pos) |
RTC_T::GPIOCTL1: PUSEL4 Mask
| #define RTC_GPIOCTL1_PUSEL4_Pos (4) |
RTC_T::GPIOCTL1: PUSEL4 Position
| #define RTC_GPIOCTL1_PUSEL5_Msk (0x3ul << RTC_GPIOCTL1_PUSEL5_Pos) |
RTC_T::GPIOCTL1: PUSEL5 Mask
| #define RTC_GPIOCTL1_PUSEL5_Pos (12) |
RTC_T::GPIOCTL1: PUSEL5 Position
| #define RTC_GPIOCTL1_PUSEL6_Msk (0x3ul << RTC_GPIOCTL1_PUSEL6_Pos) |
RTC_T::GPIOCTL1: PUSEL6 Mask
| #define RTC_GPIOCTL1_PUSEL6_Pos (20) |
RTC_T::GPIOCTL1: PUSEL6 Position
| #define RTC_GPIOCTL1_PUSEL7_Msk (0x3ul << RTC_GPIOCTL1_PUSEL7_Pos) |
RTC_T::GPIOCTL1: PUSEL7 Mask
| #define RTC_GPIOCTL1_PUSEL7_Pos (28) |
RTC_T::GPIOCTL1: PUSEL7 Position
| #define RTC_INIT_ACTIVE_Msk (0x1ul << RTC_INIT_ACTIVE_Pos) |
RTC_T::INIT: INIT_ACTIVE Mask
| #define RTC_INIT_ACTIVE_Pos (0) |
@addtogroup RTC_CONST RTC Bit Field Definition Constant Definitions for RTC Controller
RTC_T::INIT: INIT_ACTIVE Position
| #define RTC_INIT_INIT_Msk (0x7ffffffful << RTC_INIT_INIT_Pos) |
RTC_T::INIT: INIT Mask
| #define RTC_INIT_INIT_Pos (1) |
RTC_T::INIT: INIT Position
| #define RTC_INTEN_ALMIEN_Msk (0x1ul << RTC_INTEN_ALMIEN_Pos) |
RTC_T::INTEN: ALMIEN Mask
| #define RTC_INTEN_ALMIEN_Pos (0) |
RTC_T::INTEN: ALMIEN Position
| #define RTC_INTEN_TICKIEN_Msk (0x1ul << RTC_INTEN_TICKIEN_Pos) |
RTC_T::INTEN: TICKIEN Mask
| #define RTC_INTEN_TICKIEN_Pos (1) |
RTC_T::INTEN: TICKIEN Position
| #define RTC_INTSTS_ALMIF_Msk (0x1ul << RTC_INTSTS_ALMIF_Pos) |
RTC_T::INTSTS: ALMIF Mask
| #define RTC_INTSTS_ALMIF_Pos (0) |
RTC_T::INTSTS: ALMIF Position
| #define RTC_INTSTS_TICKIF_Msk (0x1ul << RTC_INTSTS_TICKIF_Pos) |
RTC_T::INTSTS: TICKIF Mask
| #define RTC_INTSTS_TICKIF_Pos (1) |
RTC_T::INTSTS: TICKIF Position
| #define RTC_LEAPYEAR_LEAPYEAR_Msk (0x1ul << RTC_LEAPYEAR_LEAPYEAR_Pos) |
RTC_T::LEAPYEAR: LEAPYEAR Mask
| #define RTC_LEAPYEAR_LEAPYEAR_Pos (0) |
RTC_T::LEAPYEAR: LEAPYEAR Position
| #define RTC_LXTCTL_GAIN_Msk (0x3ul << RTC_LXTCTL_GAIN_Pos) |
RTC_T::LXTCTL: GAIN Mask
| #define RTC_LXTCTL_GAIN_Pos (1) |
RTC_T::LXTCTL: GAIN Position
| #define RTC_RWEN_RTCBUSY_Msk (0x1ul << RTC_RWEN_RTCBUSY_Pos) |
RTC_T::RWEN: RTCBUSY Mask
| #define RTC_RWEN_RTCBUSY_Pos (24) |
RTC_T::RWEN: RTCBUSY Position
| #define RTC_RWEN_RWENF_Msk (0x1ul << RTC_RWEN_RWENF_Pos) |
RTC_T::RWEN: RWENF Mask
| #define RTC_RWEN_RWENF_Pos (16) |
RTC_T::RWEN: RWENF Position
| #define RTC_TALM_HR_Msk (0xful << RTC_TALM_HR_Pos) |
RTC_T::TALM: HR Mask
| #define RTC_TALM_HR_Pos (16) |
RTC_T::TALM: HR Position
| #define RTC_TALM_MIN_Msk (0xful << RTC_TALM_MIN_Pos) |
RTC_T::TALM: MIN Mask
| #define RTC_TALM_MIN_Pos (8) |
RTC_T::TALM: MIN Position
| #define RTC_TALM_SEC_Msk (0xful << RTC_TALM_SEC_Pos) |
RTC_T::TALM: SEC Mask
| #define RTC_TALM_SEC_Pos (0) |
RTC_T::TALM: SEC Position
| #define RTC_TALM_TENHR_Msk (0x3ul << RTC_TALM_TENHR_Pos) |
RTC_T::TALM: TENHR Mask
| #define RTC_TALM_TENHR_Pos (20) |
RTC_T::TALM: TENHR Position
| #define RTC_TALM_TENMIN_Msk (0x7ul << RTC_TALM_TENMIN_Pos) |
RTC_T::TALM: TENMIN Mask
| #define RTC_TALM_TENMIN_Pos (12) |
RTC_T::TALM: TENMIN Position
| #define RTC_TALM_TENSEC_Msk (0x7ul << RTC_TALM_TENSEC_Pos) |
RTC_T::TALM: TENSEC Mask
| #define RTC_TALM_TENSEC_Pos (4) |
RTC_T::TALM: TENSEC Position
| #define RTC_TAMSK_MHR_Msk (0x1ul << RTC_TAMSK_MHR_Pos) |
RTC_T::TAMSK: MHR Mask
| #define RTC_TAMSK_MHR_Pos (4) |
RTC_T::TAMSK: MHR Position
| #define RTC_TAMSK_MMIN_Msk (0x1ul << RTC_TAMSK_MMIN_Pos) |
RTC_T::TAMSK: MMIN Mask
| #define RTC_TAMSK_MMIN_Pos (2) |
RTC_T::TAMSK: MMIN Position
| #define RTC_TAMSK_MSEC_Msk (0x1ul << RTC_TAMSK_MSEC_Pos) |
RTC_T::TAMSK: MSEC Mask
| #define RTC_TAMSK_MSEC_Pos (0) |
RTC_T::TAMSK: MSEC Position
| #define RTC_TAMSK_MTENHR_Msk (0x1ul << RTC_TAMSK_MTENHR_Pos) |
RTC_T::TAMSK: MTENHR Mask
| #define RTC_TAMSK_MTENHR_Pos (5) |
RTC_T::TAMSK: MTENHR Position
| #define RTC_TAMSK_MTENMIN_Msk (0x1ul << RTC_TAMSK_MTENMIN_Pos) |
RTC_T::TAMSK: MTENMIN Mask
| #define RTC_TAMSK_MTENMIN_Pos (3) |
RTC_T::TAMSK: MTENMIN Position
| #define RTC_TAMSK_MTENSEC_Msk (0x1ul << RTC_TAMSK_MTENSEC_Pos) |
RTC_T::TAMSK: MTENSEC Mask
| #define RTC_TAMSK_MTENSEC_Pos (1) |
RTC_T::TAMSK: MTENSEC Position
| #define RTC_TICK_TICK_Msk (0x7ul << RTC_TICK_TICK_Pos) |
RTC_T::TICK: TICK Mask
| #define RTC_TICK_TICK_Pos (0) |
RTC_T::TICK: TICK Position
| #define RTC_TIME_HR_Msk (0xful << RTC_TIME_HR_Pos) |
RTC_T::TIME: HR Mask
| #define RTC_TIME_HR_Pos (16) |
RTC_T::TIME: HR Position
| #define RTC_TIME_MIN_Msk (0xful << RTC_TIME_MIN_Pos) |
RTC_T::TIME: MIN Mask
| #define RTC_TIME_MIN_Pos (8) |
RTC_T::TIME: MIN Position
| #define RTC_TIME_SEC_Msk (0xful << RTC_TIME_SEC_Pos) |
RTC_T::TIME: SEC Mask
| #define RTC_TIME_SEC_Pos (0) |
RTC_T::TIME: SEC Position
| #define RTC_TIME_TENHR_Msk (0x3ul << RTC_TIME_TENHR_Pos) |
RTC_T::TIME: TENHR Mask
| #define RTC_TIME_TENHR_Pos (20) |
RTC_T::TIME: TENHR Position
| #define RTC_TIME_TENMIN_Msk (0x7ul << RTC_TIME_TENMIN_Pos) |
RTC_T::TIME: TENMIN Mask
| #define RTC_TIME_TENMIN_Pos (12) |
RTC_T::TIME: TENMIN Position
| #define RTC_TIME_TENSEC_Msk (0x7ul << RTC_TIME_TENSEC_Pos) |
RTC_T::TIME: TENSEC Mask
| #define RTC_TIME_TENSEC_Pos (4) |
RTC_T::TIME: TENSEC Position
| #define RTC_WEEKDAY_WEEKDAY_Msk (0x7ul << RTC_WEEKDAY_WEEKDAY_Pos) |
RTC_T::WEEKDAY: WEEKDAY Mask
| #define RTC_WEEKDAY_WEEKDAY_Pos (0) |
RTC_T::WEEKDAY: WEEKDAY Position
| #define SC_ACTCTL_T1EXT_Msk (0x1ful << SC_ACTCTL_T1EXT_Pos) |
SC_T::ACTCTL: T1EXT Mask
| #define SC_ACTCTL_T1EXT_Pos (0) |
SC_T::ACTCTL: T1EXT Position
| #define SC_ALTCTL_ACTEN_Msk (0x1ul << SC_ALTCTL_ACTEN_Pos) |
SC_T::ALTCTL: ACTEN Mask
| #define SC_ALTCTL_ACTEN_Pos (3) |
SC_T::ALTCTL: ACTEN Position
| #define SC_ALTCTL_ACTSTS0_Msk (0x1ul << SC_ALTCTL_ACTSTS0_Pos) |
SC_T::ALTCTL: ACTSTS0 Mask
| #define SC_ALTCTL_ACTSTS0_Pos (13) |
SC_T::ALTCTL: ACTSTS0 Position
| #define SC_ALTCTL_ACTSTS1_Msk (0x1ul << SC_ALTCTL_ACTSTS1_Pos) |
SC_T::ALTCTL: ACTSTS1 Mask
| #define SC_ALTCTL_ACTSTS1_Pos (14) |
SC_T::ALTCTL: ACTSTS1 Position
| #define SC_ALTCTL_ACTSTS2_Msk (0x1ul << SC_ALTCTL_ACTSTS2_Pos) |
SC_T::ALTCTL: ACTSTS2 Mask
| #define SC_ALTCTL_ACTSTS2_Pos (15) |
SC_T::ALTCTL: ACTSTS2 Position
| #define SC_ALTCTL_ADACEN_Msk (0x1ul << SC_ALTCTL_ADACEN_Pos) |
SC_T::ALTCTL: ADACEN Mask
| #define SC_ALTCTL_ADACEN_Pos (11) |
SC_T::ALTCTL: ADACEN Position
| #define SC_ALTCTL_CNTEN0_Msk (0x1ul << SC_ALTCTL_CNTEN0_Pos) |
SC_T::ALTCTL: CNTEN0 Mask
| #define SC_ALTCTL_CNTEN0_Pos (5) |
SC_T::ALTCTL: CNTEN0 Position
| #define SC_ALTCTL_CNTEN1_Msk (0x1ul << SC_ALTCTL_CNTEN1_Pos) |
SC_T::ALTCTL: CNTEN1 Mask
| #define SC_ALTCTL_CNTEN1_Pos (6) |
SC_T::ALTCTL: CNTEN1 Position
| #define SC_ALTCTL_CNTEN2_Msk (0x1ul << SC_ALTCTL_CNTEN2_Pos) |
SC_T::ALTCTL: CNTEN2 Mask
| #define SC_ALTCTL_CNTEN2_Pos (7) |
SC_T::ALTCTL: CNTEN2 Position
| #define SC_ALTCTL_DACTEN_Msk (0x1ul << SC_ALTCTL_DACTEN_Pos) |
SC_T::ALTCTL: DACTEN Mask
| #define SC_ALTCTL_DACTEN_Pos (2) |
SC_T::ALTCTL: DACTEN Position
| #define SC_ALTCTL_INITSEL_Msk (0x3ul << SC_ALTCTL_INITSEL_Pos) |
SC_T::ALTCTL: INITSEL Mask
| #define SC_ALTCTL_INITSEL_Pos (8) |
SC_T::ALTCTL: INITSEL Position
| #define SC_ALTCTL_RXBGTEN_Msk (0x1ul << SC_ALTCTL_RXBGTEN_Pos) |
SC_T::ALTCTL: RXBGTEN Mask
| #define SC_ALTCTL_RXBGTEN_Pos (12) |
SC_T::ALTCTL: RXBGTEN Position
| #define SC_ALTCTL_RXRST_Msk (0x1ul << SC_ALTCTL_RXRST_Pos) |
SC_T::ALTCTL: RXRST Mask
| #define SC_ALTCTL_RXRST_Pos (1) |
SC_T::ALTCTL: RXRST Position
| #define SC_ALTCTL_SYNC_Msk (0x1ul << SC_ALTCTL_SYNC_Pos) |
SC_T::ALTCTL: SYNC Mask
| #define SC_ALTCTL_SYNC_Pos (31) |
SC_T::ALTCTL: SYNC Position
| #define SC_ALTCTL_TXRST_Msk (0x1ul << SC_ALTCTL_TXRST_Pos) |
SC_T::ALTCTL: TXRST Mask
| #define SC_ALTCTL_TXRST_Pos (0) |
SC_T::ALTCTL: TXRST Position
| #define SC_ALTCTL_WARSTEN_Msk (0x1ul << SC_ALTCTL_WARSTEN_Pos) |
SC_T::ALTCTL: WARSTEN Mask
| #define SC_ALTCTL_WARSTEN_Pos (4) |
SC_T::ALTCTL: WARSTEN Position
| #define SC_CTL_AUTOCEN_Msk (0x1ul << SC_CTL_AUTOCEN_Pos) |
| #define SC_CTL_BGT_Msk (0x1ful << SC_CTL_BGT_Pos) |
| #define SC_CTL_CDDBSEL_Msk (0x3ul << SC_CTL_CDDBSEL_Pos) |
| #define SC_CTL_CDDBSEL_Pos (24) |
| #define SC_CTL_CDLV_Msk (0x1ul << SC_CTL_CDLV_Pos) |
| #define SC_CTL_CONSEL_Msk (0x3ul << SC_CTL_CONSEL_Pos) |
| #define SC_CTL_NSB_Msk (0x1ul << SC_CTL_NSB_Pos) |
| #define SC_CTL_RXOFF_Msk (0x1ul << SC_CTL_RXOFF_Pos) |
| #define SC_CTL_RXRTY_Msk (0x7ul << SC_CTL_RXRTY_Pos) |
| #define SC_CTL_RXRTYEN_Msk (0x1ul << SC_CTL_RXRTYEN_Pos) |
| #define SC_CTL_RXRTYEN_Pos (19) |
| #define SC_CTL_RXTRGLV_Msk (0x3ul << SC_CTL_RXTRGLV_Pos) |
| #define SC_CTL_SCEN_Msk (0x1ul << SC_CTL_SCEN_Pos) |
| #define SC_CTL_SYNC_Msk (0x1ul << SC_CTL_SYNC_Pos) |
| #define SC_CTL_TMRSEL_Msk (0x3ul << SC_CTL_TMRSEL_Pos) |
| #define SC_CTL_TXOFF_Msk (0x1ul << SC_CTL_TXOFF_Pos) |
| #define SC_CTL_TXRTY_Msk (0x7ul << SC_CTL_TXRTY_Pos) |
| #define SC_CTL_TXRTYEN_Msk (0x1ul << SC_CTL_TXRTYEN_Pos) |
| #define SC_CTL_TXRTYEN_Pos (23) |
| #define SC_DAT_DAT_Msk (0xfful << SC_DAT_DAT_Pos) |
| #define SC_DAT_DAT_Pos (0) |
| #define SC_EGT_EGT_Msk (0xfful << SC_EGT_EGT_Pos) |
| #define SC_ETUCTL_ETURDIV_Msk (0xffful << SC_ETUCTL_ETURDIV_Pos) |
SC_T::ETUCTL: ETURDIV Mask
| #define SC_ETUCTL_ETURDIV_Pos (0) |
SC_T::ETUCTL: ETURDIV Position
| #define SC_INTEN_ACERRIEN_Msk (0x1ul << SC_INTEN_ACERRIEN_Pos) |
SC_T::INTEN: ACERRIEN Mask
| #define SC_INTEN_ACERRIEN_Pos (10) |
SC_T::INTEN: ACERRIEN Position
| #define SC_INTEN_BGTIEN_Msk (0x1ul << SC_INTEN_BGTIEN_Pos) |
SC_T::INTEN: BGTIEN Mask
| #define SC_INTEN_BGTIEN_Pos (6) |
SC_T::INTEN: BGTIEN Position
| #define SC_INTEN_CDIEN_Msk (0x1ul << SC_INTEN_CDIEN_Pos) |
SC_T::INTEN: CDIEN Mask
| #define SC_INTEN_CDIEN_Pos (7) |
SC_T::INTEN: CDIEN Position
| #define SC_INTEN_INITIEN_Msk (0x1ul << SC_INTEN_INITIEN_Pos) |
SC_T::INTEN: INITIEN Mask
| #define SC_INTEN_INITIEN_Pos (8) |
SC_T::INTEN: INITIEN Position
| #define SC_INTEN_RDAIEN_Msk (0x1ul << SC_INTEN_RDAIEN_Pos) |
SC_T::INTEN: RDAIEN Mask
| #define SC_INTEN_RDAIEN_Pos (0) |
SC_T::INTEN: RDAIEN Position
| #define SC_INTEN_RXTOIEN_Msk (0x1ul << SC_INTEN_RXTOIEN_Pos) |
SC_T::INTEN: RXTOIEN Mask
| #define SC_INTEN_RXTOIEN_Pos (9) |
SC_T::INTEN: RXTOIEN Position
| #define SC_INTEN_TBEIEN_Msk (0x1ul << SC_INTEN_TBEIEN_Pos) |
SC_T::INTEN: TBEIEN Mask
| #define SC_INTEN_TBEIEN_Pos (1) |
SC_T::INTEN: TBEIEN Position
| #define SC_INTEN_TERRIEN_Msk (0x1ul << SC_INTEN_TERRIEN_Pos) |
SC_T::INTEN: TERRIEN Mask
| #define SC_INTEN_TERRIEN_Pos (2) |
SC_T::INTEN: TERRIEN Position
| #define SC_INTEN_TMR0IEN_Msk (0x1ul << SC_INTEN_TMR0IEN_Pos) |
SC_T::INTEN: TMR0IEN Mask
| #define SC_INTEN_TMR0IEN_Pos (3) |
SC_T::INTEN: TMR0IEN Position
| #define SC_INTEN_TMR1IEN_Msk (0x1ul << SC_INTEN_TMR1IEN_Pos) |
SC_T::INTEN: TMR1IEN Mask
| #define SC_INTEN_TMR1IEN_Pos (4) |
SC_T::INTEN: TMR1IEN Position
| #define SC_INTEN_TMR2IEN_Msk (0x1ul << SC_INTEN_TMR2IEN_Pos) |
SC_T::INTEN: TMR2IEN Mask
| #define SC_INTEN_TMR2IEN_Pos (5) |
SC_T::INTEN: TMR2IEN Position
| #define SC_INTSTS_ACERRIF_Msk (0x1ul << SC_INTSTS_ACERRIF_Pos) |
SC_T::INTSTS: ACERRIF Mask
| #define SC_INTSTS_ACERRIF_Pos (10) |
SC_T::INTSTS: ACERRIF Position
| #define SC_INTSTS_BGTIF_Msk (0x1ul << SC_INTSTS_BGTIF_Pos) |
SC_T::INTSTS: BGTIF Mask
| #define SC_INTSTS_BGTIF_Pos (6) |
SC_T::INTSTS: BGTIF Position
| #define SC_INTSTS_CDIF_Msk (0x1ul << SC_INTSTS_CDIF_Pos) |
SC_T::INTSTS: CDIF Mask
| #define SC_INTSTS_CDIF_Pos (7) |
SC_T::INTSTS: CDIF Position
| #define SC_INTSTS_INITIF_Msk (0x1ul << SC_INTSTS_INITIF_Pos) |
SC_T::INTSTS: INITIF Mask
| #define SC_INTSTS_INITIF_Pos (8) |
SC_T::INTSTS: INITIF Position
| #define SC_INTSTS_RDAIF_Msk (0x1ul << SC_INTSTS_RDAIF_Pos) |
SC_T::INTSTS: RDAIF Mask
| #define SC_INTSTS_RDAIF_Pos (0) |
SC_T::INTSTS: RDAIF Position
| #define SC_INTSTS_RXTOIF_Msk (0x1ul << SC_INTSTS_RXTOIF_Pos) |
SC_T::INTSTS: RXTOIF Mask
| #define SC_INTSTS_RXTOIF_Pos (9) |
SC_T::INTSTS: RXTOIF Position
| #define SC_INTSTS_TBEIF_Msk (0x1ul << SC_INTSTS_TBEIF_Pos) |
SC_T::INTSTS: TBEIF Mask
| #define SC_INTSTS_TBEIF_Pos (1) |
SC_T::INTSTS: TBEIF Position
| #define SC_INTSTS_TERRIF_Msk (0x1ul << SC_INTSTS_TERRIF_Pos) |
SC_T::INTSTS: TERRIF Mask
| #define SC_INTSTS_TERRIF_Pos (2) |
SC_T::INTSTS: TERRIF Position
| #define SC_INTSTS_TMR0IF_Msk (0x1ul << SC_INTSTS_TMR0IF_Pos) |
SC_T::INTSTS: TMR0IF Mask
| #define SC_INTSTS_TMR0IF_Pos (3) |
SC_T::INTSTS: TMR0IF Position
| #define SC_INTSTS_TMR1IF_Msk (0x1ul << SC_INTSTS_TMR1IF_Pos) |
SC_T::INTSTS: TMR1IF Mask
| #define SC_INTSTS_TMR1IF_Pos (4) |
SC_T::INTSTS: TMR1IF Position
| #define SC_INTSTS_TMR2IF_Msk (0x1ul << SC_INTSTS_TMR2IF_Pos) |
SC_T::INTSTS: TMR2IF Mask
| #define SC_INTSTS_TMR2IF_Pos (5) |
SC_T::INTSTS: TMR2IF Position
| #define SC_PINCTL_CLKKEEP_Msk (0x1ul << SC_PINCTL_CLKKEEP_Pos) |
SC_T::PINCTL: CLKKEEP Mask
| #define SC_PINCTL_CLKKEEP_Pos (6) |
SC_T::PINCTL: CLKKEEP Position
| #define SC_PINCTL_DATASTS_Msk (0x1ul << SC_PINCTL_DATASTS_Pos) |
SC_T::PINCTL: DATASTS Mask
| #define SC_PINCTL_DATASTS_Pos (16) |
SC_T::PINCTL: DATASTS Position
| #define SC_PINCTL_PWREN_Msk (0x1ul << SC_PINCTL_PWREN_Pos) |
SC_T::PINCTL: PWREN Mask
| #define SC_PINCTL_PWREN_Pos (0) |
SC_T::PINCTL: PWREN Position
| #define SC_PINCTL_PWRINV_Msk (0x1ul << SC_PINCTL_PWRINV_Pos) |
SC_T::PINCTL: PWRINV Mask
| #define SC_PINCTL_PWRINV_Pos (11) |
SC_T::PINCTL: PWRINV Position
| #define SC_PINCTL_PWRSTS_Msk (0x1ul << SC_PINCTL_PWRSTS_Pos) |
SC_T::PINCTL: PWRSTS Mask
| #define SC_PINCTL_PWRSTS_Pos (17) |
SC_T::PINCTL: PWRSTS Position
| #define SC_PINCTL_RSTEN_Msk (0x1ul << SC_PINCTL_RSTEN_Pos) |
SC_T::PINCTL: RSTEN Mask
| #define SC_PINCTL_RSTEN_Pos (1) |
SC_T::PINCTL: RSTEN Position
| #define SC_PINCTL_RSTSTS_Msk (0x1ul << SC_PINCTL_RSTSTS_Pos) |
SC_T::PINCTL: RSTSTS Mask
| #define SC_PINCTL_RSTSTS_Pos (18) |
SC_T::PINCTL: RSTSTS Position
| #define SC_PINCTL_SCDATA_Msk (0x1ul << SC_PINCTL_SCDATA_Pos) |
SC_T::PINCTL: SCDATA Mask
| #define SC_PINCTL_SCDATA_Pos (9) |
SC_T::PINCTL: SCDATA Position
| #define SC_PINCTL_SYNC_Msk (0x1ul << SC_PINCTL_SYNC_Pos) |
SC_T::PINCTL: SYNC Mask
| #define SC_PINCTL_SYNC_Pos (30) |
SC_T::PINCTL: SYNC Position
| #define SC_RXTOUT_RFTM_Msk (0x1fful << SC_RXTOUT_RFTM_Pos) |
SC_T::RXTOUT: RFTM Mask
| #define SC_RXTOUT_RFTM_Pos (0) |
SC_T::RXTOUT: RFTM Position
| #define SC_STATUS_BEF_Msk (0x1ul << SC_STATUS_BEF_Pos) |
SC_T::STATUS: BEF Mask
| #define SC_STATUS_BEF_Pos (6) |
SC_T::STATUS: BEF Position
| #define SC_STATUS_CDPINSTS_Msk (0x1ul << SC_STATUS_CDPINSTS_Pos) |
SC_T::STATUS: CDPINSTS Mask
| #define SC_STATUS_CDPINSTS_Pos (13) |
SC_T::STATUS: CDPINSTS Position
| #define SC_STATUS_CINSERT_Msk (0x1ul << SC_STATUS_CINSERT_Pos) |
SC_T::STATUS: CINSERT Mask
| #define SC_STATUS_CINSERT_Pos (12) |
SC_T::STATUS: CINSERT Position
| #define SC_STATUS_CREMOVE_Msk (0x1ul << SC_STATUS_CREMOVE_Pos) |
SC_T::STATUS: CREMOVE Mask
| #define SC_STATUS_CREMOVE_Pos (11) |
SC_T::STATUS: CREMOVE Position
| #define SC_STATUS_FEF_Msk (0x1ul << SC_STATUS_FEF_Pos) |
SC_T::STATUS: FEF Mask
| #define SC_STATUS_FEF_Pos (5) |
SC_T::STATUS: FEF Position
| #define SC_STATUS_PEF_Msk (0x1ul << SC_STATUS_PEF_Pos) |
SC_T::STATUS: PEF Mask
| #define SC_STATUS_PEF_Pos (4) |
SC_T::STATUS: PEF Position
| #define SC_STATUS_RXACT_Msk (0x1ul << SC_STATUS_RXACT_Pos) |
SC_T::STATUS: RXACT Mask
| #define SC_STATUS_RXACT_Pos (23) |
SC_T::STATUS: RXACT Position
| #define SC_STATUS_RXEMPTY_Msk (0x1ul << SC_STATUS_RXEMPTY_Pos) |
SC_T::STATUS: RXEMPTY Mask
| #define SC_STATUS_RXEMPTY_Pos (1) |
SC_T::STATUS: RXEMPTY Position
| #define SC_STATUS_RXFULL_Msk (0x1ul << SC_STATUS_RXFULL_Pos) |
SC_T::STATUS: RXFULL Mask
| #define SC_STATUS_RXFULL_Pos (2) |
SC_T::STATUS: RXFULL Position
| #define SC_STATUS_RXOV_Msk (0x1ul << SC_STATUS_RXOV_Pos) |
SC_T::STATUS: RXOV Mask
| #define SC_STATUS_RXOV_Pos (0) |
SC_T::STATUS: RXOV Position
| #define SC_STATUS_RXOVERR_Msk (0x1ul << SC_STATUS_RXOVERR_Pos) |
SC_T::STATUS: RXOVERR Mask
| #define SC_STATUS_RXOVERR_Pos (22) |
SC_T::STATUS: RXOVERR Position
| #define SC_STATUS_RXPOINT_Msk (0x7ul << SC_STATUS_RXPOINT_Pos) |
SC_T::STATUS: RXPOINT Mask
| #define SC_STATUS_RXPOINT_Pos (16) |
SC_T::STATUS: RXPOINT Position
| #define SC_STATUS_RXRERR_Msk (0x1ul << SC_STATUS_RXRERR_Pos) |
SC_T::STATUS: RXRERR Mask
| #define SC_STATUS_RXRERR_Pos (21) |
SC_T::STATUS: RXRERR Position
| #define SC_STATUS_TXACT_Msk (0x1ul << SC_STATUS_TXACT_Pos) |
SC_T::STATUS: TXACT Mask
| #define SC_STATUS_TXACT_Pos (31) |
SC_T::STATUS: TXACT Position
| #define SC_STATUS_TXEMPTY_Msk (0x1ul << SC_STATUS_TXEMPTY_Pos) |
SC_T::STATUS: TXEMPTY Mask
| #define SC_STATUS_TXEMPTY_Pos (9) |
SC_T::STATUS: TXEMPTY Position
| #define SC_STATUS_TXFULL_Msk (0x1ul << SC_STATUS_TXFULL_Pos) |
SC_T::STATUS: TXFULL Mask
| #define SC_STATUS_TXFULL_Pos (10) |
SC_T::STATUS: TXFULL Position
| #define SC_STATUS_TXOV_Msk (0x1ul << SC_STATUS_TXOV_Pos) |
SC_T::STATUS: TXOV Mask
| #define SC_STATUS_TXOV_Pos (8) |
SC_T::STATUS: TXOV Position
| #define SC_STATUS_TXOVERR_Msk (0x1ul << SC_STATUS_TXOVERR_Pos) |
SC_T::STATUS: TXOVERR Mask
| #define SC_STATUS_TXOVERR_Pos (30) |
SC_T::STATUS: TXOVERR Position
| #define SC_STATUS_TXPOINT_Msk (0x7ul << SC_STATUS_TXPOINT_Pos) |
SC_T::STATUS: TXPOINT Mask
| #define SC_STATUS_TXPOINT_Pos (24) |
SC_T::STATUS: TXPOINT Position
| #define SC_STATUS_TXRERR_Msk (0x1ul << SC_STATUS_TXRERR_Pos) |
SC_T::STATUS: TXRERR Mask
| #define SC_STATUS_TXRERR_Pos (29) |
SC_T::STATUS: TXRERR Position
| #define SC_TMRCTL0_CNT_Msk (0xfffffful << SC_TMRCTL0_CNT_Pos) |
SC_T::TMRCTL0: CNT Mask
| #define SC_TMRCTL0_CNT_Pos (0) |
SC_T::TMRCTL0: CNT Position
| #define SC_TMRCTL0_OPMODE_Msk (0xful << SC_TMRCTL0_OPMODE_Pos) |
SC_T::TMRCTL0: OPMODE Mask
| #define SC_TMRCTL0_OPMODE_Pos (24) |
SC_T::TMRCTL0: OPMODE Position
| #define SC_TMRCTL0_SYNC_Msk (0x1ul << SC_TMRCTL0_SYNC_Pos) |
SC_T::TMRCTL0: SYNC Mask
| #define SC_TMRCTL0_SYNC_Pos (31) |
SC_T::TMRCTL0: SYNC Position
| #define SC_TMRCTL1_CNT_Msk (0xfful << SC_TMRCTL1_CNT_Pos) |
SC_T::TMRCTL1: CNT Mask
| #define SC_TMRCTL1_CNT_Pos (0) |
SC_T::TMRCTL1: CNT Position
| #define SC_TMRCTL1_OPMODE_Msk (0xful << SC_TMRCTL1_OPMODE_Pos) |
SC_T::TMRCTL1: OPMODE Mask
| #define SC_TMRCTL1_OPMODE_Pos (24) |
SC_T::TMRCTL1: OPMODE Position
| #define SC_TMRCTL1_SYNC_Msk (0x1ul << SC_TMRCTL1_SYNC_Pos) |
SC_T::TMRCTL1: SYNC Mask
| #define SC_TMRCTL1_SYNC_Pos (31) |
SC_T::TMRCTL1: SYNC Position
| #define SC_TMRCTL2_CNT_Msk (0xfful << SC_TMRCTL2_CNT_Pos) |
SC_T::TMRCTL2: CNT Mask
| #define SC_TMRCTL2_CNT_Pos (0) |
SC_T::TMRCTL2: CNT Position
| #define SC_TMRCTL2_OPMODE_Msk (0xful << SC_TMRCTL2_OPMODE_Pos) |
SC_T::TMRCTL2: OPMODE Mask
| #define SC_TMRCTL2_OPMODE_Pos (24) |
SC_T::TMRCTL2: OPMODE Position
| #define SC_TMRCTL2_SYNC_Msk (0x1ul << SC_TMRCTL2_SYNC_Pos) |
SC_T::TMRCTL2: SYNC Mask
| #define SC_TMRCTL2_SYNC_Pos (31) |
SC_T::TMRCTL2: SYNC Position
| #define SC_UARTCTL_OPE_Msk (0x1ul << SC_UARTCTL_OPE_Pos) |
SC_T::UARTCTL: OPE Mask
| #define SC_UARTCTL_OPE_Pos (7) |
SC_T::UARTCTL: OPE Position
| #define SC_UARTCTL_PBOFF_Msk (0x1ul << SC_UARTCTL_PBOFF_Pos) |
SC_T::UARTCTL: PBOFF Mask
| #define SC_UARTCTL_PBOFF_Pos (6) |
SC_T::UARTCTL: PBOFF Position
| #define SC_UARTCTL_UARTEN_Msk (0x1ul << SC_UARTCTL_UARTEN_Pos) |
SC_T::UARTCTL: UARTEN Mask
| #define SC_UARTCTL_UARTEN_Pos (0) |
SC_T::UARTCTL: UARTEN Position
| #define SC_UARTCTL_WLS_Msk (0x3ul << SC_UARTCTL_WLS_Pos) |
SC_T::UARTCTL: WLS Mask
| #define SC_UARTCTL_WLS_Pos (4) |
SC_T::UARTCTL: WLS Position
| #define SDH_BLEN_BLKLEN_Msk (0x7fful << SDH_BLEN_BLKLEN_Pos) |
SDH_T::BLEN: BLKLEN Mask
| #define SDH_BLEN_BLKLEN_Pos (0) |
SDH_T::BLEN: BLKLEN Position
| #define SDH_CMDARG_ARGUMENT_Msk (0xfffffffful << SDH_CMDARG_ARGUMENT_Pos) |
SDH_T::CMDARG: ARGUMENT Mask
| #define SDH_CMDARG_ARGUMENT_Pos (0) |
SDH_T::CMDARG: ARGUMENT Position
| #define SDH_CTL_BLKCNT_Msk (0xfful << SDH_CTL_BLKCNT_Pos) |
SDH_T::CTL: BLKCNT Mask
| #define SDH_CTL_BLKCNT_Pos (16) |
SDH_T::CTL: BLKCNT Position
| #define SDH_CTL_CLK74OEN_Msk (0x1ul << SDH_CTL_CLK74OEN_Pos) |
SDH_T::CTL: CLK74OEN Mask
| #define SDH_CTL_CLK74OEN_Pos (5) |
SDH_T::CTL: CLK74OEN Position
| #define SDH_CTL_CLK8OEN_Msk (0x1ul << SDH_CTL_CLK8OEN_Pos) |
SDH_T::CTL: CLK8OEN Mask
| #define SDH_CTL_CLK8OEN_Pos (6) |
SDH_T::CTL: CLK8OEN Position
| #define SDH_CTL_CLKKEEP_Msk (0x1ul << SDH_CTL_CLKKEEP_Pos) |
SDH_T::CTL: CLKKEEP Mask
| #define SDH_CTL_CLKKEEP_Pos (7) |
SDH_T::CTL: CLKKEEP Position
| #define SDH_CTL_CMDCODE_Msk (0x3ful << SDH_CTL_CMDCODE_Pos) |
SDH_T::CTL: CMDCODE Mask
| #define SDH_CTL_CMDCODE_Pos (8) |
SDH_T::CTL: CMDCODE Position
| #define SDH_CTL_COEN_Msk (0x1ul << SDH_CTL_COEN_Pos) |
SDH_T::CTL: COEN Mask
| #define SDH_CTL_COEN_Pos (0) |
SDH_T::CTL: COEN Position
| #define SDH_CTL_CTLRST_Msk (0x1ul << SDH_CTL_CTLRST_Pos) |
SDH_T::CTL: CTLRST Mask
| #define SDH_CTL_CTLRST_Pos (14) |
SDH_T::CTL: CTLRST Position
| #define SDH_CTL_DBW_Msk (0x1ul << SDH_CTL_DBW_Pos) |
SDH_T::CTL: DBW Mask
| #define SDH_CTL_DBW_Pos (15) |
SDH_T::CTL: DBW Position
| #define SDH_CTL_DIEN_Msk (0x1ul << SDH_CTL_DIEN_Pos) |
SDH_T::CTL: DIEN Mask
| #define SDH_CTL_DIEN_Pos (2) |
SDH_T::CTL: DIEN Position
| #define SDH_CTL_DOEN_Msk (0x1ul << SDH_CTL_DOEN_Pos) |
SDH_T::CTL: DOEN Mask
| #define SDH_CTL_DOEN_Pos (3) |
SDH_T::CTL: DOEN Position
| #define SDH_CTL_R2EN_Msk (0x1ul << SDH_CTL_R2EN_Pos) |
SDH_T::CTL: R2EN Mask
| #define SDH_CTL_R2EN_Pos (4) |
SDH_T::CTL: R2EN Position
| #define SDH_CTL_RIEN_Msk (0x1ul << SDH_CTL_RIEN_Pos) |
SDH_T::CTL: RIEN Mask
| #define SDH_CTL_RIEN_Pos (1) |
SDH_T::CTL: RIEN Position
| #define SDH_CTL_SDNWR_Msk (0xful << SDH_CTL_SDNWR_Pos) |
SDH_T::CTL: SDNWR Mask
| #define SDH_CTL_SDNWR_Pos (24) |
SDH_T::CTL: SDNWR Position
| #define SDH_DMABCNT_BCNT_Msk (0x3fffffful << SDH_DMABCNT_BCNT_Pos) |
SDH_T::DMABCNT: BCNT Mask
| #define SDH_DMABCNT_BCNT_Pos (0) |
SDH_T::DMABCNT: BCNT Position
| #define SDH_DMACTL_DMABUSY_Msk (0x1ul << SDH_DMACTL_DMABUSY_Pos) |
SDH_T::DMACTL: DMABUSY Mask
| #define SDH_DMACTL_DMABUSY_Pos (9) |
SDH_T::DMACTL: DMABUSY Position
| #define SDH_DMACTL_DMAEN_Msk (0x1ul << SDH_DMACTL_DMAEN_Pos) |
SDH_T::DMACTL: DMAEN Mask
| #define SDH_DMACTL_DMAEN_Pos (0) |
@addtogroup SDH_CONST SDH Bit Field Definition Constant Definitions for SDH Controller
SDH_T::DMACTL: DMAEN Position
| #define SDH_DMACTL_DMARST_Msk (0x1ul << SDH_DMACTL_DMARST_Pos) |
SDH_T::DMACTL: DMARST Mask
| #define SDH_DMACTL_DMARST_Pos (1) |
SDH_T::DMACTL: DMARST Position
| #define SDH_DMACTL_SGEN_Msk (0x1ul << SDH_DMACTL_SGEN_Pos) |
SDH_T::DMACTL: SGEN Mask
| #define SDH_DMACTL_SGEN_Pos (3) |
SDH_T::DMACTL: SGEN Position
| #define SDH_DMAINTEN_ABORTIEN_Msk (0x1ul << SDH_DMAINTEN_ABORTIEN_Pos) |
SDH_T::DMAINTEN: ABORTIEN Mask
| #define SDH_DMAINTEN_ABORTIEN_Pos (0) |
SDH_T::DMAINTEN: ABORTIEN Position
| #define SDH_DMAINTEN_WEOTIEN_Msk (0x1ul << SDH_DMAINTEN_WEOTIEN_Pos) |
SDH_T::DMAINTEN: WEOTIEN Mask
| #define SDH_DMAINTEN_WEOTIEN_Pos (1) |
SDH_T::DMAINTEN: WEOTIEN Position
| #define SDH_DMAINTSTS_ABORTIF_Msk (0x1ul << SDH_DMAINTSTS_ABORTIF_Pos) |
SDH_T::DMAINTSTS: ABORTIF Mask
| #define SDH_DMAINTSTS_ABORTIF_Pos (0) |
SDH_T::DMAINTSTS: ABORTIF Position
| #define SDH_DMAINTSTS_WEOTIF_Msk (0x1ul << SDH_DMAINTSTS_WEOTIF_Pos) |
SDH_T::DMAINTSTS: WEOTIF Mask
| #define SDH_DMAINTSTS_WEOTIF_Pos (1) |
SDH_T::DMAINTSTS: WEOTIF Position
| #define SDH_DMASA_DMASA_Msk (0x7ffffffful << SDH_DMASA_DMASA_Pos) |
SDH_T::DMASA: DMASA Mask
| #define SDH_DMASA_DMASA_Pos (1) |
SDH_T::DMASA: DMASA Position
| #define SDH_DMASA_ORDER_Msk (0x1ul << SDH_DMASA_ORDER_Pos) |
SDH_T::DMASA: ORDER Mask
| #define SDH_DMASA_ORDER_Pos (0) |
SDH_T::DMASA: ORDER Position
| #define SDH_GCTL_GCTLRST_Msk (0x1ul << SDH_GCTL_GCTLRST_Pos) |
SDH_T::GCTL: GCTLRST Mask
| #define SDH_GCTL_GCTLRST_Pos (0) |
SDH_T::GCTL: GCTLRST Position
| #define SDH_GCTL_SDEN_Msk (0x1ul << SDH_GCTL_SDEN_Pos) |
SDH_T::GCTL: SDEN Mask
| #define SDH_GCTL_SDEN_Pos (1) |
SDH_T::GCTL: SDEN Position
| #define SDH_GINTEN_DTAIEN_Msk (0x1ul << SDH_GINTEN_DTAIEN_Pos) |
SDH_T::GINTEN: DTAIEN Mask
| #define SDH_GINTEN_DTAIEN_Pos (0) |
SDH_T::GINTEN: DTAIEN Position
| #define SDH_GINTSTS_DTAIF_Msk (0x1ul << SDH_GINTSTS_DTAIF_Pos) |
SDH_T::GINTSTS: DTAIF Mask
| #define SDH_GINTSTS_DTAIF_Pos (0) |
SDH_T::GINTSTS: DTAIF Position
| #define SDH_INTEN_BLKDIEN_Msk (0x1ul << SDH_INTEN_BLKDIEN_Pos) |
SDH_T::INTEN: BLKDIEN Mask
| #define SDH_INTEN_BLKDIEN_Pos (0) |
SDH_T::INTEN: BLKDIEN Position
| #define SDH_INTEN_CDIEN_Msk (0x1ul << SDH_INTEN_CDIEN_Pos) |
SDH_T::INTEN: CDIEN Mask
| #define SDH_INTEN_CDIEN_Pos (8) |
SDH_T::INTEN: CDIEN Position
| #define SDH_INTEN_CDSRC_Msk (0x1ul << SDH_INTEN_CDSRC_Pos) |
SDH_T::INTEN: CDSRC Mask
| #define SDH_INTEN_CDSRC_Pos (30) |
SDH_T::INTEN: CDSRC Position
| #define SDH_INTEN_CRCIEN_Msk (0x1ul << SDH_INTEN_CRCIEN_Pos) |
SDH_T::INTEN: CRCIEN Mask
| #define SDH_INTEN_CRCIEN_Pos (1) |
SDH_T::INTEN: CRCIEN Position
| #define SDH_INTEN_DITOIEN_Msk (0x1ul << SDH_INTEN_DITOIEN_Pos) |
SDH_T::INTEN: DITOIEN Mask
| #define SDH_INTEN_DITOIEN_Pos (13) |
SDH_T::INTEN: DITOIEN Position
| #define SDH_INTEN_RTOIEN_Msk (0x1ul << SDH_INTEN_RTOIEN_Pos) |
SDH_T::INTEN: RTOIEN Mask
| #define SDH_INTEN_RTOIEN_Pos (12) |
SDH_T::INTEN: RTOIEN Position
| #define SDH_INTEN_WKIEN_Msk (0x1ul << SDH_INTEN_WKIEN_Pos) |
SDH_T::INTEN: WKIEN Mask
| #define SDH_INTEN_WKIEN_Pos (14) |
SDH_T::INTEN: WKIEN Position
| #define SDH_INTSTS_BLKDIF_Msk (0x1ul << SDH_INTSTS_BLKDIF_Pos) |
SDH_T::INTSTS: BLKDIF Mask
| #define SDH_INTSTS_BLKDIF_Pos (0) |
SDH_T::INTSTS: BLKDIF Position
| #define SDH_INTSTS_CDIF_Msk (0x1ul << SDH_INTSTS_CDIF_Pos) |
SDH_T::INTSTS: CDIF Mask
| #define SDH_INTSTS_CDIF_Pos (8) |
SDH_T::INTSTS: CDIF Position
| #define SDH_INTSTS_CDSTS_Msk (0x1ul << SDH_INTSTS_CDSTS_Pos) |
SDH_T::INTSTS: CDSTS Mask
| #define SDH_INTSTS_CDSTS_Pos (16) |
SDH_T::INTSTS: CDSTS Position
| #define SDH_INTSTS_CRC16_Msk (0x1ul << SDH_INTSTS_CRC16_Pos) |
SDH_T::INTSTS: CRC16 Mask
| #define SDH_INTSTS_CRC16_Pos (3) |
SDH_T::INTSTS: CRC16 Position
| #define SDH_INTSTS_CRC7_Msk (0x1ul << SDH_INTSTS_CRC7_Pos) |
SDH_T::INTSTS: CRC7 Mask
| #define SDH_INTSTS_CRC7_Pos (2) |
SDH_T::INTSTS: CRC7 Position
| #define SDH_INTSTS_CRCIF_Msk (0x1ul << SDH_INTSTS_CRCIF_Pos) |
SDH_T::INTSTS: CRCIF Mask
| #define SDH_INTSTS_CRCIF_Pos (1) |
SDH_T::INTSTS: CRCIF Position
| #define SDH_INTSTS_CRCSTS_Msk (0x7ul << SDH_INTSTS_CRCSTS_Pos) |
SDH_T::INTSTS: CRCSTS Mask
| #define SDH_INTSTS_CRCSTS_Pos (4) |
SDH_T::INTSTS: CRCSTS Position
| #define SDH_INTSTS_DAT0STS_Msk (0x1ul << SDH_INTSTS_DAT0STS_Pos) |
SDH_T::INTSTS: DAT0STS Mask
| #define SDH_INTSTS_DAT0STS_Pos (7) |
SDH_T::INTSTS: DAT0STS Position
| #define SDH_INTSTS_DAT1STS_Msk (0x1ul << SDH_INTSTS_DAT1STS_Pos) |
SDH_T::INTSTS: DAT1STS Mask
| #define SDH_INTSTS_DAT1STS_Pos (18) |
SDH_T::INTSTS: DAT1STS Position
| #define SDH_INTSTS_DITOIF_Msk (0x1ul << SDH_INTSTS_DITOIF_Pos) |
SDH_T::INTSTS: DITOIF Mask
| #define SDH_INTSTS_DITOIF_Pos (13) |
SDH_T::INTSTS: DITOIF Position
| #define SDH_INTSTS_RTOIF_Msk (0x1ul << SDH_INTSTS_RTOIF_Pos) |
SDH_T::INTSTS: RTOIF Mask
| #define SDH_INTSTS_RTOIF_Pos (12) |
SDH_T::INTSTS: RTOIF Position
| #define SDH_RESP0_RESPTK0_Msk (0xfffffffful << SDH_RESP0_RESPTK0_Pos) |
SDH_T::RESP0: RESPTK0 Mask
| #define SDH_RESP0_RESPTK0_Pos (0) |
SDH_T::RESP0: RESPTK0 Position
| #define SDH_RESP1_RESPTK1_Msk (0xfful << SDH_RESP1_RESPTK1_Pos) |
SDH_T::RESP1: RESPTK1 Mask
| #define SDH_RESP1_RESPTK1_Pos (0) |
SDH_T::RESP1: RESPTK1 Position
| #define SDH_TOUT_TOUT_Msk (0xfffffful << SDH_TOUT_TOUT_Pos) |
SDH_T::TOUT: TOUT Mask
| #define SDH_TOUT_TOUT_Pos (0) |
SDH_T::TOUT: TOUT Position
| #define SPI_CLKDIV_DIVIDER_Msk (0x1fful << SPI_CLKDIV_DIVIDER_Pos) |
SPI_T::CLKDIV: DIVIDER Mask
| #define SPI_CLKDIV_DIVIDER_Pos (0) |
SPI_T::CLKDIV: DIVIDER Position
| #define SPI_CTL_CLKPOL_Msk (0x1ul << SPI_CTL_CLKPOL_Pos) |
SPI_T::CTL: CLKPOL Mask
| #define SPI_CTL_CLKPOL_Pos (3) |
SPI_T::CTL: CLKPOL Position
| #define SPI_CTL_DATDIR_Msk (0x1ul << SPI_CTL_DATDIR_Pos) |
SPI_T::CTL: DATDIR Mask
| #define SPI_CTL_DATDIR_Pos (20) |
SPI_T::CTL: DATDIR Position
| #define SPI_CTL_DWIDTH_Msk (0x1ful << SPI_CTL_DWIDTH_Pos) |
SPI_T::CTL: DWIDTH Mask
| #define SPI_CTL_DWIDTH_Pos (8) |
SPI_T::CTL: DWIDTH Position
| #define SPI_CTL_HALFDPX_Msk (0x1ul << SPI_CTL_HALFDPX_Pos) |
SPI_T::CTL: HALFDPX Mask
| #define SPI_CTL_HALFDPX_Pos (14) |
SPI_T::CTL: HALFDPX Position
| #define SPI_CTL_LSB_Msk (0x1ul << SPI_CTL_LSB_Pos) |
SPI_T::CTL: LSB Mask
| #define SPI_CTL_LSB_Pos (13) |
SPI_T::CTL: LSB Position
| #define SPI_CTL_REORDER_Msk (0x1ul << SPI_CTL_REORDER_Pos) |
SPI_T::CTL: REORDER Mask
| #define SPI_CTL_REORDER_Pos (19) |
SPI_T::CTL: REORDER Position
| #define SPI_CTL_RXNEG_Msk (0x1ul << SPI_CTL_RXNEG_Pos) |
SPI_T::CTL: RXNEG Mask
| #define SPI_CTL_RXNEG_Pos (1) |
SPI_T::CTL: RXNEG Position
| #define SPI_CTL_RXONLY_Msk (0x1ul << SPI_CTL_RXONLY_Pos) |
SPI_T::CTL: RXONLY Mask
| #define SPI_CTL_RXONLY_Pos (15) |
SPI_T::CTL: RXONLY Position
| #define SPI_CTL_SLAVE_Msk (0x1ul << SPI_CTL_SLAVE_Pos) |
SPI_T::CTL: SLAVE Mask
| #define SPI_CTL_SLAVE_Pos (18) |
SPI_T::CTL: SLAVE Position
| #define SPI_CTL_SPIEN_Msk (0x1ul << SPI_CTL_SPIEN_Pos) |
SPI_T::CTL: SPIEN Mask
| #define SPI_CTL_SPIEN_Pos (0) |
@addtogroup SPI_CONST SPI Bit Field Definition Constant Definitions for SPI Controller
SPI_T::CTL: SPIEN Position
| #define SPI_CTL_SUSPITV_Msk (0xful << SPI_CTL_SUSPITV_Pos) |
SPI_T::CTL: SUSPITV Mask
| #define SPI_CTL_SUSPITV_Pos (4) |
SPI_T::CTL: SUSPITV Position
| #define SPI_CTL_TXNEG_Msk (0x1ul << SPI_CTL_TXNEG_Pos) |
SPI_T::CTL: TXNEG Mask
| #define SPI_CTL_TXNEG_Pos (2) |
SPI_T::CTL: TXNEG Position
| #define SPI_CTL_UNITIEN_Msk (0x1ul << SPI_CTL_UNITIEN_Pos) |
SPI_T::CTL: UNITIEN Mask
| #define SPI_CTL_UNITIEN_Pos (17) |
SPI_T::CTL: UNITIEN Position
| #define SPI_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI_FIFOCTL_RXFBCLR_Pos) |
SPI_T::FIFOCTL: RXFBCLR Mask
| #define SPI_FIFOCTL_RXFBCLR_Pos (8) |
SPI_T::FIFOCTL: RXFBCLR Position
| #define SPI_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI_FIFOCTL_RXOVIEN_Pos) |
SPI_T::FIFOCTL: RXOVIEN Mask
| #define SPI_FIFOCTL_RXOVIEN_Pos (5) |
SPI_T::FIFOCTL: RXOVIEN Position
| #define SPI_FIFOCTL_RXRST_Msk (0x1ul << SPI_FIFOCTL_RXRST_Pos) |
SPI_T::FIFOCTL: RXRST Mask
| #define SPI_FIFOCTL_RXRST_Pos (0) |
SPI_T::FIFOCTL: RXRST Position
| #define SPI_FIFOCTL_RXTH_Msk (0x7ul << SPI_FIFOCTL_RXTH_Pos) |
SPI_T::FIFOCTL: RXTH Mask
| #define SPI_FIFOCTL_RXTH_Pos (24) |
SPI_T::FIFOCTL: RXTH Position
| #define SPI_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI_FIFOCTL_RXTHIEN_Pos) |
SPI_T::FIFOCTL: RXTHIEN Mask
| #define SPI_FIFOCTL_RXTHIEN_Pos (2) |
SPI_T::FIFOCTL: RXTHIEN Position
| #define SPI_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI_FIFOCTL_RXTOIEN_Pos) |
SPI_T::FIFOCTL: RXTOIEN Mask
| #define SPI_FIFOCTL_RXTOIEN_Pos (4) |
SPI_T::FIFOCTL: RXTOIEN Position
| #define SPI_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI_FIFOCTL_TXFBCLR_Pos) |
SPI_T::FIFOCTL: TXFBCLR Mask
| #define SPI_FIFOCTL_TXFBCLR_Pos (9) |
SPI_T::FIFOCTL: TXFBCLR Position
| #define SPI_FIFOCTL_TXRST_Msk (0x1ul << SPI_FIFOCTL_TXRST_Pos) |
SPI_T::FIFOCTL: TXRST Mask
| #define SPI_FIFOCTL_TXRST_Pos (1) |
SPI_T::FIFOCTL: TXRST Position
| #define SPI_FIFOCTL_TXTH_Msk (0x7ul << SPI_FIFOCTL_TXTH_Pos) |
SPI_T::FIFOCTL: TXTH Mask
| #define SPI_FIFOCTL_TXTH_Pos (28) |
SPI_T::FIFOCTL: TXTH Position
| #define SPI_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI_FIFOCTL_TXTHIEN_Pos) |
SPI_T::FIFOCTL: TXTHIEN Mask
| #define SPI_FIFOCTL_TXTHIEN_Pos (3) |
SPI_T::FIFOCTL: TXTHIEN Position
| #define SPI_FIFOCTL_TXUFIEN_Msk (0x1ul << SPI_FIFOCTL_TXUFIEN_Pos) |
SPI_T::FIFOCTL: TXUFIEN Mask
| #define SPI_FIFOCTL_TXUFIEN_Pos (7) |
SPI_T::FIFOCTL: TXUFIEN Position
| #define SPI_FIFOCTL_TXUFPOL_Msk (0x1ul << SPI_FIFOCTL_TXUFPOL_Pos) |
SPI_T::FIFOCTL: TXUFPOL Mask
| #define SPI_FIFOCTL_TXUFPOL_Pos (6) |
SPI_T::FIFOCTL: TXUFPOL Position
| #define SPI_I2SCLK_BCLKDIV_Msk (0x3fful << SPI_I2SCLK_BCLKDIV_Pos) |
SPI_T::I2SCLK: BCLKDIV Mask
| #define SPI_I2SCLK_BCLKDIV_Pos (8) |
SPI_T::I2SCLK: BCLKDIV Position
| #define SPI_I2SCLK_MCLKDIV_Msk (0x7ful << SPI_I2SCLK_MCLKDIV_Pos) |
SPI_T::I2SCLK: MCLKDIV Mask
| #define SPI_I2SCLK_MCLKDIV_Pos (0) |
SPI_T::I2SCLK: MCLKDIV Position
| #define SPI_I2SCTL_FORMAT_Msk (0x3ul << SPI_I2SCTL_FORMAT_Pos) |
SPI_T::I2SCTL: FORMAT Mask
| #define SPI_I2SCTL_FORMAT_Pos (28) |
SPI_T::I2SCTL: FORMAT Position
| #define SPI_I2SCTL_I2SEN_Msk (0x1ul << SPI_I2SCTL_I2SEN_Pos) |
SPI_T::I2SCTL: I2SEN Mask
| #define SPI_I2SCTL_I2SEN_Pos (0) |
SPI_T::I2SCTL: I2SEN Position
| #define SPI_I2SCTL_LZCEN_Msk (0x1ul << SPI_I2SCTL_LZCEN_Pos) |
SPI_T::I2SCTL: LZCEN Mask
| #define SPI_I2SCTL_LZCEN_Pos (17) |
SPI_T::I2SCTL: LZCEN Position
| #define SPI_I2SCTL_LZCIEN_Msk (0x1ul << SPI_I2SCTL_LZCIEN_Pos) |
SPI_T::I2SCTL: LZCIEN Mask
| #define SPI_I2SCTL_LZCIEN_Pos (25) |
SPI_T::I2SCTL: LZCIEN Position
| #define SPI_I2SCTL_MCLKEN_Msk (0x1ul << SPI_I2SCTL_MCLKEN_Pos) |
SPI_T::I2SCTL: MCLKEN Mask
| #define SPI_I2SCTL_MCLKEN_Pos (15) |
SPI_T::I2SCTL: MCLKEN Position
| #define SPI_I2SCTL_MONO_Msk (0x1ul << SPI_I2SCTL_MONO_Pos) |
SPI_T::I2SCTL: MONO Mask
| #define SPI_I2SCTL_MONO_Pos (6) |
SPI_T::I2SCTL: MONO Position
| #define SPI_I2SCTL_MUTE_Msk (0x1ul << SPI_I2SCTL_MUTE_Pos) |
SPI_T::I2SCTL: MUTE Mask
| #define SPI_I2SCTL_MUTE_Pos (3) |
SPI_T::I2SCTL: MUTE Position
| #define SPI_I2SCTL_ORDER_Msk (0x1ul << SPI_I2SCTL_ORDER_Pos) |
SPI_T::I2SCTL: ORDER Mask
| #define SPI_I2SCTL_ORDER_Pos (7) |
SPI_T::I2SCTL: ORDER Position
| #define SPI_I2SCTL_RXEN_Msk (0x1ul << SPI_I2SCTL_RXEN_Pos) |
SPI_T::I2SCTL: RXEN Mask
| #define SPI_I2SCTL_RXEN_Pos (2) |
SPI_T::I2SCTL: RXEN Position
| #define SPI_I2SCTL_RXLCH_Msk (0x1ul << SPI_I2SCTL_RXLCH_Pos) |
SPI_T::I2SCTL: RXLCH Mask
| #define SPI_I2SCTL_RXLCH_Pos (23) |
SPI_T::I2SCTL: RXLCH Position
| #define SPI_I2SCTL_RZCEN_Msk (0x1ul << SPI_I2SCTL_RZCEN_Pos) |
SPI_T::I2SCTL: RZCEN Mask
| #define SPI_I2SCTL_RZCEN_Pos (16) |
SPI_T::I2SCTL: RZCEN Position
| #define SPI_I2SCTL_RZCIEN_Msk (0x1ul << SPI_I2SCTL_RZCIEN_Pos) |
SPI_T::I2SCTL: RZCIEN Mask
| #define SPI_I2SCTL_RZCIEN_Pos (24) |
SPI_T::I2SCTL: RZCIEN Position
| #define SPI_I2SCTL_SLAVE_Msk (0x1ul << SPI_I2SCTL_SLAVE_Pos) |
SPI_T::I2SCTL: SLAVE Mask
| #define SPI_I2SCTL_SLAVE_Pos (8) |
SPI_T::I2SCTL: SLAVE Position
| #define SPI_I2SCTL_TXEN_Msk (0x1ul << SPI_I2SCTL_TXEN_Pos) |
SPI_T::I2SCTL: TXEN Mask
| #define SPI_I2SCTL_TXEN_Pos (1) |
SPI_T::I2SCTL: TXEN Position
| #define SPI_I2SCTL_WDWIDTH_Msk (0x3ul << SPI_I2SCTL_WDWIDTH_Pos) |
SPI_T::I2SCTL: WDWIDTH Mask
| #define SPI_I2SCTL_WDWIDTH_Pos (4) |
SPI_T::I2SCTL: WDWIDTH Position
| #define SPI_I2SSTS_I2SENSTS_Msk (0x1ul << SPI_I2SSTS_I2SENSTS_Pos) |
SPI_T::I2SSTS: I2SENSTS Mask
| #define SPI_I2SSTS_I2SENSTS_Pos (15) |
SPI_T::I2SSTS: I2SENSTS Position
| #define SPI_I2SSTS_LZCIF_Msk (0x1ul << SPI_I2SSTS_LZCIF_Pos) |
SPI_T::I2SSTS: LZCIF Mask
| #define SPI_I2SSTS_LZCIF_Pos (21) |
SPI_T::I2SSTS: LZCIF Position
| #define SPI_I2SSTS_RIGHT_Msk (0x1ul << SPI_I2SSTS_RIGHT_Pos) |
SPI_T::I2SSTS: RIGHT Mask
| #define SPI_I2SSTS_RIGHT_Pos (4) |
SPI_T::I2SSTS: RIGHT Position
| #define SPI_I2SSTS_RXCNT_Msk (0x7ul << SPI_I2SSTS_RXCNT_Pos) |
SPI_T::I2SSTS: RXCNT Mask
| #define SPI_I2SSTS_RXCNT_Pos (24) |
SPI_T::I2SSTS: RXCNT Position
| #define SPI_I2SSTS_RXEMPTY_Msk (0x1ul << SPI_I2SSTS_RXEMPTY_Pos) |
SPI_T::I2SSTS: RXEMPTY Mask
| #define SPI_I2SSTS_RXEMPTY_Pos (8) |
SPI_T::I2SSTS: RXEMPTY Position
| #define SPI_I2SSTS_RXFULL_Msk (0x1ul << SPI_I2SSTS_RXFULL_Pos) |
SPI_T::I2SSTS: RXFULL Mask
| #define SPI_I2SSTS_RXFULL_Pos (9) |
SPI_T::I2SSTS: RXFULL Position
| #define SPI_I2SSTS_RXOVIF_Msk (0x1ul << SPI_I2SSTS_RXOVIF_Pos) |
SPI_T::I2SSTS: RXOVIF Mask
| #define SPI_I2SSTS_RXOVIF_Pos (11) |
SPI_T::I2SSTS: RXOVIF Position
| #define SPI_I2SSTS_RXTHIF_Msk (0x1ul << SPI_I2SSTS_RXTHIF_Pos) |
SPI_T::I2SSTS: RXTHIF Mask
| #define SPI_I2SSTS_RXTHIF_Pos (10) |
SPI_T::I2SSTS: RXTHIF Position
| #define SPI_I2SSTS_RXTOIF_Msk (0x1ul << SPI_I2SSTS_RXTOIF_Pos) |
SPI_T::I2SSTS: RXTOIF Mask
| #define SPI_I2SSTS_RXTOIF_Pos (12) |
SPI_T::I2SSTS: RXTOIF Position
| #define SPI_I2SSTS_RZCIF_Msk (0x1ul << SPI_I2SSTS_RZCIF_Pos) |
SPI_T::I2SSTS: RZCIF Mask
| #define SPI_I2SSTS_RZCIF_Pos (20) |
SPI_T::I2SSTS: RZCIF Position
| #define SPI_I2SSTS_TXCNT_Msk (0x7ul << SPI_I2SSTS_TXCNT_Pos) |
SPI_T::I2SSTS: TXCNT Mask
| #define SPI_I2SSTS_TXCNT_Pos (28) |
SPI_T::I2SSTS: TXCNT Position
| #define SPI_I2SSTS_TXEMPTY_Msk (0x1ul << SPI_I2SSTS_TXEMPTY_Pos) |
SPI_T::I2SSTS: TXEMPTY Mask
| #define SPI_I2SSTS_TXEMPTY_Pos (16) |
SPI_T::I2SSTS: TXEMPTY Position
| #define SPI_I2SSTS_TXFULL_Msk (0x1ul << SPI_I2SSTS_TXFULL_Pos) |
SPI_T::I2SSTS: TXFULL Mask
| #define SPI_I2SSTS_TXFULL_Pos (17) |
SPI_T::I2SSTS: TXFULL Position
| #define SPI_I2SSTS_TXRXRST_Msk (0x1ul << SPI_I2SSTS_TXRXRST_Pos) |
SPI_T::I2SSTS: TXRXRST Mask
| #define SPI_I2SSTS_TXRXRST_Pos (23) |
SPI_T::I2SSTS: TXRXRST Position
| #define SPI_I2SSTS_TXTHIF_Msk (0x1ul << SPI_I2SSTS_TXTHIF_Pos) |
SPI_T::I2SSTS: TXTHIF Mask
| #define SPI_I2SSTS_TXTHIF_Pos (18) |
SPI_T::I2SSTS: TXTHIF Position
| #define SPI_I2SSTS_TXUFIF_Msk (0x1ul << SPI_I2SSTS_TXUFIF_Pos) |
SPI_T::I2SSTS: TXUFIF Mask
| #define SPI_I2SSTS_TXUFIF_Pos (19) |
SPI_T::I2SSTS: TXUFIF Position
| #define SPI_PDMACTL_PDMARST_Msk (0x1ul << SPI_PDMACTL_PDMARST_Pos) |
SPI_T::PDMACTL: PDMARST Mask
| #define SPI_PDMACTL_PDMARST_Pos (2) |
SPI_T::PDMACTL: PDMARST Position
| #define SPI_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI_PDMACTL_RXPDMAEN_Pos) |
SPI_T::PDMACTL: RXPDMAEN Mask
| #define SPI_PDMACTL_RXPDMAEN_Pos (1) |
SPI_T::PDMACTL: RXPDMAEN Position
| #define SPI_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI_PDMACTL_TXPDMAEN_Pos) |
SPI_T::PDMACTL: TXPDMAEN Mask
| #define SPI_PDMACTL_TXPDMAEN_Pos (0) |
SPI_T::PDMACTL: TXPDMAEN Position
| #define SPI_RX_RX_Msk (0xfffffffful << SPI_RX_RX_Pos) |
| #define SPI_SSCTL_AUTOSS_Msk (0x1ul << SPI_SSCTL_AUTOSS_Pos) |
SPI_T::SSCTL: AUTOSS Mask
| #define SPI_SSCTL_AUTOSS_Pos (3) |
SPI_T::SSCTL: AUTOSS Position
| #define SPI_SSCTL_SLVBEIEN_Msk (0x1ul << SPI_SSCTL_SLVBEIEN_Pos) |
SPI_T::SSCTL: SLVBEIEN Mask
| #define SPI_SSCTL_SLVBEIEN_Pos (8) |
SPI_T::SSCTL: SLVBEIEN Position
| #define SPI_SSCTL_SLVTOCNT_Msk (0xfffful << SPI_SSCTL_SLVTOCNT_Pos) |
SPI_T::SSCTL: SLVTOCNT Mask
| #define SPI_SSCTL_SLVTOCNT_Pos (16) |
SPI_T::SSCTL: SLVTOCNT Position
| #define SPI_SSCTL_SLVURIEN_Msk (0x1ul << SPI_SSCTL_SLVURIEN_Pos) |
SPI_T::SSCTL: SLVURIEN Mask
| #define SPI_SSCTL_SLVURIEN_Pos (9) |
SPI_T::SSCTL: SLVURIEN Position
| #define SPI_SSCTL_SS_Msk (0x1ul << SPI_SSCTL_SS_Pos) |
SPI_T::SSCTL: SS Mask
| #define SPI_SSCTL_SS_Pos (0) |
SPI_T::SSCTL: SS Position
| #define SPI_SSCTL_SSACTIEN_Msk (0x1ul << SPI_SSCTL_SSACTIEN_Pos) |
SPI_T::SSCTL: SSACTIEN Mask
| #define SPI_SSCTL_SSACTIEN_Pos (12) |
SPI_T::SSCTL: SSACTIEN Position
| #define SPI_SSCTL_SSACTPOL_Msk (0x1ul << SPI_SSCTL_SSACTPOL_Pos) |
SPI_T::SSCTL: SSACTPOL Mask
| #define SPI_SSCTL_SSACTPOL_Pos (2) |
SPI_T::SSCTL: SSACTPOL Position
| #define SPI_SSCTL_SSINAIEN_Msk (0x1ul << SPI_SSCTL_SSINAIEN_Pos) |
SPI_T::SSCTL: SSINAIEN Mask
| #define SPI_SSCTL_SSINAIEN_Pos (13) |
SPI_T::SSCTL: SSINAIEN Position
| #define SPI_STATUS_BUSY_Msk (0x1ul << SPI_STATUS_BUSY_Pos) |
SPI_T::STATUS: BUSY Mask
| #define SPI_STATUS_BUSY_Pos (0) |
SPI_T::STATUS: BUSY Position
| #define SPI_STATUS_RXCNT_Msk (0xful << SPI_STATUS_RXCNT_Pos) |
SPI_T::STATUS: RXCNT Mask
| #define SPI_STATUS_RXCNT_Pos (24) |
SPI_T::STATUS: RXCNT Position
| #define SPI_STATUS_RXEMPTY_Msk (0x1ul << SPI_STATUS_RXEMPTY_Pos) |
SPI_T::STATUS: RXEMPTY Mask
| #define SPI_STATUS_RXEMPTY_Pos (8) |
SPI_T::STATUS: RXEMPTY Position
| #define SPI_STATUS_RXFULL_Msk (0x1ul << SPI_STATUS_RXFULL_Pos) |
SPI_T::STATUS: RXFULL Mask
| #define SPI_STATUS_RXFULL_Pos (9) |
SPI_T::STATUS: RXFULL Position
| #define SPI_STATUS_RXOVIF_Msk (0x1ul << SPI_STATUS_RXOVIF_Pos) |
SPI_T::STATUS: RXOVIF Mask
| #define SPI_STATUS_RXOVIF_Pos (11) |
SPI_T::STATUS: RXOVIF Position
| #define SPI_STATUS_RXTHIF_Msk (0x1ul << SPI_STATUS_RXTHIF_Pos) |
SPI_T::STATUS: RXTHIF Mask
| #define SPI_STATUS_RXTHIF_Pos (10) |
SPI_T::STATUS: RXTHIF Position
| #define SPI_STATUS_RXTOIF_Msk (0x1ul << SPI_STATUS_RXTOIF_Pos) |
SPI_T::STATUS: RXTOIF Mask
| #define SPI_STATUS_RXTOIF_Pos (12) |
SPI_T::STATUS: RXTOIF Position
| #define SPI_STATUS_SLVBEIF_Msk (0x1ul << SPI_STATUS_SLVBEIF_Pos) |
SPI_T::STATUS: SLVBEIF Mask
| #define SPI_STATUS_SLVBEIF_Pos (6) |
SPI_T::STATUS: SLVBEIF Position
| #define SPI_STATUS_SLVURIF_Msk (0x1ul << SPI_STATUS_SLVURIF_Pos) |
SPI_T::STATUS: SLVURIF Mask
| #define SPI_STATUS_SLVURIF_Pos (7) |
SPI_T::STATUS: SLVURIF Position
| #define SPI_STATUS_SPIENSTS_Msk (0x1ul << SPI_STATUS_SPIENSTS_Pos) |
SPI_T::STATUS: SPIENSTS Mask
| #define SPI_STATUS_SPIENSTS_Pos (15) |
SPI_T::STATUS: SPIENSTS Position
| #define SPI_STATUS_SSACTIF_Msk (0x1ul << SPI_STATUS_SSACTIF_Pos) |
SPI_T::STATUS: SSACTIF Mask
| #define SPI_STATUS_SSACTIF_Pos (2) |
SPI_T::STATUS: SSACTIF Position
| #define SPI_STATUS_SSINAIF_Msk (0x1ul << SPI_STATUS_SSINAIF_Pos) |
SPI_T::STATUS: SSINAIF Mask
| #define SPI_STATUS_SSINAIF_Pos (3) |
SPI_T::STATUS: SSINAIF Position
| #define SPI_STATUS_SSLINE_Msk (0x1ul << SPI_STATUS_SSLINE_Pos) |
SPI_T::STATUS: SSLINE Mask
| #define SPI_STATUS_SSLINE_Pos (4) |
SPI_T::STATUS: SSLINE Position
| #define SPI_STATUS_TXCNT_Msk (0xful << SPI_STATUS_TXCNT_Pos) |
SPI_T::STATUS: TXCNT Mask
| #define SPI_STATUS_TXCNT_Pos (28) |
SPI_T::STATUS: TXCNT Position
| #define SPI_STATUS_TXEMPTY_Msk (0x1ul << SPI_STATUS_TXEMPTY_Pos) |
SPI_T::STATUS: TXEMPTY Mask
| #define SPI_STATUS_TXEMPTY_Pos (16) |
SPI_T::STATUS: TXEMPTY Position
| #define SPI_STATUS_TXFULL_Msk (0x1ul << SPI_STATUS_TXFULL_Pos) |
SPI_T::STATUS: TXFULL Mask
| #define SPI_STATUS_TXFULL_Pos (17) |
SPI_T::STATUS: TXFULL Position
| #define SPI_STATUS_TXRXRST_Msk (0x1ul << SPI_STATUS_TXRXRST_Pos) |
SPI_T::STATUS: TXRXRST Mask
| #define SPI_STATUS_TXRXRST_Pos (23) |
SPI_T::STATUS: TXRXRST Position
| #define SPI_STATUS_TXTHIF_Msk (0x1ul << SPI_STATUS_TXTHIF_Pos) |
SPI_T::STATUS: TXTHIF Mask
| #define SPI_STATUS_TXTHIF_Pos (18) |
SPI_T::STATUS: TXTHIF Position
| #define SPI_STATUS_TXUFIF_Msk (0x1ul << SPI_STATUS_TXUFIF_Pos) |
SPI_T::STATUS: TXUFIF Mask
| #define SPI_STATUS_TXUFIF_Pos (19) |
SPI_T::STATUS: TXUFIF Position
| #define SPI_STATUS_UNITIF_Msk (0x1ul << SPI_STATUS_UNITIF_Pos) |
SPI_T::STATUS: UNITIF Mask
| #define SPI_STATUS_UNITIF_Pos (1) |
SPI_T::STATUS: UNITIF Position
| #define SPI_TX_TX_Msk (0xfffffffful << SPI_TX_TX_Pos) |
| #define SYS_AHBMCTL_INTACTEN_Msk (0x1ul << SYS_AHBMCTL_INTACTEN_Pos) |
SYS_T::AHBMCTL: INTACTEN Mask
| #define SYS_AHBMCTL_INTACTEN_Pos (0) |
SYS_T::AHBMCTL: INTACTEN Position
| #define SYS_BODCTL_BODDGSEL_Msk (0x7ul << SYS_BODCTL_BODDGSEL_Pos) |
SYS_T::BODCTL: BODDGSEL Mask
| #define SYS_BODCTL_BODDGSEL_Pos (8) |
SYS_T::BODCTL: BODDGSEL Position
| #define SYS_BODCTL_BODEN_Msk (0x1ul << SYS_BODCTL_BODEN_Pos) |
SYS_T::BODCTL: BODEN Mask
| #define SYS_BODCTL_BODEN_Pos (0) |
SYS_T::BODCTL: BODEN Position
| #define SYS_BODCTL_BODIF_Msk (0x1ul << SYS_BODCTL_BODIF_Pos) |
SYS_T::BODCTL: BODIF Mask
| #define SYS_BODCTL_BODIF_Pos (4) |
SYS_T::BODCTL: BODIF Position
| #define SYS_BODCTL_BODLPM_Msk (0x1ul << SYS_BODCTL_BODLPM_Pos) |
SYS_T::BODCTL: BODLPM Mask
| #define SYS_BODCTL_BODLPM_Pos (5) |
SYS_T::BODCTL: BODLPM Position
| #define SYS_BODCTL_BODOUT_Msk (0x1ul << SYS_BODCTL_BODOUT_Pos) |
SYS_T::BODCTL: BODOUT Mask
| #define SYS_BODCTL_BODOUT_Pos (6) |
SYS_T::BODCTL: BODOUT Position
| #define SYS_BODCTL_BODRSTEN_Msk (0x1ul << SYS_BODCTL_BODRSTEN_Pos) |
SYS_T::BODCTL: BODRSTEN Mask
| #define SYS_BODCTL_BODRSTEN_Pos (3) |
SYS_T::BODCTL: BODRSTEN Position
| #define SYS_BODCTL_BODVL_Msk (0x7ul << SYS_BODCTL_BODVL_Pos) |
SYS_T::BODCTL: BODVL Mask
| #define SYS_BODCTL_BODVL_Pos (16) |
SYS_T::BODCTL: BODVL Position
| #define SYS_BODCTL_LVRDGSEL_Msk (0x7ul << SYS_BODCTL_LVRDGSEL_Pos) |
SYS_T::BODCTL: LVRDGSEL Mask
| #define SYS_BODCTL_LVRDGSEL_Pos (12) |
SYS_T::BODCTL: LVRDGSEL Position
| #define SYS_BODCTL_LVREN_Msk (0x1ul << SYS_BODCTL_LVREN_Pos) |
SYS_T::BODCTL: LVREN Mask
| #define SYS_BODCTL_LVREN_Pos (7) |
SYS_T::BODCTL: LVREN Position
| #define SYS_CSERVER_VERSION_Msk (0xfful << SYS_CSERVER_VERSION_Pos) |
SYS_T::CSERVER: VERSION Mask
| #define SYS_CSERVER_VERSION_Pos (0) |
SYS_T::CSERVER: VERSION Position
| #define SYS_GPA_MFOS_MFOS0_Msk (0x1ul << SYS_GPA_MFOS_MFOS0_Pos) |
SYS_T::GPA_MFOS: MFOS0 Mask
| #define SYS_GPA_MFOS_MFOS0_Pos (0) |
SYS_T::GPA_MFOS: MFOS0 Position
| #define SYS_GPA_MFOS_MFOS10_Msk (0x1ul << SYS_GPA_MFOS_MFOS10_Pos) |
SYS_T::GPA_MFOS: MFOS10 Mask
| #define SYS_GPA_MFOS_MFOS10_Pos (10) |
SYS_T::GPA_MFOS: MFOS10 Position
| #define SYS_GPA_MFOS_MFOS11_Msk (0x1ul << SYS_GPA_MFOS_MFOS11_Pos) |
SYS_T::GPA_MFOS: MFOS11 Mask
| #define SYS_GPA_MFOS_MFOS11_Pos (11) |
SYS_T::GPA_MFOS: MFOS11 Position
| #define SYS_GPA_MFOS_MFOS12_Msk (0x1ul << SYS_GPA_MFOS_MFOS12_Pos) |
SYS_T::GPA_MFOS: MFOS12 Mask
| #define SYS_GPA_MFOS_MFOS12_Pos (12) |
SYS_T::GPA_MFOS: MFOS12 Position
| #define SYS_GPA_MFOS_MFOS13_Msk (0x1ul << SYS_GPA_MFOS_MFOS13_Pos) |
SYS_T::GPA_MFOS: MFOS13 Mask
| #define SYS_GPA_MFOS_MFOS13_Pos (13) |
SYS_T::GPA_MFOS: MFOS13 Position
| #define SYS_GPA_MFOS_MFOS14_Msk (0x1ul << SYS_GPA_MFOS_MFOS14_Pos) |
SYS_T::GPA_MFOS: MFOS14 Mask
| #define SYS_GPA_MFOS_MFOS14_Pos (14) |
SYS_T::GPA_MFOS: MFOS14 Position
| #define SYS_GPA_MFOS_MFOS15_Msk (0x1ul << SYS_GPA_MFOS_MFOS15_Pos) |
SYS_T::GPA_MFOS: MFOS15 Mask
| #define SYS_GPA_MFOS_MFOS15_Pos (15) |
SYS_T::GPA_MFOS: MFOS15 Position
| #define SYS_GPA_MFOS_MFOS1_Msk (0x1ul << SYS_GPA_MFOS_MFOS1_Pos) |
SYS_T::GPA_MFOS: MFOS1 Mask
| #define SYS_GPA_MFOS_MFOS1_Pos (1) |
SYS_T::GPA_MFOS: MFOS1 Position
| #define SYS_GPA_MFOS_MFOS2_Msk (0x1ul << SYS_GPA_MFOS_MFOS2_Pos) |
SYS_T::GPA_MFOS: MFOS2 Mask
| #define SYS_GPA_MFOS_MFOS2_Pos (2) |
SYS_T::GPA_MFOS: MFOS2 Position
| #define SYS_GPA_MFOS_MFOS3_Msk (0x1ul << SYS_GPA_MFOS_MFOS3_Pos) |
SYS_T::GPA_MFOS: MFOS3 Mask
| #define SYS_GPA_MFOS_MFOS3_Pos (3) |
SYS_T::GPA_MFOS: MFOS3 Position
| #define SYS_GPA_MFOS_MFOS4_Msk (0x1ul << SYS_GPA_MFOS_MFOS4_Pos) |
SYS_T::GPA_MFOS: MFOS4 Mask
| #define SYS_GPA_MFOS_MFOS4_Pos (4) |
SYS_T::GPA_MFOS: MFOS4 Position
| #define SYS_GPA_MFOS_MFOS5_Msk (0x1ul << SYS_GPA_MFOS_MFOS5_Pos) |
SYS_T::GPA_MFOS: MFOS5 Mask
| #define SYS_GPA_MFOS_MFOS5_Pos (5) |
SYS_T::GPA_MFOS: MFOS5 Position
| #define SYS_GPA_MFOS_MFOS6_Msk (0x1ul << SYS_GPA_MFOS_MFOS6_Pos) |
SYS_T::GPA_MFOS: MFOS6 Mask
| #define SYS_GPA_MFOS_MFOS6_Pos (6) |
SYS_T::GPA_MFOS: MFOS6 Position
| #define SYS_GPA_MFOS_MFOS7_Msk (0x1ul << SYS_GPA_MFOS_MFOS7_Pos) |
SYS_T::GPA_MFOS: MFOS7 Mask
| #define SYS_GPA_MFOS_MFOS7_Pos (7) |
SYS_T::GPA_MFOS: MFOS7 Position
| #define SYS_GPA_MFOS_MFOS8_Msk (0x1ul << SYS_GPA_MFOS_MFOS8_Pos) |
SYS_T::GPA_MFOS: MFOS8 Mask
| #define SYS_GPA_MFOS_MFOS8_Pos (8) |
SYS_T::GPA_MFOS: MFOS8 Position
| #define SYS_GPA_MFOS_MFOS9_Msk (0x1ul << SYS_GPA_MFOS_MFOS9_Pos) |
SYS_T::GPA_MFOS: MFOS9 Mask
| #define SYS_GPA_MFOS_MFOS9_Pos (9) |
SYS_T::GPA_MFOS: MFOS9 Position
| #define SYS_GPA_MFPH_PA10MFP_Msk (0xful << SYS_GPA_MFPH_PA10MFP_Pos) |
SYS_T::GPA_MFPH: PA10MFP Mask
| #define SYS_GPA_MFPH_PA10MFP_Pos (8) |
SYS_T::GPA_MFPH: PA10MFP Position
| #define SYS_GPA_MFPH_PA11MFP_Msk (0xful << SYS_GPA_MFPH_PA11MFP_Pos) |
SYS_T::GPA_MFPH: PA11MFP Mask
| #define SYS_GPA_MFPH_PA11MFP_Pos (12) |
SYS_T::GPA_MFPH: PA11MFP Position
| #define SYS_GPA_MFPH_PA12MFP_Msk (0xful << SYS_GPA_MFPH_PA12MFP_Pos) |
SYS_T::GPA_MFPH: PA12MFP Mask
| #define SYS_GPA_MFPH_PA12MFP_Pos (16) |
SYS_T::GPA_MFPH: PA12MFP Position
| #define SYS_GPA_MFPH_PA13MFP_Msk (0xful << SYS_GPA_MFPH_PA13MFP_Pos) |
SYS_T::GPA_MFPH: PA13MFP Mask
| #define SYS_GPA_MFPH_PA13MFP_Pos (20) |
SYS_T::GPA_MFPH: PA13MFP Position
| #define SYS_GPA_MFPH_PA14MFP_Msk (0xful << SYS_GPA_MFPH_PA14MFP_Pos) |
SYS_T::GPA_MFPH: PA14MFP Mask
| #define SYS_GPA_MFPH_PA14MFP_Pos (24) |
SYS_T::GPA_MFPH: PA14MFP Position
| #define SYS_GPA_MFPH_PA15MFP_Msk (0xful << SYS_GPA_MFPH_PA15MFP_Pos) |
SYS_T::GPA_MFPH: PA15MFP Mask
| #define SYS_GPA_MFPH_PA15MFP_Pos (28) |
SYS_T::GPA_MFPH: PA15MFP Position
| #define SYS_GPA_MFPH_PA8MFP_Msk (0xful << SYS_GPA_MFPH_PA8MFP_Pos) |
SYS_T::GPA_MFPH: PA8MFP Mask
| #define SYS_GPA_MFPH_PA8MFP_Pos (0) |
SYS_T::GPA_MFPH: PA8MFP Position
| #define SYS_GPA_MFPH_PA9MFP_Msk (0xful << SYS_GPA_MFPH_PA9MFP_Pos) |
SYS_T::GPA_MFPH: PA9MFP Mask
| #define SYS_GPA_MFPH_PA9MFP_Pos (4) |
SYS_T::GPA_MFPH: PA9MFP Position
| #define SYS_GPA_MFPL_PA0MFP_Msk (0xful << SYS_GPA_MFPL_PA0MFP_Pos) |
SYS_T::GPA_MFPL: PA0MFP Mask
| #define SYS_GPA_MFPL_PA0MFP_Pos (0) |
SYS_T::GPA_MFPL: PA0MFP Position
| #define SYS_GPA_MFPL_PA1MFP_Msk (0xful << SYS_GPA_MFPL_PA1MFP_Pos) |
SYS_T::GPA_MFPL: PA1MFP Mask
| #define SYS_GPA_MFPL_PA1MFP_Pos (4) |
SYS_T::GPA_MFPL: PA1MFP Position
| #define SYS_GPA_MFPL_PA2MFP_Msk (0xful << SYS_GPA_MFPL_PA2MFP_Pos) |
SYS_T::GPA_MFPL: PA2MFP Mask
| #define SYS_GPA_MFPL_PA2MFP_Pos (8) |
SYS_T::GPA_MFPL: PA2MFP Position
| #define SYS_GPA_MFPL_PA3MFP_Msk (0xful << SYS_GPA_MFPL_PA3MFP_Pos) |
SYS_T::GPA_MFPL: PA3MFP Mask
| #define SYS_GPA_MFPL_PA3MFP_Pos (12) |
SYS_T::GPA_MFPL: PA3MFP Position
| #define SYS_GPA_MFPL_PA4MFP_Msk (0xful << SYS_GPA_MFPL_PA4MFP_Pos) |
SYS_T::GPA_MFPL: PA4MFP Mask
| #define SYS_GPA_MFPL_PA4MFP_Pos (16) |
SYS_T::GPA_MFPL: PA4MFP Position
| #define SYS_GPA_MFPL_PA5MFP_Msk (0xful << SYS_GPA_MFPL_PA5MFP_Pos) |
SYS_T::GPA_MFPL: PA5MFP Mask
| #define SYS_GPA_MFPL_PA5MFP_Pos (20) |
SYS_T::GPA_MFPL: PA5MFP Position
| #define SYS_GPA_MFPL_PA6MFP_Msk (0xful << SYS_GPA_MFPL_PA6MFP_Pos) |
SYS_T::GPA_MFPL: PA6MFP Mask
| #define SYS_GPA_MFPL_PA6MFP_Pos (24) |
SYS_T::GPA_MFPL: PA6MFP Position
| #define SYS_GPA_MFPL_PA7MFP_Msk (0xful << SYS_GPA_MFPL_PA7MFP_Pos) |
SYS_T::GPA_MFPL: PA7MFP Mask
| #define SYS_GPA_MFPL_PA7MFP_Pos (28) |
SYS_T::GPA_MFPL: PA7MFP Position
| #define SYS_GPB_MFOS_MFOS0_Msk (0x1ul << SYS_GPB_MFOS_MFOS0_Pos) |
SYS_T::GPB_MFOS: MFOS0 Mask
| #define SYS_GPB_MFOS_MFOS0_Pos (0) |
SYS_T::GPB_MFOS: MFOS0 Position
| #define SYS_GPB_MFOS_MFOS10_Msk (0x1ul << SYS_GPB_MFOS_MFOS10_Pos) |
SYS_T::GPB_MFOS: MFOS10 Mask
| #define SYS_GPB_MFOS_MFOS10_Pos (10) |
SYS_T::GPB_MFOS: MFOS10 Position
| #define SYS_GPB_MFOS_MFOS11_Msk (0x1ul << SYS_GPB_MFOS_MFOS11_Pos) |
SYS_T::GPB_MFOS: MFOS11 Mask
| #define SYS_GPB_MFOS_MFOS11_Pos (11) |
SYS_T::GPB_MFOS: MFOS11 Position
| #define SYS_GPB_MFOS_MFOS12_Msk (0x1ul << SYS_GPB_MFOS_MFOS12_Pos) |
SYS_T::GPB_MFOS: MFOS12 Mask
| #define SYS_GPB_MFOS_MFOS12_Pos (12) |
SYS_T::GPB_MFOS: MFOS12 Position
| #define SYS_GPB_MFOS_MFOS13_Msk (0x1ul << SYS_GPB_MFOS_MFOS13_Pos) |
SYS_T::GPB_MFOS: MFOS13 Mask
| #define SYS_GPB_MFOS_MFOS13_Pos (13) |
SYS_T::GPB_MFOS: MFOS13 Position
| #define SYS_GPB_MFOS_MFOS14_Msk (0x1ul << SYS_GPB_MFOS_MFOS14_Pos) |
SYS_T::GPB_MFOS: MFOS14 Mask
| #define SYS_GPB_MFOS_MFOS14_Pos (14) |
SYS_T::GPB_MFOS: MFOS14 Position
| #define SYS_GPB_MFOS_MFOS15_Msk (0x1ul << SYS_GPB_MFOS_MFOS15_Pos) |
SYS_T::GPB_MFOS: MFOS15 Mask
| #define SYS_GPB_MFOS_MFOS15_Pos (15) |
SYS_T::GPB_MFOS: MFOS15 Position
| #define SYS_GPB_MFOS_MFOS1_Msk (0x1ul << SYS_GPB_MFOS_MFOS1_Pos) |
SYS_T::GPB_MFOS: MFOS1 Mask
| #define SYS_GPB_MFOS_MFOS1_Pos (1) |
SYS_T::GPB_MFOS: MFOS1 Position
| #define SYS_GPB_MFOS_MFOS2_Msk (0x1ul << SYS_GPB_MFOS_MFOS2_Pos) |
SYS_T::GPB_MFOS: MFOS2 Mask
| #define SYS_GPB_MFOS_MFOS2_Pos (2) |
SYS_T::GPB_MFOS: MFOS2 Position
| #define SYS_GPB_MFOS_MFOS3_Msk (0x1ul << SYS_GPB_MFOS_MFOS3_Pos) |
SYS_T::GPB_MFOS: MFOS3 Mask
| #define SYS_GPB_MFOS_MFOS3_Pos (3) |
SYS_T::GPB_MFOS: MFOS3 Position
| #define SYS_GPB_MFOS_MFOS4_Msk (0x1ul << SYS_GPB_MFOS_MFOS4_Pos) |
SYS_T::GPB_MFOS: MFOS4 Mask
| #define SYS_GPB_MFOS_MFOS4_Pos (4) |
SYS_T::GPB_MFOS: MFOS4 Position
| #define SYS_GPB_MFOS_MFOS5_Msk (0x1ul << SYS_GPB_MFOS_MFOS5_Pos) |
SYS_T::GPB_MFOS: MFOS5 Mask
| #define SYS_GPB_MFOS_MFOS5_Pos (5) |
SYS_T::GPB_MFOS: MFOS5 Position
| #define SYS_GPB_MFOS_MFOS6_Msk (0x1ul << SYS_GPB_MFOS_MFOS6_Pos) |
SYS_T::GPB_MFOS: MFOS6 Mask
| #define SYS_GPB_MFOS_MFOS6_Pos (6) |
SYS_T::GPB_MFOS: MFOS6 Position
| #define SYS_GPB_MFOS_MFOS7_Msk (0x1ul << SYS_GPB_MFOS_MFOS7_Pos) |
SYS_T::GPB_MFOS: MFOS7 Mask
| #define SYS_GPB_MFOS_MFOS7_Pos (7) |
SYS_T::GPB_MFOS: MFOS7 Position
| #define SYS_GPB_MFOS_MFOS8_Msk (0x1ul << SYS_GPB_MFOS_MFOS8_Pos) |
SYS_T::GPB_MFOS: MFOS8 Mask
| #define SYS_GPB_MFOS_MFOS8_Pos (8) |
SYS_T::GPB_MFOS: MFOS8 Position
| #define SYS_GPB_MFOS_MFOS9_Msk (0x1ul << SYS_GPB_MFOS_MFOS9_Pos) |
SYS_T::GPB_MFOS: MFOS9 Mask
| #define SYS_GPB_MFOS_MFOS9_Pos (9) |
SYS_T::GPB_MFOS: MFOS9 Position
| #define SYS_GPB_MFPH_PB10MFP_Msk (0xful << SYS_GPB_MFPH_PB10MFP_Pos) |
SYS_T::GPB_MFPH: PB10MFP Mask
| #define SYS_GPB_MFPH_PB10MFP_Pos (8) |
SYS_T::GPB_MFPH: PB10MFP Position
| #define SYS_GPB_MFPH_PB11MFP_Msk (0xful << SYS_GPB_MFPH_PB11MFP_Pos) |
SYS_T::GPB_MFPH: PB11MFP Mask
| #define SYS_GPB_MFPH_PB11MFP_Pos (12) |
SYS_T::GPB_MFPH: PB11MFP Position
| #define SYS_GPB_MFPH_PB12MFP_Msk (0xful << SYS_GPB_MFPH_PB12MFP_Pos) |
SYS_T::GPB_MFPH: PB12MFP Mask
| #define SYS_GPB_MFPH_PB12MFP_Pos (16) |
SYS_T::GPB_MFPH: PB12MFP Position
| #define SYS_GPB_MFPH_PB13MFP_Msk (0xful << SYS_GPB_MFPH_PB13MFP_Pos) |
SYS_T::GPB_MFPH: PB13MFP Mask
| #define SYS_GPB_MFPH_PB13MFP_Pos (20) |
SYS_T::GPB_MFPH: PB13MFP Position
| #define SYS_GPB_MFPH_PB14MFP_Msk (0xful << SYS_GPB_MFPH_PB14MFP_Pos) |
SYS_T::GPB_MFPH: PB14MFP Mask
| #define SYS_GPB_MFPH_PB14MFP_Pos (24) |
SYS_T::GPB_MFPH: PB14MFP Position
| #define SYS_GPB_MFPH_PB15MFP_Msk (0xful << SYS_GPB_MFPH_PB15MFP_Pos) |
SYS_T::GPB_MFPH: PB15MFP Mask
| #define SYS_GPB_MFPH_PB15MFP_Pos (28) |
SYS_T::GPB_MFPH: PB15MFP Position
| #define SYS_GPB_MFPH_PB8MFP_Msk (0xful << SYS_GPB_MFPH_PB8MFP_Pos) |
SYS_T::GPB_MFPH: PB8MFP Mask
| #define SYS_GPB_MFPH_PB8MFP_Pos (0) |
SYS_T::GPB_MFPH: PB8MFP Position
| #define SYS_GPB_MFPH_PB9MFP_Msk (0xful << SYS_GPB_MFPH_PB9MFP_Pos) |
SYS_T::GPB_MFPH: PB9MFP Mask
| #define SYS_GPB_MFPH_PB9MFP_Pos (4) |
SYS_T::GPB_MFPH: PB9MFP Position
| #define SYS_GPB_MFPL_PB0MFP_Msk (0xful << SYS_GPB_MFPL_PB0MFP_Pos) |
SYS_T::GPB_MFPL: PB0MFP Mask
| #define SYS_GPB_MFPL_PB0MFP_Pos (0) |
SYS_T::GPB_MFPL: PB0MFP Position
| #define SYS_GPB_MFPL_PB1MFP_Msk (0xful << SYS_GPB_MFPL_PB1MFP_Pos) |
SYS_T::GPB_MFPL: PB1MFP Mask
| #define SYS_GPB_MFPL_PB1MFP_Pos (4) |
SYS_T::GPB_MFPL: PB1MFP Position
| #define SYS_GPB_MFPL_PB2MFP_Msk (0xful << SYS_GPB_MFPL_PB2MFP_Pos) |
SYS_T::GPB_MFPL: PB2MFP Mask
| #define SYS_GPB_MFPL_PB2MFP_Pos (8) |
SYS_T::GPB_MFPL: PB2MFP Position
| #define SYS_GPB_MFPL_PB3MFP_Msk (0xful << SYS_GPB_MFPL_PB3MFP_Pos) |
SYS_T::GPB_MFPL: PB3MFP Mask
| #define SYS_GPB_MFPL_PB3MFP_Pos (12) |
SYS_T::GPB_MFPL: PB3MFP Position
| #define SYS_GPB_MFPL_PB4MFP_Msk (0xful << SYS_GPB_MFPL_PB4MFP_Pos) |
SYS_T::GPB_MFPL: PB4MFP Mask
| #define SYS_GPB_MFPL_PB4MFP_Pos (16) |
SYS_T::GPB_MFPL: PB4MFP Position
| #define SYS_GPB_MFPL_PB5MFP_Msk (0xful << SYS_GPB_MFPL_PB5MFP_Pos) |
SYS_T::GPB_MFPL: PB5MFP Mask
| #define SYS_GPB_MFPL_PB5MFP_Pos (20) |
SYS_T::GPB_MFPL: PB5MFP Position
| #define SYS_GPB_MFPL_PB6MFP_Msk (0xful << SYS_GPB_MFPL_PB6MFP_Pos) |
SYS_T::GPB_MFPL: PB6MFP Mask
| #define SYS_GPB_MFPL_PB6MFP_Pos (24) |
SYS_T::GPB_MFPL: PB6MFP Position
| #define SYS_GPB_MFPL_PB7MFP_Msk (0xful << SYS_GPB_MFPL_PB7MFP_Pos) |
SYS_T::GPB_MFPL: PB7MFP Mask
| #define SYS_GPB_MFPL_PB7MFP_Pos (28) |
SYS_T::GPB_MFPL: PB7MFP Position
| #define SYS_GPC_MFOS_MFOS0_Msk (0x1ul << SYS_GPC_MFOS_MFOS0_Pos) |
SYS_T::GPC_MFOS: MFOS0 Mask
| #define SYS_GPC_MFOS_MFOS0_Pos (0) |
SYS_T::GPC_MFOS: MFOS0 Position
| #define SYS_GPC_MFOS_MFOS10_Msk (0x1ul << SYS_GPC_MFOS_MFOS10_Pos) |
SYS_T::GPC_MFOS: MFOS10 Mask
| #define SYS_GPC_MFOS_MFOS10_Pos (10) |
SYS_T::GPC_MFOS: MFOS10 Position
| #define SYS_GPC_MFOS_MFOS11_Msk (0x1ul << SYS_GPC_MFOS_MFOS11_Pos) |
SYS_T::GPC_MFOS: MFOS11 Mask
| #define SYS_GPC_MFOS_MFOS11_Pos (11) |
SYS_T::GPC_MFOS: MFOS11 Position
| #define SYS_GPC_MFOS_MFOS12_Msk (0x1ul << SYS_GPC_MFOS_MFOS12_Pos) |
SYS_T::GPC_MFOS: MFOS12 Mask
| #define SYS_GPC_MFOS_MFOS12_Pos (12) |
SYS_T::GPC_MFOS: MFOS12 Position
| #define SYS_GPC_MFOS_MFOS13_Msk (0x1ul << SYS_GPC_MFOS_MFOS13_Pos) |
SYS_T::GPC_MFOS: MFOS13 Mask
| #define SYS_GPC_MFOS_MFOS13_Pos (13) |
SYS_T::GPC_MFOS: MFOS13 Position
| #define SYS_GPC_MFOS_MFOS14_Msk (0x1ul << SYS_GPC_MFOS_MFOS14_Pos) |
SYS_T::GPC_MFOS: MFOS14 Mask
| #define SYS_GPC_MFOS_MFOS14_Pos (14) |
SYS_T::GPC_MFOS: MFOS14 Position
| #define SYS_GPC_MFOS_MFOS15_Msk (0x1ul << SYS_GPC_MFOS_MFOS15_Pos) |
SYS_T::GPC_MFOS: MFOS15 Mask
| #define SYS_GPC_MFOS_MFOS15_Pos (15) |
SYS_T::GPC_MFOS: MFOS15 Position
| #define SYS_GPC_MFOS_MFOS1_Msk (0x1ul << SYS_GPC_MFOS_MFOS1_Pos) |
SYS_T::GPC_MFOS: MFOS1 Mask
| #define SYS_GPC_MFOS_MFOS1_Pos (1) |
SYS_T::GPC_MFOS: MFOS1 Position
| #define SYS_GPC_MFOS_MFOS2_Msk (0x1ul << SYS_GPC_MFOS_MFOS2_Pos) |
SYS_T::GPC_MFOS: MFOS2 Mask
| #define SYS_GPC_MFOS_MFOS2_Pos (2) |
SYS_T::GPC_MFOS: MFOS2 Position
| #define SYS_GPC_MFOS_MFOS3_Msk (0x1ul << SYS_GPC_MFOS_MFOS3_Pos) |
SYS_T::GPC_MFOS: MFOS3 Mask
| #define SYS_GPC_MFOS_MFOS3_Pos (3) |
SYS_T::GPC_MFOS: MFOS3 Position
| #define SYS_GPC_MFOS_MFOS4_Msk (0x1ul << SYS_GPC_MFOS_MFOS4_Pos) |
SYS_T::GPC_MFOS: MFOS4 Mask
| #define SYS_GPC_MFOS_MFOS4_Pos (4) |
SYS_T::GPC_MFOS: MFOS4 Position
| #define SYS_GPC_MFOS_MFOS5_Msk (0x1ul << SYS_GPC_MFOS_MFOS5_Pos) |
SYS_T::GPC_MFOS: MFOS5 Mask
| #define SYS_GPC_MFOS_MFOS5_Pos (5) |
SYS_T::GPC_MFOS: MFOS5 Position
| #define SYS_GPC_MFOS_MFOS6_Msk (0x1ul << SYS_GPC_MFOS_MFOS6_Pos) |
SYS_T::GPC_MFOS: MFOS6 Mask
| #define SYS_GPC_MFOS_MFOS6_Pos (6) |
SYS_T::GPC_MFOS: MFOS6 Position
| #define SYS_GPC_MFOS_MFOS7_Msk (0x1ul << SYS_GPC_MFOS_MFOS7_Pos) |
SYS_T::GPC_MFOS: MFOS7 Mask
| #define SYS_GPC_MFOS_MFOS7_Pos (7) |
SYS_T::GPC_MFOS: MFOS7 Position
| #define SYS_GPC_MFOS_MFOS8_Msk (0x1ul << SYS_GPC_MFOS_MFOS8_Pos) |
SYS_T::GPC_MFOS: MFOS8 Mask
| #define SYS_GPC_MFOS_MFOS8_Pos (8) |
SYS_T::GPC_MFOS: MFOS8 Position
| #define SYS_GPC_MFOS_MFOS9_Msk (0x1ul << SYS_GPC_MFOS_MFOS9_Pos) |
SYS_T::GPC_MFOS: MFOS9 Mask
| #define SYS_GPC_MFOS_MFOS9_Pos (9) |
SYS_T::GPC_MFOS: MFOS9 Position
| #define SYS_GPC_MFPH_PC10MFP_Msk (0xful << SYS_GPC_MFPH_PC10MFP_Pos) |
SYS_T::GPC_MFPH: PC10MFP Mask
| #define SYS_GPC_MFPH_PC10MFP_Pos (8) |
SYS_T::GPC_MFPH: PC10MFP Position
| #define SYS_GPC_MFPH_PC11MFP_Msk (0xful << SYS_GPC_MFPH_PC11MFP_Pos) |
SYS_T::GPC_MFPH: PC11MFP Mask
| #define SYS_GPC_MFPH_PC11MFP_Pos (12) |
SYS_T::GPC_MFPH: PC11MFP Position
| #define SYS_GPC_MFPH_PC12MFP_Msk (0xful << SYS_GPC_MFPH_PC12MFP_Pos) |
SYS_T::GPC_MFPH: PC12MFP Mask
| #define SYS_GPC_MFPH_PC12MFP_Pos (16) |
SYS_T::GPC_MFPH: PC12MFP Position
| #define SYS_GPC_MFPH_PC13MFP_Msk (0xful << SYS_GPC_MFPH_PC13MFP_Pos) |
SYS_T::GPC_MFPH: PC13MFP Mask
| #define SYS_GPC_MFPH_PC13MFP_Pos (20) |
SYS_T::GPC_MFPH: PC13MFP Position
| #define SYS_GPC_MFPH_PC14MFP_Msk (0xful << SYS_GPC_MFPH_PC14MFP_Pos) |
SYS_T::GPC_MFPH: PC14MFP Mask
| #define SYS_GPC_MFPH_PC14MFP_Pos (24) |
SYS_T::GPC_MFPH: PC14MFP Position
| #define SYS_GPC_MFPH_PC15MFP_Msk (0xful << SYS_GPC_MFPH_PC15MFP_Pos) |
SYS_T::GPC_MFPH: PC15MFP Mask
| #define SYS_GPC_MFPH_PC15MFP_Pos (28) |
SYS_T::GPC_MFPH: PC15MFP Position
| #define SYS_GPC_MFPH_PC8MFP_Msk (0xful << SYS_GPC_MFPH_PC8MFP_Pos) |
SYS_T::GPC_MFPH: PC8MFP Mask
| #define SYS_GPC_MFPH_PC8MFP_Pos (0) |
SYS_T::GPC_MFPH: PC8MFP Position
| #define SYS_GPC_MFPH_PC9MFP_Msk (0xful << SYS_GPC_MFPH_PC9MFP_Pos) |
SYS_T::GPC_MFPH: PC9MFP Mask
| #define SYS_GPC_MFPH_PC9MFP_Pos (4) |
SYS_T::GPC_MFPH: PC9MFP Position
| #define SYS_GPC_MFPL_PC0MFP_Msk (0xful << SYS_GPC_MFPL_PC0MFP_Pos) |
SYS_T::GPC_MFPL: PC0MFP Mask
| #define SYS_GPC_MFPL_PC0MFP_Pos (0) |
SYS_T::GPC_MFPL: PC0MFP Position
| #define SYS_GPC_MFPL_PC1MFP_Msk (0xful << SYS_GPC_MFPL_PC1MFP_Pos) |
SYS_T::GPC_MFPL: PC1MFP Mask
| #define SYS_GPC_MFPL_PC1MFP_Pos (4) |
SYS_T::GPC_MFPL: PC1MFP Position
| #define SYS_GPC_MFPL_PC2MFP_Msk (0xful << SYS_GPC_MFPL_PC2MFP_Pos) |
SYS_T::GPC_MFPL: PC2MFP Mask
| #define SYS_GPC_MFPL_PC2MFP_Pos (8) |
SYS_T::GPC_MFPL: PC2MFP Position
| #define SYS_GPC_MFPL_PC3MFP_Msk (0xful << SYS_GPC_MFPL_PC3MFP_Pos) |
SYS_T::GPC_MFPL: PC3MFP Mask
| #define SYS_GPC_MFPL_PC3MFP_Pos (12) |
SYS_T::GPC_MFPL: PC3MFP Position
| #define SYS_GPC_MFPL_PC4MFP_Msk (0xful << SYS_GPC_MFPL_PC4MFP_Pos) |
SYS_T::GPC_MFPL: PC4MFP Mask
| #define SYS_GPC_MFPL_PC4MFP_Pos (16) |
SYS_T::GPC_MFPL: PC4MFP Position
| #define SYS_GPC_MFPL_PC5MFP_Msk (0xful << SYS_GPC_MFPL_PC5MFP_Pos) |
SYS_T::GPC_MFPL: PC5MFP Mask
| #define SYS_GPC_MFPL_PC5MFP_Pos (20) |
SYS_T::GPC_MFPL: PC5MFP Position
| #define SYS_GPC_MFPL_PC6MFP_Msk (0xful << SYS_GPC_MFPL_PC6MFP_Pos) |
SYS_T::GPC_MFPL: PC6MFP Mask
| #define SYS_GPC_MFPL_PC6MFP_Pos (24) |
SYS_T::GPC_MFPL: PC6MFP Position
| #define SYS_GPC_MFPL_PC7MFP_Msk (0xful << SYS_GPC_MFPL_PC7MFP_Pos) |
SYS_T::GPC_MFPL: PC7MFP Mask
| #define SYS_GPC_MFPL_PC7MFP_Pos (28) |
SYS_T::GPC_MFPL: PC7MFP Position
| #define SYS_GPD_MFOS_MFOS0_Msk (0x1ul << SYS_GPD_MFOS_MFOS0_Pos) |
SYS_T::GPD_MFOS: MFOS0 Mask
| #define SYS_GPD_MFOS_MFOS0_Pos (0) |
SYS_T::GPD_MFOS: MFOS0 Position
| #define SYS_GPD_MFOS_MFOS10_Msk (0x1ul << SYS_GPD_MFOS_MFOS10_Pos) |
SYS_T::GPD_MFOS: MFOS10 Mask
| #define SYS_GPD_MFOS_MFOS10_Pos (10) |
SYS_T::GPD_MFOS: MFOS10 Position
| #define SYS_GPD_MFOS_MFOS11_Msk (0x1ul << SYS_GPD_MFOS_MFOS11_Pos) |
SYS_T::GPD_MFOS: MFOS11 Mask
| #define SYS_GPD_MFOS_MFOS11_Pos (11) |
SYS_T::GPD_MFOS: MFOS11 Position
| #define SYS_GPD_MFOS_MFOS12_Msk (0x1ul << SYS_GPD_MFOS_MFOS12_Pos) |
SYS_T::GPD_MFOS: MFOS12 Mask
| #define SYS_GPD_MFOS_MFOS12_Pos (12) |
SYS_T::GPD_MFOS: MFOS12 Position
| #define SYS_GPD_MFOS_MFOS13_Msk (0x1ul << SYS_GPD_MFOS_MFOS13_Pos) |
SYS_T::GPD_MFOS: MFOS13 Mask
| #define SYS_GPD_MFOS_MFOS13_Pos (13) |
SYS_T::GPD_MFOS: MFOS13 Position
| #define SYS_GPD_MFOS_MFOS14_Msk (0x1ul << SYS_GPD_MFOS_MFOS14_Pos) |
SYS_T::GPD_MFOS: MFOS14 Mask
| #define SYS_GPD_MFOS_MFOS14_Pos (14) |
SYS_T::GPD_MFOS: MFOS14 Position
| #define SYS_GPD_MFOS_MFOS15_Msk (0x1ul << SYS_GPD_MFOS_MFOS15_Pos) |
SYS_T::GPD_MFOS: MFOS15 Mask
| #define SYS_GPD_MFOS_MFOS15_Pos (15) |
SYS_T::GPD_MFOS: MFOS15 Position
| #define SYS_GPD_MFOS_MFOS1_Msk (0x1ul << SYS_GPD_MFOS_MFOS1_Pos) |
SYS_T::GPD_MFOS: MFOS1 Mask
| #define SYS_GPD_MFOS_MFOS1_Pos (1) |
SYS_T::GPD_MFOS: MFOS1 Position
| #define SYS_GPD_MFOS_MFOS2_Msk (0x1ul << SYS_GPD_MFOS_MFOS2_Pos) |
SYS_T::GPD_MFOS: MFOS2 Mask
| #define SYS_GPD_MFOS_MFOS2_Pos (2) |
SYS_T::GPD_MFOS: MFOS2 Position
| #define SYS_GPD_MFOS_MFOS3_Msk (0x1ul << SYS_GPD_MFOS_MFOS3_Pos) |
SYS_T::GPD_MFOS: MFOS3 Mask
| #define SYS_GPD_MFOS_MFOS3_Pos (3) |
SYS_T::GPD_MFOS: MFOS3 Position
| #define SYS_GPD_MFOS_MFOS4_Msk (0x1ul << SYS_GPD_MFOS_MFOS4_Pos) |
SYS_T::GPD_MFOS: MFOS4 Mask
| #define SYS_GPD_MFOS_MFOS4_Pos (4) |
SYS_T::GPD_MFOS: MFOS4 Position
| #define SYS_GPD_MFOS_MFOS5_Msk (0x1ul << SYS_GPD_MFOS_MFOS5_Pos) |
SYS_T::GPD_MFOS: MFOS5 Mask
| #define SYS_GPD_MFOS_MFOS5_Pos (5) |
SYS_T::GPD_MFOS: MFOS5 Position
| #define SYS_GPD_MFOS_MFOS6_Msk (0x1ul << SYS_GPD_MFOS_MFOS6_Pos) |
SYS_T::GPD_MFOS: MFOS6 Mask
| #define SYS_GPD_MFOS_MFOS6_Pos (6) |
SYS_T::GPD_MFOS: MFOS6 Position
| #define SYS_GPD_MFOS_MFOS7_Msk (0x1ul << SYS_GPD_MFOS_MFOS7_Pos) |
SYS_T::GPD_MFOS: MFOS7 Mask
| #define SYS_GPD_MFOS_MFOS7_Pos (7) |
SYS_T::GPD_MFOS: MFOS7 Position
| #define SYS_GPD_MFOS_MFOS8_Msk (0x1ul << SYS_GPD_MFOS_MFOS8_Pos) |
SYS_T::GPD_MFOS: MFOS8 Mask
| #define SYS_GPD_MFOS_MFOS8_Pos (8) |
SYS_T::GPD_MFOS: MFOS8 Position
| #define SYS_GPD_MFOS_MFOS9_Msk (0x1ul << SYS_GPD_MFOS_MFOS9_Pos) |
SYS_T::GPD_MFOS: MFOS9 Mask
| #define SYS_GPD_MFOS_MFOS9_Pos (9) |
SYS_T::GPD_MFOS: MFOS9 Position
| #define SYS_GPD_MFPH_PD10MFP_Msk (0xful << SYS_GPD_MFPH_PD10MFP_Pos) |
SYS_T::GPD_MFPH: PD10MFP Mask
| #define SYS_GPD_MFPH_PD10MFP_Pos (8) |
SYS_T::GPD_MFPH: PD10MFP Position
| #define SYS_GPD_MFPH_PD11MFP_Msk (0xful << SYS_GPD_MFPH_PD11MFP_Pos) |
SYS_T::GPD_MFPH: PD11MFP Mask
| #define SYS_GPD_MFPH_PD11MFP_Pos (12) |
SYS_T::GPD_MFPH: PD11MFP Position
| #define SYS_GPD_MFPH_PD12MFP_Msk (0xful << SYS_GPD_MFPH_PD12MFP_Pos) |
SYS_T::GPD_MFPH: PD12MFP Mask
| #define SYS_GPD_MFPH_PD12MFP_Pos (16) |
SYS_T::GPD_MFPH: PD12MFP Position
| #define SYS_GPD_MFPH_PD13MFP_Msk (0xful << SYS_GPD_MFPH_PD13MFP_Pos) |
SYS_T::GPD_MFPH: PD13MFP Mask
| #define SYS_GPD_MFPH_PD13MFP_Pos (20) |
SYS_T::GPD_MFPH: PD13MFP Position
| #define SYS_GPD_MFPH_PD14MFP_Msk (0xful << SYS_GPD_MFPH_PD14MFP_Pos) |
SYS_T::GPD_MFPH: PD14MFP Mask
| #define SYS_GPD_MFPH_PD14MFP_Pos (24) |
SYS_T::GPD_MFPH: PD14MFP Position
| #define SYS_GPD_MFPH_PD15MFP_Msk (0xful << SYS_GPD_MFPH_PD15MFP_Pos) |
SYS_T::GPD_MFPH: PD15MFP Mask
| #define SYS_GPD_MFPH_PD15MFP_Pos (28) |
SYS_T::GPD_MFPH: PD15MFP Position
| #define SYS_GPD_MFPH_PD8MFP_Msk (0xful << SYS_GPD_MFPH_PD8MFP_Pos) |
SYS_T::GPD_MFPH: PD8MFP Mask
| #define SYS_GPD_MFPH_PD8MFP_Pos (0) |
SYS_T::GPD_MFPH: PD8MFP Position
| #define SYS_GPD_MFPH_PD9MFP_Msk (0xful << SYS_GPD_MFPH_PD9MFP_Pos) |
SYS_T::GPD_MFPH: PD9MFP Mask
| #define SYS_GPD_MFPH_PD9MFP_Pos (4) |
SYS_T::GPD_MFPH: PD9MFP Position
| #define SYS_GPD_MFPL_PD0MFP_Msk (0xful << SYS_GPD_MFPL_PD0MFP_Pos) |
SYS_T::GPD_MFPL: PD0MFP Mask
| #define SYS_GPD_MFPL_PD0MFP_Pos (0) |
SYS_T::GPD_MFPL: PD0MFP Position
| #define SYS_GPD_MFPL_PD1MFP_Msk (0xful << SYS_GPD_MFPL_PD1MFP_Pos) |
SYS_T::GPD_MFPL: PD1MFP Mask
| #define SYS_GPD_MFPL_PD1MFP_Pos (4) |
SYS_T::GPD_MFPL: PD1MFP Position
| #define SYS_GPD_MFPL_PD2MFP_Msk (0xful << SYS_GPD_MFPL_PD2MFP_Pos) |
SYS_T::GPD_MFPL: PD2MFP Mask
| #define SYS_GPD_MFPL_PD2MFP_Pos (8) |
SYS_T::GPD_MFPL: PD2MFP Position
| #define SYS_GPD_MFPL_PD3MFP_Msk (0xful << SYS_GPD_MFPL_PD3MFP_Pos) |
SYS_T::GPD_MFPL: PD3MFP Mask
| #define SYS_GPD_MFPL_PD3MFP_Pos (12) |
SYS_T::GPD_MFPL: PD3MFP Position
| #define SYS_GPD_MFPL_PD4MFP_Msk (0xful << SYS_GPD_MFPL_PD4MFP_Pos) |
SYS_T::GPD_MFPL: PD4MFP Mask
| #define SYS_GPD_MFPL_PD4MFP_Pos (16) |
SYS_T::GPD_MFPL: PD4MFP Position
| #define SYS_GPD_MFPL_PD5MFP_Msk (0xful << SYS_GPD_MFPL_PD5MFP_Pos) |
SYS_T::GPD_MFPL: PD5MFP Mask
| #define SYS_GPD_MFPL_PD5MFP_Pos (20) |
SYS_T::GPD_MFPL: PD5MFP Position
| #define SYS_GPD_MFPL_PD6MFP_Msk (0xful << SYS_GPD_MFPL_PD6MFP_Pos) |
SYS_T::GPD_MFPL: PD6MFP Mask
| #define SYS_GPD_MFPL_PD6MFP_Pos (24) |
SYS_T::GPD_MFPL: PD6MFP Position
| #define SYS_GPD_MFPL_PD7MFP_Msk (0xful << SYS_GPD_MFPL_PD7MFP_Pos) |
SYS_T::GPD_MFPL: PD7MFP Mask
| #define SYS_GPD_MFPL_PD7MFP_Pos (28) |
SYS_T::GPD_MFPL: PD7MFP Position
| #define SYS_GPE_MFOS_MFOS0_Msk (0x1ul << SYS_GPE_MFOS_MFOS0_Pos) |
SYS_T::GPE_MFOS: MFOS0 Mask
| #define SYS_GPE_MFOS_MFOS0_Pos (0) |
SYS_T::GPE_MFOS: MFOS0 Position
| #define SYS_GPE_MFOS_MFOS10_Msk (0x1ul << SYS_GPE_MFOS_MFOS10_Pos) |
SYS_T::GPE_MFOS: MFOS10 Mask
| #define SYS_GPE_MFOS_MFOS10_Pos (10) |
SYS_T::GPE_MFOS: MFOS10 Position
| #define SYS_GPE_MFOS_MFOS11_Msk (0x1ul << SYS_GPE_MFOS_MFOS11_Pos) |
SYS_T::GPE_MFOS: MFOS11 Mask
| #define SYS_GPE_MFOS_MFOS11_Pos (11) |
SYS_T::GPE_MFOS: MFOS11 Position
| #define SYS_GPE_MFOS_MFOS12_Msk (0x1ul << SYS_GPE_MFOS_MFOS12_Pos) |
SYS_T::GPE_MFOS: MFOS12 Mask
| #define SYS_GPE_MFOS_MFOS12_Pos (12) |
SYS_T::GPE_MFOS: MFOS12 Position
| #define SYS_GPE_MFOS_MFOS13_Msk (0x1ul << SYS_GPE_MFOS_MFOS13_Pos) |
SYS_T::GPE_MFOS: MFOS13 Mask
| #define SYS_GPE_MFOS_MFOS13_Pos (13) |
SYS_T::GPE_MFOS: MFOS13 Position
| #define SYS_GPE_MFOS_MFOS14_Msk (0x1ul << SYS_GPE_MFOS_MFOS14_Pos) |
SYS_T::GPE_MFOS: MFOS14 Mask
| #define SYS_GPE_MFOS_MFOS14_Pos (14) |
SYS_T::GPE_MFOS: MFOS14 Position
| #define SYS_GPE_MFOS_MFOS15_Msk (0x1ul << SYS_GPE_MFOS_MFOS15_Pos) |
SYS_T::GPE_MFOS: MFOS15 Mask
| #define SYS_GPE_MFOS_MFOS15_Pos (15) |
SYS_T::GPE_MFOS: MFOS15 Position
| #define SYS_GPE_MFOS_MFOS1_Msk (0x1ul << SYS_GPE_MFOS_MFOS1_Pos) |
SYS_T::GPE_MFOS: MFOS1 Mask
| #define SYS_GPE_MFOS_MFOS1_Pos (1) |
SYS_T::GPE_MFOS: MFOS1 Position
| #define SYS_GPE_MFOS_MFOS2_Msk (0x1ul << SYS_GPE_MFOS_MFOS2_Pos) |
SYS_T::GPE_MFOS: MFOS2 Mask
| #define SYS_GPE_MFOS_MFOS2_Pos (2) |
SYS_T::GPE_MFOS: MFOS2 Position
| #define SYS_GPE_MFOS_MFOS3_Msk (0x1ul << SYS_GPE_MFOS_MFOS3_Pos) |
SYS_T::GPE_MFOS: MFOS3 Mask
| #define SYS_GPE_MFOS_MFOS3_Pos (3) |
SYS_T::GPE_MFOS: MFOS3 Position
| #define SYS_GPE_MFOS_MFOS4_Msk (0x1ul << SYS_GPE_MFOS_MFOS4_Pos) |
SYS_T::GPE_MFOS: MFOS4 Mask
| #define SYS_GPE_MFOS_MFOS4_Pos (4) |
SYS_T::GPE_MFOS: MFOS4 Position
| #define SYS_GPE_MFOS_MFOS5_Msk (0x1ul << SYS_GPE_MFOS_MFOS5_Pos) |
SYS_T::GPE_MFOS: MFOS5 Mask
| #define SYS_GPE_MFOS_MFOS5_Pos (5) |
SYS_T::GPE_MFOS: MFOS5 Position
| #define SYS_GPE_MFOS_MFOS6_Msk (0x1ul << SYS_GPE_MFOS_MFOS6_Pos) |
SYS_T::GPE_MFOS: MFOS6 Mask
| #define SYS_GPE_MFOS_MFOS6_Pos (6) |
SYS_T::GPE_MFOS: MFOS6 Position
| #define SYS_GPE_MFOS_MFOS7_Msk (0x1ul << SYS_GPE_MFOS_MFOS7_Pos) |
SYS_T::GPE_MFOS: MFOS7 Mask
| #define SYS_GPE_MFOS_MFOS7_Pos (7) |
SYS_T::GPE_MFOS: MFOS7 Position
| #define SYS_GPE_MFOS_MFOS8_Msk (0x1ul << SYS_GPE_MFOS_MFOS8_Pos) |
SYS_T::GPE_MFOS: MFOS8 Mask
| #define SYS_GPE_MFOS_MFOS8_Pos (8) |
SYS_T::GPE_MFOS: MFOS8 Position
| #define SYS_GPE_MFOS_MFOS9_Msk (0x1ul << SYS_GPE_MFOS_MFOS9_Pos) |
SYS_T::GPE_MFOS: MFOS9 Mask
| #define SYS_GPE_MFOS_MFOS9_Pos (9) |
SYS_T::GPE_MFOS: MFOS9 Position
| #define SYS_GPE_MFPH_PE10MFP_Msk (0xful << SYS_GPE_MFPH_PE10MFP_Pos) |
SYS_T::GPE_MFPH: PE10MFP Mask
| #define SYS_GPE_MFPH_PE10MFP_Pos (8) |
SYS_T::GPE_MFPH: PE10MFP Position
| #define SYS_GPE_MFPH_PE11MFP_Msk (0xful << SYS_GPE_MFPH_PE11MFP_Pos) |
SYS_T::GPE_MFPH: PE11MFP Mask
| #define SYS_GPE_MFPH_PE11MFP_Pos (12) |
SYS_T::GPE_MFPH: PE11MFP Position
| #define SYS_GPE_MFPH_PE12MFP_Msk (0xful << SYS_GPE_MFPH_PE12MFP_Pos) |
SYS_T::GPE_MFPH: PE12MFP Mask
| #define SYS_GPE_MFPH_PE12MFP_Pos (16) |
SYS_T::GPE_MFPH: PE12MFP Position
| #define SYS_GPE_MFPH_PE13MFP_Msk (0xful << SYS_GPE_MFPH_PE13MFP_Pos) |
SYS_T::GPE_MFPH: PE13MFP Mask
| #define SYS_GPE_MFPH_PE13MFP_Pos (20) |
SYS_T::GPE_MFPH: PE13MFP Position
| #define SYS_GPE_MFPH_PE14MFP_Msk (0xful << SYS_GPE_MFPH_PE14MFP_Pos) |
SYS_T::GPE_MFPH: PE14MFP Mask
| #define SYS_GPE_MFPH_PE14MFP_Pos (24) |
SYS_T::GPE_MFPH: PE14MFP Position
| #define SYS_GPE_MFPH_PE15MFP_Msk (0xful << SYS_GPE_MFPH_PE15MFP_Pos) |
SYS_T::GPE_MFPH: PE15MFP Mask
| #define SYS_GPE_MFPH_PE15MFP_Pos (28) |
SYS_T::GPE_MFPH: PE15MFP Position
| #define SYS_GPE_MFPH_PE8MFP_Msk (0xful << SYS_GPE_MFPH_PE8MFP_Pos) |
SYS_T::GPE_MFPH: PE8MFP Mask
| #define SYS_GPE_MFPH_PE8MFP_Pos (0) |
SYS_T::GPE_MFPH: PE8MFP Position
| #define SYS_GPE_MFPH_PE9MFP_Msk (0xful << SYS_GPE_MFPH_PE9MFP_Pos) |
SYS_T::GPE_MFPH: PE9MFP Mask
| #define SYS_GPE_MFPH_PE9MFP_Pos (4) |
SYS_T::GPE_MFPH: PE9MFP Position
| #define SYS_GPE_MFPL_PE0MFP_Msk (0xful << SYS_GPE_MFPL_PE0MFP_Pos) |
SYS_T::GPE_MFPL: PE0MFP Mask
| #define SYS_GPE_MFPL_PE0MFP_Pos (0) |
SYS_T::GPE_MFPL: PE0MFP Position
| #define SYS_GPE_MFPL_PE1MFP_Msk (0xful << SYS_GPE_MFPL_PE1MFP_Pos) |
SYS_T::GPE_MFPL: PE1MFP Mask
| #define SYS_GPE_MFPL_PE1MFP_Pos (4) |
SYS_T::GPE_MFPL: PE1MFP Position
| #define SYS_GPE_MFPL_PE2MFP_Msk (0xful << SYS_GPE_MFPL_PE2MFP_Pos) |
SYS_T::GPE_MFPL: PE2MFP Mask
| #define SYS_GPE_MFPL_PE2MFP_Pos (8) |
SYS_T::GPE_MFPL: PE2MFP Position
| #define SYS_GPE_MFPL_PE3MFP_Msk (0xful << SYS_GPE_MFPL_PE3MFP_Pos) |
SYS_T::GPE_MFPL: PE3MFP Mask
| #define SYS_GPE_MFPL_PE3MFP_Pos (12) |
SYS_T::GPE_MFPL: PE3MFP Position
| #define SYS_GPE_MFPL_PE4MFP_Msk (0xful << SYS_GPE_MFPL_PE4MFP_Pos) |
SYS_T::GPE_MFPL: PE4MFP Mask
| #define SYS_GPE_MFPL_PE4MFP_Pos (16) |
SYS_T::GPE_MFPL: PE4MFP Position
| #define SYS_GPE_MFPL_PE5MFP_Msk (0xful << SYS_GPE_MFPL_PE5MFP_Pos) |
SYS_T::GPE_MFPL: PE5MFP Mask
| #define SYS_GPE_MFPL_PE5MFP_Pos (20) |
SYS_T::GPE_MFPL: PE5MFP Position
| #define SYS_GPE_MFPL_PE6MFP_Msk (0xful << SYS_GPE_MFPL_PE6MFP_Pos) |
SYS_T::GPE_MFPL: PE6MFP Mask
| #define SYS_GPE_MFPL_PE6MFP_Pos (24) |
SYS_T::GPE_MFPL: PE6MFP Position
| #define SYS_GPE_MFPL_PE7MFP_Msk (0xful << SYS_GPE_MFPL_PE7MFP_Pos) |
SYS_T::GPE_MFPL: PE7MFP Mask
| #define SYS_GPE_MFPL_PE7MFP_Pos (28) |
SYS_T::GPE_MFPL: PE7MFP Position
| #define SYS_GPF_MFOS_MFOS0_Msk (0x1ul << SYS_GPF_MFOS_MFOS0_Pos) |
SYS_T::GPF_MFOS: MFOS0 Mask
| #define SYS_GPF_MFOS_MFOS0_Pos (0) |
SYS_T::GPF_MFOS: MFOS0 Position
| #define SYS_GPF_MFOS_MFOS10_Msk (0x1ul << SYS_GPF_MFOS_MFOS10_Pos) |
SYS_T::GPF_MFOS: MFOS10 Mask
| #define SYS_GPF_MFOS_MFOS10_Pos (10) |
SYS_T::GPF_MFOS: MFOS10 Position
| #define SYS_GPF_MFOS_MFOS11_Msk (0x1ul << SYS_GPF_MFOS_MFOS11_Pos) |
SYS_T::GPF_MFOS: MFOS11 Mask
| #define SYS_GPF_MFOS_MFOS11_Pos (11) |
SYS_T::GPF_MFOS: MFOS11 Position
| #define SYS_GPF_MFOS_MFOS12_Msk (0x1ul << SYS_GPF_MFOS_MFOS12_Pos) |
SYS_T::GPF_MFOS: MFOS12 Mask
| #define SYS_GPF_MFOS_MFOS12_Pos (12) |
SYS_T::GPF_MFOS: MFOS12 Position
| #define SYS_GPF_MFOS_MFOS13_Msk (0x1ul << SYS_GPF_MFOS_MFOS13_Pos) |
SYS_T::GPF_MFOS: MFOS13 Mask
| #define SYS_GPF_MFOS_MFOS13_Pos (13) |
SYS_T::GPF_MFOS: MFOS13 Position
| #define SYS_GPF_MFOS_MFOS14_Msk (0x1ul << SYS_GPF_MFOS_MFOS14_Pos) |
SYS_T::GPF_MFOS: MFOS14 Mask
| #define SYS_GPF_MFOS_MFOS14_Pos (14) |
SYS_T::GPF_MFOS: MFOS14 Position
| #define SYS_GPF_MFOS_MFOS15_Msk (0x1ul << SYS_GPF_MFOS_MFOS15_Pos) |
SYS_T::GPF_MFOS: MFOS15 Mask
| #define SYS_GPF_MFOS_MFOS15_Pos (15) |
SYS_T::GPF_MFOS: MFOS15 Position
| #define SYS_GPF_MFOS_MFOS1_Msk (0x1ul << SYS_GPF_MFOS_MFOS1_Pos) |
SYS_T::GPF_MFOS: MFOS1 Mask
| #define SYS_GPF_MFOS_MFOS1_Pos (1) |
SYS_T::GPF_MFOS: MFOS1 Position
| #define SYS_GPF_MFOS_MFOS2_Msk (0x1ul << SYS_GPF_MFOS_MFOS2_Pos) |
SYS_T::GPF_MFOS: MFOS2 Mask
| #define SYS_GPF_MFOS_MFOS2_Pos (2) |
SYS_T::GPF_MFOS: MFOS2 Position
| #define SYS_GPF_MFOS_MFOS3_Msk (0x1ul << SYS_GPF_MFOS_MFOS3_Pos) |
SYS_T::GPF_MFOS: MFOS3 Mask
| #define SYS_GPF_MFOS_MFOS3_Pos (3) |
SYS_T::GPF_MFOS: MFOS3 Position
| #define SYS_GPF_MFOS_MFOS4_Msk (0x1ul << SYS_GPF_MFOS_MFOS4_Pos) |
SYS_T::GPF_MFOS: MFOS4 Mask
| #define SYS_GPF_MFOS_MFOS4_Pos (4) |
SYS_T::GPF_MFOS: MFOS4 Position
| #define SYS_GPF_MFOS_MFOS5_Msk (0x1ul << SYS_GPF_MFOS_MFOS5_Pos) |
SYS_T::GPF_MFOS: MFOS5 Mask
| #define SYS_GPF_MFOS_MFOS5_Pos (5) |
SYS_T::GPF_MFOS: MFOS5 Position
| #define SYS_GPF_MFOS_MFOS6_Msk (0x1ul << SYS_GPF_MFOS_MFOS6_Pos) |
SYS_T::GPF_MFOS: MFOS6 Mask
| #define SYS_GPF_MFOS_MFOS6_Pos (6) |
SYS_T::GPF_MFOS: MFOS6 Position
| #define SYS_GPF_MFOS_MFOS7_Msk (0x1ul << SYS_GPF_MFOS_MFOS7_Pos) |
SYS_T::GPF_MFOS: MFOS7 Mask
| #define SYS_GPF_MFOS_MFOS7_Pos (7) |
SYS_T::GPF_MFOS: MFOS7 Position
| #define SYS_GPF_MFOS_MFOS8_Msk (0x1ul << SYS_GPF_MFOS_MFOS8_Pos) |
SYS_T::GPF_MFOS: MFOS8 Mask
| #define SYS_GPF_MFOS_MFOS8_Pos (8) |
SYS_T::GPF_MFOS: MFOS8 Position
| #define SYS_GPF_MFOS_MFOS9_Msk (0x1ul << SYS_GPF_MFOS_MFOS9_Pos) |
SYS_T::GPF_MFOS: MFOS9 Mask
| #define SYS_GPF_MFOS_MFOS9_Pos (9) |
SYS_T::GPF_MFOS: MFOS9 Position
| #define SYS_GPF_MFPH_PF10MFP_Msk (0xful << SYS_GPF_MFPH_PF10MFP_Pos) |
SYS_T::GPF_MFPH: PF10MFP Mask
| #define SYS_GPF_MFPH_PF10MFP_Pos (8) |
SYS_T::GPF_MFPH: PF10MFP Position
| #define SYS_GPF_MFPH_PF11MFP_Msk (0xful << SYS_GPF_MFPH_PF11MFP_Pos) |
SYS_T::GPF_MFPH: PF11MFP Mask
| #define SYS_GPF_MFPH_PF11MFP_Pos (12) |
SYS_T::GPF_MFPH: PF11MFP Position
| #define SYS_GPF_MFPH_PF12MFP_Msk (0xful << SYS_GPF_MFPH_PF12MFP_Pos) |
SYS_T::GPF_MFPH: PF12MFP Mask
| #define SYS_GPF_MFPH_PF12MFP_Pos (16) |
SYS_T::GPF_MFPH: PF12MFP Position
| #define SYS_GPF_MFPH_PF13MFP_Msk (0xful << SYS_GPF_MFPH_PF13MFP_Pos) |
SYS_T::GPF_MFPH: PF13MFP Mask
| #define SYS_GPF_MFPH_PF13MFP_Pos (20) |
SYS_T::GPF_MFPH: PF13MFP Position
| #define SYS_GPF_MFPH_PF14MFP_Msk (0xful << SYS_GPF_MFPH_PF14MFP_Pos) |
SYS_T::GPF_MFPH: PF14MFP Mask
| #define SYS_GPF_MFPH_PF14MFP_Pos (24) |
SYS_T::GPF_MFPH: PF14MFP Position
| #define SYS_GPF_MFPH_PF15MFP_Msk (0xful << SYS_GPF_MFPH_PF15MFP_Pos) |
SYS_T::GPF_MFPH: PF15MFP Mask
| #define SYS_GPF_MFPH_PF15MFP_Pos (28) |
SYS_T::GPF_MFPH: PF15MFP Position
| #define SYS_GPF_MFPH_PF8MFP_Msk (0xful << SYS_GPF_MFPH_PF8MFP_Pos) |
SYS_T::GPF_MFPH: PF8MFP Mask
| #define SYS_GPF_MFPH_PF8MFP_Pos (0) |
SYS_T::GPF_MFPH: PF8MFP Position
| #define SYS_GPF_MFPH_PF9MFP_Msk (0xful << SYS_GPF_MFPH_PF9MFP_Pos) |
SYS_T::GPF_MFPH: PF9MFP Mask
| #define SYS_GPF_MFPH_PF9MFP_Pos (4) |
SYS_T::GPF_MFPH: PF9MFP Position
| #define SYS_GPF_MFPL_PF0MFP_Msk (0xful << SYS_GPF_MFPL_PF0MFP_Pos) |
SYS_T::GPF_MFPL: PF0MFP Mask
| #define SYS_GPF_MFPL_PF0MFP_Pos (0) |
SYS_T::GPF_MFPL: PF0MFP Position
| #define SYS_GPF_MFPL_PF1MFP_Msk (0xful << SYS_GPF_MFPL_PF1MFP_Pos) |
SYS_T::GPF_MFPL: PF1MFP Mask
| #define SYS_GPF_MFPL_PF1MFP_Pos (4) |
SYS_T::GPF_MFPL: PF1MFP Position
| #define SYS_GPF_MFPL_PF2MFP_Msk (0xful << SYS_GPF_MFPL_PF2MFP_Pos) |
SYS_T::GPF_MFPL: PF2MFP Mask
| #define SYS_GPF_MFPL_PF2MFP_Pos (8) |
SYS_T::GPF_MFPL: PF2MFP Position
| #define SYS_GPF_MFPL_PF3MFP_Msk (0xful << SYS_GPF_MFPL_PF3MFP_Pos) |
SYS_T::GPF_MFPL: PF3MFP Mask
| #define SYS_GPF_MFPL_PF3MFP_Pos (12) |
SYS_T::GPF_MFPL: PF3MFP Position
| #define SYS_GPF_MFPL_PF4MFP_Msk (0xful << SYS_GPF_MFPL_PF4MFP_Pos) |
SYS_T::GPF_MFPL: PF4MFP Mask
| #define SYS_GPF_MFPL_PF4MFP_Pos (16) |
SYS_T::GPF_MFPL: PF4MFP Position
| #define SYS_GPF_MFPL_PF5MFP_Msk (0xful << SYS_GPF_MFPL_PF5MFP_Pos) |
SYS_T::GPF_MFPL: PF5MFP Mask
| #define SYS_GPF_MFPL_PF5MFP_Pos (20) |
SYS_T::GPF_MFPL: PF5MFP Position
| #define SYS_GPF_MFPL_PF6MFP_Msk (0xful << SYS_GPF_MFPL_PF6MFP_Pos) |
SYS_T::GPF_MFPL: PF6MFP Mask
| #define SYS_GPF_MFPL_PF6MFP_Pos (24) |
SYS_T::GPF_MFPL: PF6MFP Position
| #define SYS_GPF_MFPL_PF7MFP_Msk (0xful << SYS_GPF_MFPL_PF7MFP_Pos) |
SYS_T::GPF_MFPL: PF7MFP Mask
| #define SYS_GPF_MFPL_PF7MFP_Pos (28) |
SYS_T::GPF_MFPL: PF7MFP Position
| #define SYS_GPG_MFOS_MFOS0_Msk (0x1ul << SYS_GPG_MFOS_MFOS0_Pos) |
SYS_T::GPG_MFOS: MFOS0 Mask
| #define SYS_GPG_MFOS_MFOS0_Pos (0) |
SYS_T::GPG_MFOS: MFOS0 Position
| #define SYS_GPG_MFOS_MFOS10_Msk (0x1ul << SYS_GPG_MFOS_MFOS10_Pos) |
SYS_T::GPG_MFOS: MFOS10 Mask
| #define SYS_GPG_MFOS_MFOS10_Pos (10) |
SYS_T::GPG_MFOS: MFOS10 Position
| #define SYS_GPG_MFOS_MFOS11_Msk (0x1ul << SYS_GPG_MFOS_MFOS11_Pos) |
SYS_T::GPG_MFOS: MFOS11 Mask
| #define SYS_GPG_MFOS_MFOS11_Pos (11) |
SYS_T::GPG_MFOS: MFOS11 Position
| #define SYS_GPG_MFOS_MFOS12_Msk (0x1ul << SYS_GPG_MFOS_MFOS12_Pos) |
SYS_T::GPG_MFOS: MFOS12 Mask
| #define SYS_GPG_MFOS_MFOS12_Pos (12) |
SYS_T::GPG_MFOS: MFOS12 Position
| #define SYS_GPG_MFOS_MFOS13_Msk (0x1ul << SYS_GPG_MFOS_MFOS13_Pos) |
SYS_T::GPG_MFOS: MFOS13 Mask
| #define SYS_GPG_MFOS_MFOS13_Pos (13) |
SYS_T::GPG_MFOS: MFOS13 Position
| #define SYS_GPG_MFOS_MFOS14_Msk (0x1ul << SYS_GPG_MFOS_MFOS14_Pos) |
SYS_T::GPG_MFOS: MFOS14 Mask
| #define SYS_GPG_MFOS_MFOS14_Pos (14) |
SYS_T::GPG_MFOS: MFOS14 Position
| #define SYS_GPG_MFOS_MFOS15_Msk (0x1ul << SYS_GPG_MFOS_MFOS15_Pos) |
SYS_T::GPG_MFOS: MFOS15 Mask
| #define SYS_GPG_MFOS_MFOS15_Pos (15) |
SYS_T::GPG_MFOS: MFOS15 Position
| #define SYS_GPG_MFOS_MFOS1_Msk (0x1ul << SYS_GPG_MFOS_MFOS1_Pos) |
SYS_T::GPG_MFOS: MFOS1 Mask
| #define SYS_GPG_MFOS_MFOS1_Pos (1) |
SYS_T::GPG_MFOS: MFOS1 Position
| #define SYS_GPG_MFOS_MFOS2_Msk (0x1ul << SYS_GPG_MFOS_MFOS2_Pos) |
SYS_T::GPG_MFOS: MFOS2 Mask
| #define SYS_GPG_MFOS_MFOS2_Pos (2) |
SYS_T::GPG_MFOS: MFOS2 Position
| #define SYS_GPG_MFOS_MFOS3_Msk (0x1ul << SYS_GPG_MFOS_MFOS3_Pos) |
SYS_T::GPG_MFOS: MFOS3 Mask
| #define SYS_GPG_MFOS_MFOS3_Pos (3) |
SYS_T::GPG_MFOS: MFOS3 Position
| #define SYS_GPG_MFOS_MFOS4_Msk (0x1ul << SYS_GPG_MFOS_MFOS4_Pos) |
SYS_T::GPG_MFOS: MFOS4 Mask
| #define SYS_GPG_MFOS_MFOS4_Pos (4) |
SYS_T::GPG_MFOS: MFOS4 Position
| #define SYS_GPG_MFOS_MFOS5_Msk (0x1ul << SYS_GPG_MFOS_MFOS5_Pos) |
SYS_T::GPG_MFOS: MFOS5 Mask
| #define SYS_GPG_MFOS_MFOS5_Pos (5) |
SYS_T::GPG_MFOS: MFOS5 Position
| #define SYS_GPG_MFOS_MFOS6_Msk (0x1ul << SYS_GPG_MFOS_MFOS6_Pos) |
SYS_T::GPG_MFOS: MFOS6 Mask
| #define SYS_GPG_MFOS_MFOS6_Pos (6) |
SYS_T::GPG_MFOS: MFOS6 Position
| #define SYS_GPG_MFOS_MFOS7_Msk (0x1ul << SYS_GPG_MFOS_MFOS7_Pos) |
SYS_T::GPG_MFOS: MFOS7 Mask
| #define SYS_GPG_MFOS_MFOS7_Pos (7) |
SYS_T::GPG_MFOS: MFOS7 Position
| #define SYS_GPG_MFOS_MFOS8_Msk (0x1ul << SYS_GPG_MFOS_MFOS8_Pos) |
SYS_T::GPG_MFOS: MFOS8 Mask
| #define SYS_GPG_MFOS_MFOS8_Pos (8) |
SYS_T::GPG_MFOS: MFOS8 Position
| #define SYS_GPG_MFOS_MFOS9_Msk (0x1ul << SYS_GPG_MFOS_MFOS9_Pos) |
SYS_T::GPG_MFOS: MFOS9 Mask
| #define SYS_GPG_MFOS_MFOS9_Pos (9) |
SYS_T::GPG_MFOS: MFOS9 Position
| #define SYS_GPG_MFPH_PG10MFP_Msk (0xful << SYS_GPG_MFPH_PG10MFP_Pos) |
SYS_T::GPG_MFPH: PG10MFP Mask
| #define SYS_GPG_MFPH_PG10MFP_Pos (8) |
SYS_T::GPG_MFPH: PG10MFP Position
| #define SYS_GPG_MFPH_PG11MFP_Msk (0xful << SYS_GPG_MFPH_PG11MFP_Pos) |
SYS_T::GPG_MFPH: PG11MFP Mask
| #define SYS_GPG_MFPH_PG11MFP_Pos (12) |
SYS_T::GPG_MFPH: PG11MFP Position
| #define SYS_GPG_MFPH_PG12MFP_Msk (0xful << SYS_GPG_MFPH_PG12MFP_Pos) |
SYS_T::GPG_MFPH: PG12MFP Mask
| #define SYS_GPG_MFPH_PG12MFP_Pos (16) |
SYS_T::GPG_MFPH: PG12MFP Position
| #define SYS_GPG_MFPH_PG13MFP_Msk (0xful << SYS_GPG_MFPH_PG13MFP_Pos) |
SYS_T::GPG_MFPH: PG13MFP Mask
| #define SYS_GPG_MFPH_PG13MFP_Pos (20) |
SYS_T::GPG_MFPH: PG13MFP Position
| #define SYS_GPG_MFPH_PG14MFP_Msk (0xful << SYS_GPG_MFPH_PG14MFP_Pos) |
SYS_T::GPG_MFPH: PG14MFP Mask
| #define SYS_GPG_MFPH_PG14MFP_Pos (24) |
SYS_T::GPG_MFPH: PG14MFP Position
| #define SYS_GPG_MFPH_PG15MFP_Msk (0xful << SYS_GPG_MFPH_PG15MFP_Pos) |
SYS_T::GPG_MFPH: PG15MFP Mask
| #define SYS_GPG_MFPH_PG15MFP_Pos (28) |
SYS_T::GPG_MFPH: PG15MFP Position
| #define SYS_GPG_MFPH_PG8MFP_Msk (0xful << SYS_GPG_MFPH_PG8MFP_Pos) |
SYS_T::GPG_MFPH: PG8MFP Mask
| #define SYS_GPG_MFPH_PG8MFP_Pos (0) |
SYS_T::GPG_MFPH: PG8MFP Position
| #define SYS_GPG_MFPH_PG9MFP_Msk (0xful << SYS_GPG_MFPH_PG9MFP_Pos) |
SYS_T::GPG_MFPH: PG9MFP Mask
| #define SYS_GPG_MFPH_PG9MFP_Pos (4) |
SYS_T::GPG_MFPH: PG9MFP Position
| #define SYS_GPG_MFPL_PG0MFP_Msk (0xful << SYS_GPG_MFPL_PG0MFP_Pos) |
SYS_T::GPG_MFPL: PG0MFP Mask
| #define SYS_GPG_MFPL_PG0MFP_Pos (0) |
SYS_T::GPG_MFPL: PG0MFP Position
| #define SYS_GPG_MFPL_PG1MFP_Msk (0xful << SYS_GPG_MFPL_PG1MFP_Pos) |
SYS_T::GPG_MFPL: PG1MFP Mask
| #define SYS_GPG_MFPL_PG1MFP_Pos (4) |
SYS_T::GPG_MFPL: PG1MFP Position
| #define SYS_GPG_MFPL_PG2MFP_Msk (0xful << SYS_GPG_MFPL_PG2MFP_Pos) |
SYS_T::GPG_MFPL: PG2MFP Mask
| #define SYS_GPG_MFPL_PG2MFP_Pos (8) |
SYS_T::GPG_MFPL: PG2MFP Position
| #define SYS_GPG_MFPL_PG3MFP_Msk (0xful << SYS_GPG_MFPL_PG3MFP_Pos) |
SYS_T::GPG_MFPL: PG3MFP Mask
| #define SYS_GPG_MFPL_PG3MFP_Pos (12) |
SYS_T::GPG_MFPL: PG3MFP Position
| #define SYS_GPG_MFPL_PG4MFP_Msk (0xful << SYS_GPG_MFPL_PG4MFP_Pos) |
SYS_T::GPG_MFPL: PG4MFP Mask
| #define SYS_GPG_MFPL_PG4MFP_Pos (16) |
SYS_T::GPG_MFPL: PG4MFP Position
| #define SYS_GPG_MFPL_PG5MFP_Msk (0xful << SYS_GPG_MFPL_PG5MFP_Pos) |
SYS_T::GPG_MFPL: PG5MFP Mask
| #define SYS_GPG_MFPL_PG5MFP_Pos (20) |
SYS_T::GPG_MFPL: PG5MFP Position
| #define SYS_GPG_MFPL_PG6MFP_Msk (0xful << SYS_GPG_MFPL_PG6MFP_Pos) |
SYS_T::GPG_MFPL: PG6MFP Mask
| #define SYS_GPG_MFPL_PG6MFP_Pos (24) |
SYS_T::GPG_MFPL: PG6MFP Position
| #define SYS_GPG_MFPL_PG7MFP_Msk (0xful << SYS_GPG_MFPL_PG7MFP_Pos) |
SYS_T::GPG_MFPL: PG7MFP Mask
| #define SYS_GPG_MFPL_PG7MFP_Pos (28) |
SYS_T::GPG_MFPL: PG7MFP Position
| #define SYS_GPH_MFOS_MFOS0_Msk (0x1ul << SYS_GPH_MFOS_MFOS0_Pos) |
SYS_T::GPH_MFOS: MFOS0 Mask
| #define SYS_GPH_MFOS_MFOS0_Pos (0) |
SYS_T::GPH_MFOS: MFOS0 Position
| #define SYS_GPH_MFOS_MFOS10_Msk (0x1ul << SYS_GPH_MFOS_MFOS10_Pos) |
SYS_T::GPH_MFOS: MFOS10 Mask
| #define SYS_GPH_MFOS_MFOS10_Pos (10) |
SYS_T::GPH_MFOS: MFOS10 Position
| #define SYS_GPH_MFOS_MFOS11_Msk (0x1ul << SYS_GPH_MFOS_MFOS11_Pos) |
SYS_T::GPH_MFOS: MFOS11 Mask
| #define SYS_GPH_MFOS_MFOS11_Pos (11) |
SYS_T::GPH_MFOS: MFOS11 Position
| #define SYS_GPH_MFOS_MFOS12_Msk (0x1ul << SYS_GPH_MFOS_MFOS12_Pos) |
SYS_T::GPH_MFOS: MFOS12 Mask
| #define SYS_GPH_MFOS_MFOS12_Pos (12) |
SYS_T::GPH_MFOS: MFOS12 Position
| #define SYS_GPH_MFOS_MFOS13_Msk (0x1ul << SYS_GPH_MFOS_MFOS13_Pos) |
SYS_T::GPH_MFOS: MFOS13 Mask
| #define SYS_GPH_MFOS_MFOS13_Pos (13) |
SYS_T::GPH_MFOS: MFOS13 Position
| #define SYS_GPH_MFOS_MFOS14_Msk (0x1ul << SYS_GPH_MFOS_MFOS14_Pos) |
SYS_T::GPH_MFOS: MFOS14 Mask
| #define SYS_GPH_MFOS_MFOS14_Pos (14) |
SYS_T::GPH_MFOS: MFOS14 Position
| #define SYS_GPH_MFOS_MFOS15_Msk (0x1ul << SYS_GPH_MFOS_MFOS15_Pos) |
SYS_T::GPH_MFOS: MFOS15 Mask
| #define SYS_GPH_MFOS_MFOS15_Pos (15) |
SYS_T::GPH_MFOS: MFOS15 Position
| #define SYS_GPH_MFOS_MFOS1_Msk (0x1ul << SYS_GPH_MFOS_MFOS1_Pos) |
SYS_T::GPH_MFOS: MFOS1 Mask
| #define SYS_GPH_MFOS_MFOS1_Pos (1) |
SYS_T::GPH_MFOS: MFOS1 Position
| #define SYS_GPH_MFOS_MFOS2_Msk (0x1ul << SYS_GPH_MFOS_MFOS2_Pos) |
SYS_T::GPH_MFOS: MFOS2 Mask
| #define SYS_GPH_MFOS_MFOS2_Pos (2) |
SYS_T::GPH_MFOS: MFOS2 Position
| #define SYS_GPH_MFOS_MFOS3_Msk (0x1ul << SYS_GPH_MFOS_MFOS3_Pos) |
SYS_T::GPH_MFOS: MFOS3 Mask
| #define SYS_GPH_MFOS_MFOS3_Pos (3) |
SYS_T::GPH_MFOS: MFOS3 Position
| #define SYS_GPH_MFOS_MFOS4_Msk (0x1ul << SYS_GPH_MFOS_MFOS4_Pos) |
SYS_T::GPH_MFOS: MFOS4 Mask
| #define SYS_GPH_MFOS_MFOS4_Pos (4) |
SYS_T::GPH_MFOS: MFOS4 Position
| #define SYS_GPH_MFOS_MFOS5_Msk (0x1ul << SYS_GPH_MFOS_MFOS5_Pos) |
SYS_T::GPH_MFOS: MFOS5 Mask
| #define SYS_GPH_MFOS_MFOS5_Pos (5) |
SYS_T::GPH_MFOS: MFOS5 Position
| #define SYS_GPH_MFOS_MFOS6_Msk (0x1ul << SYS_GPH_MFOS_MFOS6_Pos) |
SYS_T::GPH_MFOS: MFOS6 Mask
| #define SYS_GPH_MFOS_MFOS6_Pos (6) |
SYS_T::GPH_MFOS: MFOS6 Position
| #define SYS_GPH_MFOS_MFOS7_Msk (0x1ul << SYS_GPH_MFOS_MFOS7_Pos) |
SYS_T::GPH_MFOS: MFOS7 Mask
| #define SYS_GPH_MFOS_MFOS7_Pos (7) |
SYS_T::GPH_MFOS: MFOS7 Position
| #define SYS_GPH_MFOS_MFOS8_Msk (0x1ul << SYS_GPH_MFOS_MFOS8_Pos) |
SYS_T::GPH_MFOS: MFOS8 Mask
| #define SYS_GPH_MFOS_MFOS8_Pos (8) |
SYS_T::GPH_MFOS: MFOS8 Position
| #define SYS_GPH_MFOS_MFOS9_Msk (0x1ul << SYS_GPH_MFOS_MFOS9_Pos) |
SYS_T::GPH_MFOS: MFOS9 Mask
| #define SYS_GPH_MFOS_MFOS9_Pos (9) |
SYS_T::GPH_MFOS: MFOS9 Position
| #define SYS_GPH_MFPH_PH10MFP_Msk (0xful << SYS_GPH_MFPH_PH10MFP_Pos) |
SYS_T::GPH_MFPH: PH10MFP Mask
| #define SYS_GPH_MFPH_PH10MFP_Pos (8) |
SYS_T::GPH_MFPH: PH10MFP Position
| #define SYS_GPH_MFPH_PH11MFP_Msk (0xful << SYS_GPH_MFPH_PH11MFP_Pos) |
SYS_T::GPH_MFPH: PH11MFP Mask
| #define SYS_GPH_MFPH_PH11MFP_Pos (12) |
SYS_T::GPH_MFPH: PH11MFP Position
| #define SYS_GPH_MFPH_PH12MFP_Msk (0xful << SYS_GPH_MFPH_PH12MFP_Pos) |
SYS_T::GPH_MFPH: PH12MFP Mask
| #define SYS_GPH_MFPH_PH12MFP_Pos (16) |
SYS_T::GPH_MFPH: PH12MFP Position
| #define SYS_GPH_MFPH_PH13MFP_Msk (0xful << SYS_GPH_MFPH_PH13MFP_Pos) |
SYS_T::GPH_MFPH: PH13MFP Mask
| #define SYS_GPH_MFPH_PH13MFP_Pos (20) |
SYS_T::GPH_MFPH: PH13MFP Position
| #define SYS_GPH_MFPH_PH14MFP_Msk (0xful << SYS_GPH_MFPH_PH14MFP_Pos) |
SYS_T::GPH_MFPH: PH14MFP Mask
| #define SYS_GPH_MFPH_PH14MFP_Pos (24) |
SYS_T::GPH_MFPH: PH14MFP Position
| #define SYS_GPH_MFPH_PH15MFP_Msk (0xful << SYS_GPH_MFPH_PH15MFP_Pos) |
SYS_T::GPH_MFPH: PH15MFP Mask
| #define SYS_GPH_MFPH_PH15MFP_Pos (28) |
SYS_T::GPH_MFPH: PH15MFP Position
| #define SYS_GPH_MFPH_PH8MFP_Msk (0xful << SYS_GPH_MFPH_PH8MFP_Pos) |
SYS_T::GPH_MFPH: PH8MFP Mask
| #define SYS_GPH_MFPH_PH8MFP_Pos (0) |
SYS_T::GPH_MFPH: PH8MFP Position
| #define SYS_GPH_MFPH_PH9MFP_Msk (0xful << SYS_GPH_MFPH_PH9MFP_Pos) |
SYS_T::GPH_MFPH: PH9MFP Mask
| #define SYS_GPH_MFPH_PH9MFP_Pos (4) |
SYS_T::GPH_MFPH: PH9MFP Position
| #define SYS_GPH_MFPL_PH0MFP_Msk (0xful << SYS_GPH_MFPL_PH0MFP_Pos) |
SYS_T::GPH_MFPL: PH0MFP Mask
| #define SYS_GPH_MFPL_PH0MFP_Pos (0) |
SYS_T::GPH_MFPL: PH0MFP Position
| #define SYS_GPH_MFPL_PH1MFP_Msk (0xful << SYS_GPH_MFPL_PH1MFP_Pos) |
SYS_T::GPH_MFPL: PH1MFP Mask
| #define SYS_GPH_MFPL_PH1MFP_Pos (4) |
SYS_T::GPH_MFPL: PH1MFP Position
| #define SYS_GPH_MFPL_PH2MFP_Msk (0xful << SYS_GPH_MFPL_PH2MFP_Pos) |
SYS_T::GPH_MFPL: PH2MFP Mask
| #define SYS_GPH_MFPL_PH2MFP_Pos (8) |
SYS_T::GPH_MFPL: PH2MFP Position
| #define SYS_GPH_MFPL_PH3MFP_Msk (0xful << SYS_GPH_MFPL_PH3MFP_Pos) |
SYS_T::GPH_MFPL: PH3MFP Mask
| #define SYS_GPH_MFPL_PH3MFP_Pos (12) |
SYS_T::GPH_MFPL: PH3MFP Position
| #define SYS_GPH_MFPL_PH4MFP_Msk (0xful << SYS_GPH_MFPL_PH4MFP_Pos) |
SYS_T::GPH_MFPL: PH4MFP Mask
| #define SYS_GPH_MFPL_PH4MFP_Pos (16) |
SYS_T::GPH_MFPL: PH4MFP Position
| #define SYS_GPH_MFPL_PH5MFP_Msk (0xful << SYS_GPH_MFPL_PH5MFP_Pos) |
SYS_T::GPH_MFPL: PH5MFP Mask
| #define SYS_GPH_MFPL_PH5MFP_Pos (20) |
SYS_T::GPH_MFPL: PH5MFP Position
| #define SYS_GPH_MFPL_PH6MFP_Msk (0xful << SYS_GPH_MFPL_PH6MFP_Pos) |
SYS_T::GPH_MFPL: PH6MFP Mask
| #define SYS_GPH_MFPL_PH6MFP_Pos (24) |
SYS_T::GPH_MFPL: PH6MFP Position
| #define SYS_GPH_MFPL_PH7MFP_Msk (0xful << SYS_GPH_MFPL_PH7MFP_Pos) |
SYS_T::GPH_MFPL: PH7MFP Mask
| #define SYS_GPH_MFPL_PH7MFP_Pos (28) |
SYS_T::GPH_MFPL: PH7MFP Position
| #define SYS_HIRCTCTL_BOUNDARY_Msk (0x1ful << SYS_HIRCTCTL_BOUNDARY_Pos) |
SYS_T::HIRCTCTL: BOUNDARY Mask
| #define SYS_HIRCTCTL_BOUNDARY_Pos (16) |
SYS_T::HIRCTCTL: BOUNDARY Position
| #define SYS_HIRCTCTL_BOUNDEN_Msk (0x1ul << SYS_HIRCTCTL_BOUNDEN_Pos) |
SYS_T::HIRCTCTL: BOUNDEN Mask
| #define SYS_HIRCTCTL_BOUNDEN_Pos (9) |
SYS_T::HIRCTCTL: BOUNDEN Position
| #define SYS_HIRCTCTL_CESTOPEN_Msk (0x1ul << SYS_HIRCTCTL_CESTOPEN_Pos) |
SYS_T::HIRCTCTL: CESTOPEN Mask
| #define SYS_HIRCTCTL_CESTOPEN_Pos (8) |
SYS_T::HIRCTCTL: CESTOPEN Position
| #define SYS_HIRCTCTL_FREQSEL_Msk (0x3ul << SYS_HIRCTCTL_FREQSEL_Pos) |
SYS_T::HIRCTCTL: FREQSEL Mask
| #define SYS_HIRCTCTL_FREQSEL_Pos (0) |
SYS_T::HIRCTCTL: FREQSEL Position
| #define SYS_HIRCTCTL_LOOPSEL_Msk (0x3ul << SYS_HIRCTCTL_LOOPSEL_Pos) |
SYS_T::HIRCTCTL: LOOPSEL Mask
| #define SYS_HIRCTCTL_LOOPSEL_Pos (4) |
SYS_T::HIRCTCTL: LOOPSEL Position
| #define SYS_HIRCTCTL_REFCKSEL_Msk (0x1ul << SYS_HIRCTCTL_REFCKSEL_Pos) |
SYS_T::HIRCTCTL: REFCKSEL Mask
| #define SYS_HIRCTCTL_REFCKSEL_Pos (10) |
SYS_T::HIRCTCTL: REFCKSEL Position
| #define SYS_HIRCTCTL_RETRYCNT_Msk (0x3ul << SYS_HIRCTCTL_RETRYCNT_Pos) |
SYS_T::HIRCTCTL: RETRYCNT Mask
| #define SYS_HIRCTCTL_RETRYCNT_Pos (6) |
SYS_T::HIRCTCTL: RETRYCNT Position
| #define SYS_HIRCTIEN_CLKEIEN_Msk (0x1ul << SYS_HIRCTIEN_CLKEIEN_Pos) |
SYS_T::HIRCTIEN: CLKEIEN Mask
| #define SYS_HIRCTIEN_CLKEIEN_Pos (2) |
SYS_T::HIRCTIEN: CLKEIEN Position
| #define SYS_HIRCTIEN_TFAILIEN_Msk (0x1ul << SYS_HIRCTIEN_TFAILIEN_Pos) |
SYS_T::HIRCTIEN: TFAILIEN Mask
| #define SYS_HIRCTIEN_TFAILIEN_Pos (1) |
SYS_T::HIRCTIEN: TFAILIEN Position
| #define SYS_HIRCTISTS_CLKERRIF_Msk (0x1ul << SYS_HIRCTISTS_CLKERRIF_Pos) |
SYS_T::HIRCTISTS: CLKERRIF Mask
| #define SYS_HIRCTISTS_CLKERRIF_Pos (2) |
SYS_T::HIRCTISTS: CLKERRIF Position
| #define SYS_HIRCTISTS_FREQLOCK_Msk (0x1ul << SYS_HIRCTISTS_FREQLOCK_Pos) |
SYS_T::HIRCTISTS: FREQLOCK Mask
| #define SYS_HIRCTISTS_FREQLOCK_Pos (0) |
SYS_T::HIRCTISTS: FREQLOCK Position
| #define SYS_HIRCTISTS_OVBDIF_Msk (0x1ul << SYS_HIRCTISTS_OVBDIF_Pos) |
SYS_T::HIRCTISTS: OVBDIF Mask
| #define SYS_HIRCTISTS_OVBDIF_Pos (3) |
SYS_T::HIRCTISTS: OVBDIF Position
| #define SYS_HIRCTISTS_TFAILIF_Msk (0x1ul << SYS_HIRCTISTS_TFAILIF_Pos) |
SYS_T::HIRCTISTS: TFAILIF Mask
| #define SYS_HIRCTISTS_TFAILIF_Pos (1) |
SYS_T::HIRCTISTS: TFAILIF Position
| #define SYS_IPRST0_CCAPRST_Msk (0x1ul << SYS_IPRST0_CCAPRST_Pos) |
SYS_T::IPRST0: CCAPRST Mask
| #define SYS_IPRST0_CCAPRST_Pos (8) |
SYS_T::IPRST0: CCAPRST Position
| #define SYS_IPRST0_CHIPRST_Msk (0x1ul << SYS_IPRST0_CHIPRST_Pos) |
SYS_T::IPRST0: CHIPRST Mask
| #define SYS_IPRST0_CHIPRST_Pos (0) |
SYS_T::IPRST0: CHIPRST Position
| #define SYS_IPRST0_CPURST_Msk (0x1ul << SYS_IPRST0_CPURST_Pos) |
SYS_T::IPRST0: CPURST Mask
| #define SYS_IPRST0_CPURST_Pos (1) |
SYS_T::IPRST0: CPURST Position
| #define SYS_IPRST0_CRCRST_Msk (0x1ul << SYS_IPRST0_CRCRST_Pos) |
SYS_T::IPRST0: CRCRST Mask
| #define SYS_IPRST0_CRCRST_Pos (7) |
SYS_T::IPRST0: CRCRST Position
| #define SYS_IPRST0_CRPTRST_Msk (0x1ul << SYS_IPRST0_CRPTRST_Pos) |
SYS_T::IPRST0: CRPTRST Mask
| #define SYS_IPRST0_CRPTRST_Pos (12) |
SYS_T::IPRST0: CRPTRST Position
| #define SYS_IPRST0_EBIRST_Msk (0x1ul << SYS_IPRST0_EBIRST_Pos) |
SYS_T::IPRST0: EBIRST Mask
| #define SYS_IPRST0_EBIRST_Pos (3) |
SYS_T::IPRST0: EBIRST Position
| #define SYS_IPRST0_EMACRST_Msk (0x1ul << SYS_IPRST0_EMACRST_Pos) |
SYS_T::IPRST0: EMACRST Mask
| #define SYS_IPRST0_EMACRST_Pos (5) |
SYS_T::IPRST0: EMACRST Position
| #define SYS_IPRST0_HSUSBDRST_Msk (0x1ul << SYS_IPRST0_HSUSBDRST_Pos) |
SYS_T::IPRST0: HSUSBDRST Mask
| #define SYS_IPRST0_HSUSBDRST_Pos (10) |
SYS_T::IPRST0: HSUSBDRST Position
| #define SYS_IPRST0_PDMARST_Msk (0x1ul << SYS_IPRST0_PDMARST_Pos) |
SYS_T::IPRST0: PDMARST Mask
| #define SYS_IPRST0_PDMARST_Pos (2) |
SYS_T::IPRST0: PDMARST Position
| #define SYS_IPRST0_SDH0RST_Msk (0x1ul << SYS_IPRST0_SDH0RST_Pos) |
SYS_T::IPRST0: SDH0RST Mask
| #define SYS_IPRST0_SDH0RST_Pos (6) |
SYS_T::IPRST0: SDH0RST Position
| #define SYS_IPRST0_SDH1RST_Msk (0x1ul << SYS_IPRST0_SDH1RST_Pos) |
SYS_T::IPRST0: SDH1RST Mask
| #define SYS_IPRST0_SDH1RST_Pos (17) |
SYS_T::IPRST0: SDH1RST Position
| #define SYS_IPRST0_SPIMRST_Msk (0x1ul << SYS_IPRST0_SPIMRST_Pos) |
SYS_T::IPRST0: SPIMRST Mask
| #define SYS_IPRST0_SPIMRST_Pos (14) |
SYS_T::IPRST0: SPIMRST Position
| #define SYS_IPRST0_USBHRST_Msk (0x1ul << SYS_IPRST0_USBHRST_Pos) |
SYS_T::IPRST0: USBHRST Mask
| #define SYS_IPRST0_USBHRST_Pos (16) |
SYS_T::IPRST0: USBHRST Position
| #define SYS_IPRST1_ACMP01RST_Msk (0x1ul << SYS_IPRST1_ACMP01RST_Pos) |
SYS_T::IPRST1: ACMP01RST Mask
| #define SYS_IPRST1_ACMP01RST_Pos (7) |
SYS_T::IPRST1: ACMP01RST Position
| #define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) |
SYS_T::IPRST1: CAN0RST Mask
| #define SYS_IPRST1_CAN0RST_Pos (24) |
SYS_T::IPRST1: CAN0RST Position
| #define SYS_IPRST1_CAN1RST_Msk (0x1ul << SYS_IPRST1_CAN1RST_Pos) |
SYS_T::IPRST1: CAN1RST Mask
| #define SYS_IPRST1_CAN1RST_Pos (25) |
SYS_T::IPRST1: CAN1RST Position
| #define SYS_IPRST1_EADCRST_Msk (0x1ul << SYS_IPRST1_EADCRST_Pos) |
SYS_T::IPRST1: EADCRST Mask
| #define SYS_IPRST1_EADCRST_Pos (28) |
SYS_T::IPRST1: EADCRST Position
| #define SYS_IPRST1_GPIORST_Msk (0x1ul << SYS_IPRST1_GPIORST_Pos) |
SYS_T::IPRST1: GPIORST Mask
| #define SYS_IPRST1_GPIORST_Pos (1) |
SYS_T::IPRST1: GPIORST Position
| #define SYS_IPRST1_HSOTGRST_Msk (0x1ul << SYS_IPRST1_HSOTGRST_Pos) |
SYS_T::IPRST1: HSOTGRST Mask
| #define SYS_IPRST1_HSOTGRST_Pos (30) |
SYS_T::IPRST1: HSOTGRST Position
| #define SYS_IPRST1_I2C0RST_Msk (0x1ul << SYS_IPRST1_I2C0RST_Pos) |
SYS_T::IPRST1: I2C0RST Mask
| #define SYS_IPRST1_I2C0RST_Pos (8) |
SYS_T::IPRST1: I2C0RST Position
| #define SYS_IPRST1_I2C1RST_Msk (0x1ul << SYS_IPRST1_I2C1RST_Pos) |
SYS_T::IPRST1: I2C1RST Mask
| #define SYS_IPRST1_I2C1RST_Pos (9) |
SYS_T::IPRST1: I2C1RST Position
| #define SYS_IPRST1_I2S0RST_Msk (0x1ul << SYS_IPRST1_I2S0RST_Pos) |
SYS_T::IPRST1: I2S0RST Mask
| #define SYS_IPRST1_I2S0RST_Pos (29) |
SYS_T::IPRST1: I2S0RST Position
| #define SYS_IPRST1_OTGRST_Msk (0x1ul << SYS_IPRST1_OTGRST_Pos) |
SYS_T::IPRST1: OTGRST Mask
| #define SYS_IPRST1_OTGRST_Pos (26) |
SYS_T::IPRST1: OTGRST Position
| #define SYS_IPRST1_QSPI0RST_Msk (0x1ul << SYS_IPRST1_QSPI0RST_Pos) |
SYS_T::IPRST1: QSPI0RST Mask
| #define SYS_IPRST1_QSPI0RST_Pos (12) |
SYS_T::IPRST1: QSPI0RST Position
| #define SYS_IPRST1_SPI0RST_Msk (0x1ul << SYS_IPRST1_SPI0RST_Pos) |
SYS_T::IPRST1: SPI0RST Mask
| #define SYS_IPRST1_SPI0RST_Pos (13) |
SYS_T::IPRST1: SPI0RST Position
| #define SYS_IPRST1_SPI1RST_Msk (0x1ul << SYS_IPRST1_SPI1RST_Pos) |
SYS_T::IPRST1: SPI1RST Mask
| #define SYS_IPRST1_SPI1RST_Pos (14) |
SYS_T::IPRST1: SPI1RST Position
| #define SYS_IPRST1_SPI2RST_Msk (0x1ul << SYS_IPRST1_SPI2RST_Pos) |
SYS_T::IPRST1: SPI2RST Mask
| #define SYS_IPRST1_SPI2RST_Pos (15) |
SYS_T::IPRST1: SPI2RST Position
| #define SYS_IPRST1_TMR0RST_Msk (0x1ul << SYS_IPRST1_TMR0RST_Pos) |
SYS_T::IPRST1: TMR0RST Mask
| #define SYS_IPRST1_TMR0RST_Pos (2) |
SYS_T::IPRST1: TMR0RST Position
| #define SYS_IPRST1_TMR1RST_Msk (0x1ul << SYS_IPRST1_TMR1RST_Pos) |
SYS_T::IPRST1: TMR1RST Mask
| #define SYS_IPRST1_TMR1RST_Pos (3) |
SYS_T::IPRST1: TMR1RST Position
| #define SYS_IPRST1_TMR2RST_Msk (0x1ul << SYS_IPRST1_TMR2RST_Pos) |
SYS_T::IPRST1: TMR2RST Mask
| #define SYS_IPRST1_TMR2RST_Pos (4) |
SYS_T::IPRST1: TMR2RST Position
| #define SYS_IPRST1_TMR3RST_Msk (0x1ul << SYS_IPRST1_TMR3RST_Pos) |
SYS_T::IPRST1: TMR3RST Mask
| #define SYS_IPRST1_TMR3RST_Pos (5) |
SYS_T::IPRST1: TMR3RST Position
| #define SYS_IPRST1_TRNGRST_Msk (0x1ul << SYS_IPRST1_TRNGRST_Pos) |
SYS_T::IPRST1: TRNGRST Mask
| #define SYS_IPRST1_TRNGRST_Pos (31) |
SYS_T::IPRST1: TRNGRST Position
| #define SYS_IPRST1_UART0RST_Msk (0x1ul << SYS_IPRST1_UART0RST_Pos) |
SYS_T::IPRST1: UART0RST Mask
| #define SYS_IPRST1_UART0RST_Pos (16) |
SYS_T::IPRST1: UART0RST Position
| #define SYS_IPRST1_UART1RST_Msk (0x1ul << SYS_IPRST1_UART1RST_Pos) |
SYS_T::IPRST1: UART1RST Mask
| #define SYS_IPRST1_UART1RST_Pos (17) |
SYS_T::IPRST1: UART1RST Position
| #define SYS_IPRST1_UART2RST_Msk (0x1ul << SYS_IPRST1_UART2RST_Pos) |
SYS_T::IPRST1: UART2RST Mask
| #define SYS_IPRST1_UART2RST_Pos (18) |
SYS_T::IPRST1: UART2RST Position
| #define SYS_IPRST1_UART3RST_Msk (0x1ul << SYS_IPRST1_UART3RST_Pos) |
SYS_T::IPRST1: UART3RST Mask
| #define SYS_IPRST1_UART3RST_Pos (19) |
SYS_T::IPRST1: UART3RST Position
| #define SYS_IPRST1_UART4RST_Msk (0x1ul << SYS_IPRST1_UART4RST_Pos) |
SYS_T::IPRST1: UART4RST Mask
| #define SYS_IPRST1_UART4RST_Pos (20) |
SYS_T::IPRST1: UART4RST Position
| #define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) |
SYS_T::IPRST1: UART5RST Mask
| #define SYS_IPRST1_UART5RST_Pos (21) |
SYS_T::IPRST1: UART5RST Position
| #define SYS_IPRST1_UART6RST_Msk (0x1ul << SYS_IPRST1_UART6RST_Pos) |
SYS_T::IPRST1: UART6RST Mask
| #define SYS_IPRST1_UART6RST_Pos (22) |
SYS_T::IPRST1: UART6RST Position
| #define SYS_IPRST1_UART7RST_Msk (0x1ul << SYS_IPRST1_UART7RST_Pos) |
SYS_T::IPRST1: UART7RST Mask
| #define SYS_IPRST1_UART7RST_Pos (23) |
SYS_T::IPRST1: UART7RST Position
| #define SYS_IPRST1_USBDRST_Msk (0x1ul << SYS_IPRST1_USBDRST_Pos) |
SYS_T::IPRST1: USBDRST Mask
| #define SYS_IPRST1_USBDRST_Pos (27) |
SYS_T::IPRST1: USBDRST Position
| #define SYS_IPRST2_BPWM0RST_Msk (0x1ul << SYS_IPRST2_BPWM0RST_Pos) |
SYS_T::IPRST2: BPWM0RST Mask
| #define SYS_IPRST2_BPWM0RST_Pos (18) |
SYS_T::IPRST2: BPWM0RST Position
| #define SYS_IPRST2_BPWM1RST_Msk (0x1ul << SYS_IPRST2_BPWM1RST_Pos) |
SYS_T::IPRST2: BPWM1RST Mask
| #define SYS_IPRST2_BPWM1RST_Pos (19) |
SYS_T::IPRST2: BPWM1RST Position
| #define SYS_IPRST2_DACRST_Msk (0x1ul << SYS_IPRST2_DACRST_Pos) |
SYS_T::IPRST2: DACRST Mask
| #define SYS_IPRST2_DACRST_Pos (12) |
SYS_T::IPRST2: DACRST Position
| #define SYS_IPRST2_EADC1RST_Msk (0x1ul << SYS_IPRST2_EADC1RST_Pos) |
SYS_T::IPRST2: EADC1RST Mask
| #define SYS_IPRST2_EADC1RST_Pos (31) |
SYS_T::IPRST2: EADC1RST Position
| #define SYS_IPRST2_ECAP0RST_Msk (0x1ul << SYS_IPRST2_ECAP0RST_Pos) |
SYS_T::IPRST2: ECAP0RST Mask
| #define SYS_IPRST2_ECAP0RST_Pos (26) |
SYS_T::IPRST2: ECAP0RST Position
| #define SYS_IPRST2_ECAP1RST_Msk (0x1ul << SYS_IPRST2_ECAP1RST_Pos) |
SYS_T::IPRST2: ECAP1RST Mask
| #define SYS_IPRST2_ECAP1RST_Pos (27) |
SYS_T::IPRST2: ECAP1RST Position
| #define SYS_IPRST2_EPWM0RST_Msk (0x1ul << SYS_IPRST2_EPWM0RST_Pos) |
SYS_T::IPRST2: EPWM0RST Mask
| #define SYS_IPRST2_EPWM0RST_Pos (16) |
SYS_T::IPRST2: EPWM0RST Position
| #define SYS_IPRST2_EPWM1RST_Msk (0x1ul << SYS_IPRST2_EPWM1RST_Pos) |
SYS_T::IPRST2: EPWM1RST Mask
| #define SYS_IPRST2_EPWM1RST_Pos (17) |
SYS_T::IPRST2: EPWM1RST Position
| #define SYS_IPRST2_OPARST_Msk (0x1ul << SYS_IPRST2_OPARST_Pos) |
SYS_T::IPRST2: OPARST Mask
| #define SYS_IPRST2_OPARST_Pos (30) |
SYS_T::IPRST2: OPARST Position
| #define SYS_IPRST2_QEI0RST_Msk (0x1ul << SYS_IPRST2_QEI0RST_Pos) |
SYS_T::IPRST2: QEI0RST Mask
| #define SYS_IPRST2_QEI0RST_Pos (22) |
SYS_T::IPRST2: QEI0RST Position
| #define SYS_IPRST2_QEI1RST_Msk (0x1ul << SYS_IPRST2_QEI1RST_Pos) |
SYS_T::IPRST2: QEI1RST Mask
| #define SYS_IPRST2_QEI1RST_Pos (23) |
SYS_T::IPRST2: QEI1RST Position
| #define SYS_IPRST2_QSPI1RST_Msk (0x1ul << SYS_IPRST2_QSPI1RST_Pos) |
SYS_T::IPRST2: QSPI1RST Mask
| #define SYS_IPRST2_QSPI1RST_Pos (4) |
SYS_T::IPRST2: QSPI1RST Position
| #define SYS_IPRST2_SC0RST_Msk (0x1ul << SYS_IPRST2_SC0RST_Pos) |
SYS_T::IPRST2: SC0RST Mask
| #define SYS_IPRST2_SC0RST_Pos (0) |
SYS_T::IPRST2: SC0RST Position
| #define SYS_IPRST2_SC1RST_Msk (0x1ul << SYS_IPRST2_SC1RST_Pos) |
SYS_T::IPRST2: SC1RST Mask
| #define SYS_IPRST2_SC1RST_Pos (1) |
SYS_T::IPRST2: SC1RST Position
| #define SYS_IPRST2_SC2RST_Msk (0x1ul << SYS_IPRST2_SC2RST_Pos) |
SYS_T::IPRST2: SC2RST Mask
| #define SYS_IPRST2_SC2RST_Pos (2) |
SYS_T::IPRST2: SC2RST Position
| #define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) |
SYS_T::IPRST2: SPI3RST Mask
| #define SYS_IPRST2_SPI3RST_Pos (6) |
SYS_T::IPRST2: SPI3RST Position
| #define SYS_IRCTCTL_CESTOPEN_Msk (0x1ul << SYS_IRCTCTL_CESTOPEN_Pos) |
SYS_T::IRCTCTL: CESTOPEN Mask
| #define SYS_IRCTCTL_CESTOPEN_Pos (8) |
SYS_T::IRCTCTL: CESTOPEN Position
| #define SYS_IRCTCTL_FREQSEL_Msk (0x3ul << SYS_IRCTCTL_FREQSEL_Pos) |
SYS_T::IRCTCTL: FREQSEL Mask
| #define SYS_IRCTCTL_FREQSEL_Pos (0) |
SYS_T::IRCTCTL: FREQSEL Position
| #define SYS_IRCTCTL_LOOPSEL_Msk (0x3ul << SYS_IRCTCTL_LOOPSEL_Pos) |
SYS_T::IRCTCTL: LOOPSEL Mask
| #define SYS_IRCTCTL_LOOPSEL_Pos (4) |
SYS_T::IRCTCTL: LOOPSEL Position
| #define SYS_IRCTCTL_REFCKSEL_Msk (0x1ul << SYS_IRCTCTL_REFCKSEL_Pos) |
SYS_T::IRCTCTL: REFCKSEL Mask
| #define SYS_IRCTCTL_REFCKSEL_Pos (10) |
SYS_T::IRCTCTL: REFCKSEL Position
| #define SYS_IRCTCTL_RETRYCNT_Msk (0x3ul << SYS_IRCTCTL_RETRYCNT_Pos) |
SYS_T::IRCTCTL: RETRYCNT Mask
| #define SYS_IRCTCTL_RETRYCNT_Pos (6) |
SYS_T::IRCTCTL: RETRYCNT Position
| #define SYS_IRCTIEN_CLKEIEN_Msk (0x1ul << SYS_IRCTIEN_CLKEIEN_Pos) |
SYS_T::IRCTIEN: CLKEIEN Mask
| #define SYS_IRCTIEN_CLKEIEN_Pos (2) |
SYS_T::IRCTIEN: CLKEIEN Position
| #define SYS_IRCTIEN_TFAILIEN_Msk (0x1ul << SYS_IRCTIEN_TFAILIEN_Pos) |
SYS_T::IRCTIEN: TFAILIEN Mask
| #define SYS_IRCTIEN_TFAILIEN_Pos (1) |
SYS_T::IRCTIEN: TFAILIEN Position
| #define SYS_IRCTISTS_CLKERRIF_Msk (0x1ul << SYS_IRCTISTS_CLKERRIF_Pos) |
SYS_T::IRCTISTS: CLKERRIF Mask
| #define SYS_IRCTISTS_CLKERRIF_Pos (2) |
SYS_T::IRCTISTS: CLKERRIF Position
| #define SYS_IRCTISTS_FREQLOCK_Msk (0x1ul << SYS_IRCTISTS_FREQLOCK_Pos) |
SYS_T::IRCTISTS: FREQLOCK Mask
| #define SYS_IRCTISTS_FREQLOCK_Pos (0) |
SYS_T::IRCTISTS: FREQLOCK Position
| #define SYS_IRCTISTS_TFAILIF_Msk (0x1ul << SYS_IRCTISTS_TFAILIF_Pos) |
SYS_T::IRCTISTS: TFAILIF Mask
| #define SYS_IRCTISTS_TFAILIF_Pos (1) |
SYS_T::IRCTISTS: TFAILIF Position
| #define SYS_IVSCTL_VBATUGEN_Msk (0x1ul << SYS_IVSCTL_VBATUGEN_Pos) |
SYS_T::IVSCTL: VBATUGEN Mask
| #define SYS_IVSCTL_VBATUGEN_Pos (1) |
SYS_T::IVSCTL: VBATUGEN Position
| #define SYS_IVSCTL_VTEMPEN_Msk (0x1ul << SYS_IVSCTL_VTEMPEN_Pos) |
SYS_T::IVSCTL: VTEMPEN Mask
| #define SYS_IVSCTL_VTEMPEN_Pos (0) |
SYS_T::IVSCTL: VTEMPEN Position
| #define SYS_PDID_PDID_Msk (0xfffffffful << SYS_PDID_PDID_Pos) |
SYS_T::PDID: PDID Mask
| #define SYS_PDID_PDID_Pos (0) |
@addtogroup SYS_CONST SYS Bit Field Definition Constant Definitions for SYS Controller
SYS_T::PDID: PDID Position
| #define SYS_PLCTL_LVSPRD_Msk (0xfful << SYS_PLCTL_LVSPRD_Pos) |
SYS_T::PLCTL: LVSPRD Mask
| #define SYS_PLCTL_LVSPRD_Pos (24) |
SYS_T::PLCTL: LVSPRD Position
| #define SYS_PLCTL_LVSSTEP_Msk (0x3ful << SYS_PLCTL_LVSSTEP_Pos) |
SYS_T::PLCTL: LVSSTEP Mask
| #define SYS_PLCTL_LVSSTEP_Pos (16) |
SYS_T::PLCTL: LVSSTEP Position
| #define SYS_PLCTL_PLSEL_Msk (0x3ul << SYS_PLCTL_PLSEL_Pos) |
SYS_T::PLCTL: PLSEL Mask
| #define SYS_PLCTL_PLSEL_Pos (0) |
SYS_T::PLCTL: PLSEL Position
| #define SYS_PLSTS_PLCBUSY_Msk (0x1ul << SYS_PLSTS_PLCBUSY_Pos) |
SYS_T::PLSTS: PLCBUSY Mask
| #define SYS_PLSTS_PLCBUSY_Pos (0) |
SYS_T::PLSTS: PLCBUSY Position
| #define SYS_PLSTS_PLSTATUS_Msk (0x3ul << SYS_PLSTS_PLSTATUS_Pos) |
SYS_T::PLSTS: PLSTATUS Mask
| #define SYS_PLSTS_PLSTATUS_Pos (8) |
SYS_T::PLSTS: PLSTATUS Position
| #define SYS_PORCTL_POROFF_Msk (0xfffful << SYS_PORCTL_POROFF_Pos) |
SYS_T::PORCTL: POROFF Mask
| #define SYS_PORCTL_POROFF_Pos (0) |
SYS_T::PORCTL: POROFF Position
| #define SYS_PORDISAN_POROFFAN_Msk (0xfffful << SYS_PORDISAN_POROFFAN_Pos) |
SYS_T::PORDISAN: POROFFAN Mask
| #define SYS_PORDISAN_POROFFAN_Pos (0) |
SYS_T::PORDISAN: POROFFAN Position
| #define SYS_REGLCTL_REGLCTL_Msk (0x1ul << SYS_REGLCTL_REGLCTL_Pos) |
SYS_T::REGLCTL: REGLCTL Mask
| #define SYS_REGLCTL_REGLCTL_Pos (0) |
SYS_T::REGLCTL: REGLCTL Position
| #define SYS_RSTSTS_BODRF_Msk (0x1ul << SYS_RSTSTS_BODRF_Pos) |
SYS_T::RSTSTS: BODRF Mask
| #define SYS_RSTSTS_BODRF_Pos (4) |
SYS_T::RSTSTS: BODRF Position
| #define SYS_RSTSTS_CPULKRF_Msk (0x1ul << SYS_RSTSTS_CPULKRF_Pos) |
SYS_T::RSTSTS: CPULKRF Mask
| #define SYS_RSTSTS_CPULKRF_Pos (8) |
SYS_T::RSTSTS: CPULKRF Position
| #define SYS_RSTSTS_CPURF_Msk (0x1ul << SYS_RSTSTS_CPURF_Pos) |
SYS_T::RSTSTS: CPURF Mask
| #define SYS_RSTSTS_CPURF_Pos (7) |
SYS_T::RSTSTS: CPURF Position
| #define SYS_RSTSTS_LVRF_Msk (0x1ul << SYS_RSTSTS_LVRF_Pos) |
SYS_T::RSTSTS: LVRF Mask
| #define SYS_RSTSTS_LVRF_Pos (3) |
SYS_T::RSTSTS: LVRF Position
| #define SYS_RSTSTS_PINRF_Msk (0x1ul << SYS_RSTSTS_PINRF_Pos) |
SYS_T::RSTSTS: PINRF Mask
| #define SYS_RSTSTS_PINRF_Pos (1) |
SYS_T::RSTSTS: PINRF Position
| #define SYS_RSTSTS_PORF_Msk (0x1ul << SYS_RSTSTS_PORF_Pos) |
SYS_T::RSTSTS: PORF Mask
| #define SYS_RSTSTS_PORF_Pos (0) |
SYS_T::RSTSTS: PORF Position
| #define SYS_RSTSTS_SYSRF_Msk (0x1ul << SYS_RSTSTS_SYSRF_Pos) |
SYS_T::RSTSTS: SYSRF Mask
| #define SYS_RSTSTS_SYSRF_Pos (5) |
SYS_T::RSTSTS: SYSRF Position
| #define SYS_RSTSTS_WDTRF_Msk (0x1ul << SYS_RSTSTS_WDTRF_Pos) |
SYS_T::RSTSTS: WDTRF Mask
| #define SYS_RSTSTS_WDTRF_Pos (2) |
SYS_T::RSTSTS: WDTRF Position
| #define SYS_SRAM_BISTCTL_CANBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CANBIST_Pos) |
SYS_T::SRAM_BISTCTL: CANBIST Mask
| #define SYS_SRAM_BISTCTL_CANBIST_Pos (3) |
SYS_T::SRAM_BISTCTL: CANBIST Position
| #define SYS_SRAM_BISTCTL_CRBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_CRBIST_Pos) |
SYS_T::SRAM_BISTCTL: CRBIST Mask
| #define SYS_SRAM_BISTCTL_CRBIST_Pos (2) |
SYS_T::SRAM_BISTCTL: CRBIST Position
| #define SYS_SRAM_BISTCTL_EMCBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_EMCBIST_Pos) |
SYS_T::SRAM_BISTCTL: EMCBIST Mask
| #define SYS_SRAM_BISTCTL_EMCBIST_Pos (6) |
SYS_T::SRAM_BISTCTL: EMCBIST Position
| #define SYS_SRAM_BISTCTL_PDMABIST_Msk (0x1ul << SYS_SRAM_BISTCTL_PDMABIST_Pos) |
SYS_T::SRAM_BISTCTL: PDMABIST Mask
| #define SYS_SRAM_BISTCTL_PDMABIST_Pos (7) |
SYS_T::SRAM_BISTCTL: PDMABIST Position
| #define SYS_SRAM_BISTCTL_SPIMBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_SPIMBIST_Pos) |
SYS_T::SRAM_BISTCTL: SPIMBIST Mask
| #define SYS_SRAM_BISTCTL_SPIMBIST_Pos (5) |
SYS_T::SRAM_BISTCTL: SPIMBIST Position
| #define SYS_SRAM_BISTCTL_SRB0S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S0_Pos) |
SYS_T::SRAM_BISTCTL: SRB0S0 Mask
| #define SYS_SRAM_BISTCTL_SRB0S0_Pos (16) |
SYS_T::SRAM_BISTCTL: SRB0S0 Position
| #define SYS_SRAM_BISTCTL_SRB0S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB0S1_Pos) |
SYS_T::SRAM_BISTCTL: SRB0S1 Mask
| #define SYS_SRAM_BISTCTL_SRB0S1_Pos (17) |
SYS_T::SRAM_BISTCTL: SRB0S1 Position
| #define SYS_SRAM_BISTCTL_SRB1S0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S0_Pos) |
SYS_T::SRAM_BISTCTL: SRB1S0 Mask
| #define SYS_SRAM_BISTCTL_SRB1S0_Pos (18) |
SYS_T::SRAM_BISTCTL: SRB1S0 Position
| #define SYS_SRAM_BISTCTL_SRB1S1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S1_Pos) |
SYS_T::SRAM_BISTCTL: SRB1S1 Mask
| #define SYS_SRAM_BISTCTL_SRB1S1_Pos (19) |
SYS_T::SRAM_BISTCTL: SRB1S1 Position
| #define SYS_SRAM_BISTCTL_SRB1S2_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S2_Pos) |
SYS_T::SRAM_BISTCTL: SRB1S2 Mask
| #define SYS_SRAM_BISTCTL_SRB1S2_Pos (20) |
SYS_T::SRAM_BISTCTL: SRB1S2 Position
| #define SYS_SRAM_BISTCTL_SRB1S3_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S3_Pos) |
SYS_T::SRAM_BISTCTL: SRB1S3 Mask
| #define SYS_SRAM_BISTCTL_SRB1S3_Pos (21) |
SYS_T::SRAM_BISTCTL: SRB1S3 Position
| #define SYS_SRAM_BISTCTL_SRB1S4_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S4_Pos) |
SYS_T::SRAM_BISTCTL: SRB1S4 Mask
| #define SYS_SRAM_BISTCTL_SRB1S4_Pos (22) |
SYS_T::SRAM_BISTCTL: SRB1S4 Position
| #define SYS_SRAM_BISTCTL_SRB1S5_Msk (0x1ul << SYS_SRAM_BISTCTL_SRB1S5_Pos) |
SYS_T::SRAM_BISTCTL: SRB1S5 Mask
| #define SYS_SRAM_BISTCTL_SRB1S5_Pos (23) |
SYS_T::SRAM_BISTCTL: SRB1S5 Position
| #define SYS_SRAM_BISTCTL_SRBIST0_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST0_Pos) |
SYS_T::SRAM_BISTCTL: SRBIST0 Mask
| #define SYS_SRAM_BISTCTL_SRBIST0_Pos (0) |
SYS_T::SRAM_BISTCTL: SRBIST0 Position
| #define SYS_SRAM_BISTCTL_SRBIST1_Msk (0x1ul << SYS_SRAM_BISTCTL_SRBIST1_Pos) |
SYS_T::SRAM_BISTCTL: SRBIST1 Mask
| #define SYS_SRAM_BISTCTL_SRBIST1_Pos (1) |
SYS_T::SRAM_BISTCTL: SRBIST1 Position
| #define SYS_SRAM_BISTCTL_USBBIST_Msk (0x1ul << SYS_SRAM_BISTCTL_USBBIST_Pos) |
SYS_T::SRAM_BISTCTL: USBBIST Mask
| #define SYS_SRAM_BISTCTL_USBBIST_Pos (4) |
SYS_T::SRAM_BISTCTL: USBBIST Position
| #define SYS_SRAM_BISTSTS_CANBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEF_Pos) |
SYS_T::SRAM_BISTSTS: CANBEF Mask
| #define SYS_SRAM_BISTSTS_CANBEF_Pos (3) |
SYS_T::SRAM_BISTSTS: CANBEF Position
| #define SYS_SRAM_BISTSTS_CANBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CANBEND_Pos) |
SYS_T::SRAM_BISTSTS: CANBEND Mask
| #define SYS_SRAM_BISTSTS_CANBEND_Pos (19) |
SYS_T::SRAM_BISTSTS: CANBEND Position
| #define SYS_SRAM_BISTSTS_CRBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBEND_Pos) |
SYS_T::SRAM_BISTSTS: CRBEND Mask
| #define SYS_SRAM_BISTSTS_CRBEND_Pos (18) |
SYS_T::SRAM_BISTSTS: CRBEND Position
| #define SYS_SRAM_BISTSTS_CRBISTEF_Msk (0x1ul << SYS_SRAM_BISTSTS_CRBISTEF_Pos) |
SYS_T::SRAM_BISTSTS: CRBISTEF Mask
| #define SYS_SRAM_BISTSTS_CRBISTEF_Pos (2) |
SYS_T::SRAM_BISTSTS: CRBISTEF Position
| #define SYS_SRAM_BISTSTS_SRBEND0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND0_Pos) |
SYS_T::SRAM_BISTSTS: SRBEND0 Mask
| #define SYS_SRAM_BISTSTS_SRBEND0_Pos (16) |
SYS_T::SRAM_BISTSTS: SRBEND0 Position
| #define SYS_SRAM_BISTSTS_SRBEND1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBEND1_Pos) |
SYS_T::SRAM_BISTSTS: SRBEND1 Mask
| #define SYS_SRAM_BISTSTS_SRBEND1_Pos (17) |
SYS_T::SRAM_BISTSTS: SRBEND1 Position
| #define SYS_SRAM_BISTSTS_SRBISTEF0_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF0_Pos) |
SYS_T::SRAM_BISTSTS: SRBISTEF0 Mask
| #define SYS_SRAM_BISTSTS_SRBISTEF0_Pos (0) |
SYS_T::SRAM_BISTSTS: SRBISTEF0 Position
| #define SYS_SRAM_BISTSTS_SRBISTEF1_Msk (0x1ul << SYS_SRAM_BISTSTS_SRBISTEF1_Pos) |
SYS_T::SRAM_BISTSTS: SRBISTEF1 Mask
| #define SYS_SRAM_BISTSTS_SRBISTEF1_Pos (1) |
SYS_T::SRAM_BISTSTS: SRBISTEF1 Position
| #define SYS_SRAM_BISTSTS_USBBEF_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEF_Pos) |
SYS_T::SRAM_BISTSTS: USBBEF Mask
| #define SYS_SRAM_BISTSTS_USBBEF_Pos (4) |
SYS_T::SRAM_BISTSTS: USBBEF Position
| #define SYS_SRAM_BISTSTS_USBBEND_Msk (0x1ul << SYS_SRAM_BISTSTS_USBBEND_Pos) |
SYS_T::SRAM_BISTSTS: USBBEND Mask
| #define SYS_SRAM_BISTSTS_USBBEND_Pos (20) |
SYS_T::SRAM_BISTSTS: USBBEND Position
| #define SYS_SRAM_ERRADDR_ERRADDR_Msk (0xfffffffful << SYS_SRAM_ERRADDR_ERRADDR_Pos) |
SYS_T::SRAM_ERRADDR: ERRADDR Mask
| #define SYS_SRAM_ERRADDR_ERRADDR_Pos (0) |
SYS_T::SRAM_ERRADDR: ERRADDR Position
| #define SYS_SRAM_INTCTL_PERRIEN_Msk (0x1ul << SYS_SRAM_INTCTL_PERRIEN_Pos) |
SYS_T::SRAM_INTCTL: PERRIEN Mask
| #define SYS_SRAM_INTCTL_PERRIEN_Pos (0) |
SYS_T::SRAM_INTCTL: PERRIEN Position
| #define SYS_SRAM_STATUS_PERRIF_Msk (0x1ul << SYS_SRAM_STATUS_PERRIF_Pos) |
SYS_T::SRAM_STATUS: PERRIF Mask
| #define SYS_SRAM_STATUS_PERRIF_Pos (0) |
SYS_T::SRAM_STATUS: PERRIF Position
| #define SYS_USBPHY_SBO_Msk (0x1ul << SYS_USBPHY_SBO_Pos) |
SYS_T::USBPHY: SBO Mask
| #define SYS_USBPHY_SBO_Pos (2) |
SYS_T::USBPHY: SBO Position
| #define SYS_USBPHY_USBEN_Msk (0x1ul << SYS_USBPHY_USBEN_Pos) |
SYS_T::USBPHY: USBEN Mask
| #define SYS_USBPHY_USBEN_Pos (8) |
SYS_T::USBPHY: USBEN Position
| #define SYS_USBPHY_USBROLE_Msk (0x3ul << SYS_USBPHY_USBROLE_Pos) |
SYS_T::USBPHY: USBROLE Mask
| #define SYS_USBPHY_USBROLE_Pos (0) |
SYS_T::USBPHY: USBROLE Position
| #define SYS_VREFCTL_PRELOAD_SEL_Msk (0x3ul << SYS_VREFCTL_PRELOAD_SEL_Pos) |
SYS_T::VREFCTL: PRELOAD_SEL Mask
| #define SYS_VREFCTL_PRELOAD_SEL_Pos (6) |
SYS_T::VREFCTL: PRELOAD_SEL Position
| #define SYS_VREFCTL_VREFCTL_Msk (0x1ful << SYS_VREFCTL_VREFCTL_Pos) |
SYS_T::VREFCTL: VREFCTL Mask
| #define SYS_VREFCTL_VREFCTL_Pos (0) |
SYS_T::VREFCTL: VREFCTL Position
| #define TIMER_ALTCTL_FUNCSEL_Msk (0x1ul << TIMER_ALTCTL_FUNCSEL_Pos) |
TIMER_T::ALTCTL: FUNCSEL Mask
Definition at line 862 of file timer_reg.h.
| #define TIMER_ALTCTL_FUNCSEL_Pos (0) |
TIMER_T::ALTCTL: FUNCSEL Position
Definition at line 861 of file timer_reg.h.
| #define TIMER_CAP_CAPDAT_Msk (0xfffffful << TIMER_CAP_CAPDAT_Pos) |
TIMER_T::CAP: CAPDAT Mask
Definition at line 811 of file timer_reg.h.
| #define TIMER_CAP_CAPDAT_Pos (0) |
TIMER_T::CAP: CAPDAT Position
Definition at line 810 of file timer_reg.h.
| #define TIMER_CMP_CMPDAT_Msk (0xfffffful << TIMER_CMP_CMPDAT_Pos) |
TIMER_T::CMP: CMPDAT Mask
Definition at line 796 of file timer_reg.h.
| #define TIMER_CMP_CMPDAT_Pos (0) |
TIMER_T::CMP: CMPDAT Position
Definition at line 795 of file timer_reg.h.
| #define TIMER_CNT_CNT_Msk (0xfffffful << TIMER_CNT_CNT_Pos) |
TIMER_T::CNT: CNT Mask
Definition at line 805 of file timer_reg.h.
| #define TIMER_CNT_CNT_Pos (0) |
TIMER_T::CNT: CNT Position
Definition at line 804 of file timer_reg.h.
| #define TIMER_CNT_RSTACT_Msk (0x1ul << TIMER_CNT_RSTACT_Pos) |
TIMER_T::CNT: RSTACT Mask
Definition at line 808 of file timer_reg.h.
| #define TIMER_CNT_RSTACT_Pos (31) |
TIMER_T::CNT: RSTACT Position
Definition at line 807 of file timer_reg.h.
| #define TIMER_CTL_ACTSTS_Msk (0x1ul << TIMER_CTL_ACTSTS_Pos) |
TIMER_T::CTL: ACTSTS Mask
Definition at line 781 of file timer_reg.h.
| #define TIMER_CTL_ACTSTS_Pos (25) |
TIMER_T::CTL: ACTSTS Position
Definition at line 780 of file timer_reg.h.
| #define TIMER_CTL_CAPSRC_Msk (0x1ul << TIMER_CTL_CAPSRC_Pos) |
TIMER_T::CTL: CAPSRC Mask
Definition at line 772 of file timer_reg.h.
| #define TIMER_CTL_CAPSRC_Pos (22) |
TIMER_T::CTL: CAPSRC Position
Definition at line 771 of file timer_reg.h.
| #define TIMER_CTL_CNTEN_Msk (0x1ul << TIMER_CTL_CNTEN_Pos) |
TIMER_T::CTL: CNTEN Mask
Definition at line 790 of file timer_reg.h.
| #define TIMER_CTL_CNTEN_Pos (30) |
TIMER_T::CTL: CNTEN Position
Definition at line 789 of file timer_reg.h.
| #define TIMER_CTL_EXTCNTEN_Msk (0x1ul << TIMER_CTL_EXTCNTEN_Pos) |
TIMER_T::CTL: EXTCNTEN Mask
Definition at line 778 of file timer_reg.h.
| #define TIMER_CTL_EXTCNTEN_Pos (24) |
TIMER_T::CTL: EXTCNTEN Position
Definition at line 777 of file timer_reg.h.
| #define TIMER_CTL_ICEDEBUG_Msk (0x1ul << TIMER_CTL_ICEDEBUG_Pos) |
TIMER_T::CTL: ICEDEBUG Mask
Definition at line 793 of file timer_reg.h.
| #define TIMER_CTL_ICEDEBUG_Pos (31) |
TIMER_T::CTL: ICEDEBUG Position
Definition at line 792 of file timer_reg.h.
| #define TIMER_CTL_INTEN_Msk (0x1ul << TIMER_CTL_INTEN_Pos) |
TIMER_T::CTL: INTEN Mask
Definition at line 787 of file timer_reg.h.
| #define TIMER_CTL_INTEN_Pos (29) |
TIMER_T::CTL: INTEN Position
Definition at line 786 of file timer_reg.h.
| #define TIMER_CTL_INTRGEN_Msk (0x1ul << TIMER_CTL_INTRGEN_Pos) |
TIMER_T::CTL: INTRGEN Mask
Definition at line 763 of file timer_reg.h.
| #define TIMER_CTL_INTRGEN_Pos (19) |
TIMER_T::CTL: INTRGEN Position
Definition at line 762 of file timer_reg.h.
| #define TIMER_CTL_OPMODE_Msk (0x3ul << TIMER_CTL_OPMODE_Pos) |
TIMER_T::CTL: OPMODE Mask
Definition at line 784 of file timer_reg.h.
| #define TIMER_CTL_OPMODE_Pos (27) |
TIMER_T::CTL: OPMODE Position
Definition at line 783 of file timer_reg.h.
| #define TIMER_CTL_PERIOSEL_Msk (0x1ul << TIMER_CTL_PERIOSEL_Pos) |
TIMER_T::CTL: PERIOSEL Mask
Definition at line 766 of file timer_reg.h.
| #define TIMER_CTL_PERIOSEL_Pos (20) |
TIMER_T::CTL: PERIOSEL Position
Definition at line 765 of file timer_reg.h.
| #define TIMER_CTL_PSC_Msk (0xfful << TIMER_CTL_PSC_Pos) |
TIMER_T::CTL: PSC Mask
Definition at line 760 of file timer_reg.h.
| #define TIMER_CTL_PSC_Pos (0) |
@addtogroup TIMER_CONST TIMER Bit Field Definition Constant Definitions for TIMER Controller
TIMER_T::CTL: PSC Position
Definition at line 759 of file timer_reg.h.
| #define TIMER_CTL_TGLPINSEL_Msk (0x1ul << TIMER_CTL_TGLPINSEL_Pos) |
TIMER_T::CTL: TGLPINSEL Mask
Definition at line 769 of file timer_reg.h.
| #define TIMER_CTL_TGLPINSEL_Pos (21) |
TIMER_T::CTL: TGLPINSEL Position
Definition at line 768 of file timer_reg.h.
| #define TIMER_CTL_WKEN_Msk (0x1ul << TIMER_CTL_WKEN_Pos) |
TIMER_T::CTL: WKEN Mask
Definition at line 775 of file timer_reg.h.
| #define TIMER_CTL_WKEN_Pos (23) |
TIMER_T::CTL: WKEN Position
Definition at line 774 of file timer_reg.h.
| #define TIMER_EINTSTS_CAPIF_Msk (0x1ul << TIMER_EINTSTS_CAPIF_Pos) |
TIMER_T::EINTSTS: CAPIF Mask
Definition at line 844 of file timer_reg.h.
| #define TIMER_EINTSTS_CAPIF_Pos (0) |
TIMER_T::EINTSTS: CAPIF Position
Definition at line 843 of file timer_reg.h.
| #define TIMER_EXTCTL_CAPDBEN_Msk (0x1ul << TIMER_EXTCTL_CAPDBEN_Pos) |
TIMER_T::EXTCTL: CAPDBEN Mask
Definition at line 826 of file timer_reg.h.
| #define TIMER_EXTCTL_CAPDBEN_Pos (6) |
TIMER_T::EXTCTL: CAPDBEN Position
Definition at line 825 of file timer_reg.h.
| #define TIMER_EXTCTL_CAPDIVSCL_Msk (0xful << TIMER_EXTCTL_CAPDIVSCL_Pos) |
TIMER_T::EXTCTL: CAPDIVSCL Mask
Definition at line 841 of file timer_reg.h.
| #define TIMER_EXTCTL_CAPDIVSCL_Pos (28) |
TIMER_T::EXTCTL: CAPDIVSCL Position
Definition at line 840 of file timer_reg.h.
| #define TIMER_EXTCTL_CAPEDGE_Msk (0x7ul << TIMER_EXTCTL_CAPEDGE_Pos) |
TIMER_T::EXTCTL: CAPEDGE Mask
Definition at line 835 of file timer_reg.h.
| #define TIMER_EXTCTL_CAPEDGE_Pos (12) |
TIMER_T::EXTCTL: CAPEDGE Position
Definition at line 834 of file timer_reg.h.
| #define TIMER_EXTCTL_CAPEN_Msk (0x1ul << TIMER_EXTCTL_CAPEN_Pos) |
TIMER_T::EXTCTL: CAPEN Mask
Definition at line 817 of file timer_reg.h.
| #define TIMER_EXTCTL_CAPEN_Pos (3) |
TIMER_T::EXTCTL: CAPEN Position
Definition at line 816 of file timer_reg.h.
| #define TIMER_EXTCTL_CAPFUNCS_Msk (0x1ul << TIMER_EXTCTL_CAPFUNCS_Pos) |
TIMER_T::EXTCTL: CAPFUNCS Mask
Definition at line 820 of file timer_reg.h.
| #define TIMER_EXTCTL_CAPFUNCS_Pos (4) |
TIMER_T::EXTCTL: CAPFUNCS Position
Definition at line 819 of file timer_reg.h.
| #define TIMER_EXTCTL_CAPIEN_Msk (0x1ul << TIMER_EXTCTL_CAPIEN_Pos) |
TIMER_T::EXTCTL: CAPIEN Mask
Definition at line 823 of file timer_reg.h.
| #define TIMER_EXTCTL_CAPIEN_Pos (5) |
TIMER_T::EXTCTL: CAPIEN Position
Definition at line 822 of file timer_reg.h.
| #define TIMER_EXTCTL_CNTDBEN_Msk (0x1ul << TIMER_EXTCTL_CNTDBEN_Pos) |
TIMER_T::EXTCTL: CNTDBEN Mask
Definition at line 829 of file timer_reg.h.
| #define TIMER_EXTCTL_CNTDBEN_Pos (7) |
TIMER_T::EXTCTL: CNTDBEN Position
Definition at line 828 of file timer_reg.h.
| #define TIMER_EXTCTL_CNTPHASE_Msk (0x1ul << TIMER_EXTCTL_CNTPHASE_Pos) |
TIMER_T::EXTCTL: CNTPHASE Mask
Definition at line 814 of file timer_reg.h.
| #define TIMER_EXTCTL_CNTPHASE_Pos (0) |
TIMER_T::EXTCTL: CNTPHASE Position
Definition at line 813 of file timer_reg.h.
| #define TIMER_EXTCTL_ECNTSSEL_Msk (0x1ul << TIMER_EXTCTL_ECNTSSEL_Pos) |
TIMER_T::EXTCTL: ECNTSSEL Mask
Definition at line 838 of file timer_reg.h.
| #define TIMER_EXTCTL_ECNTSSEL_Pos (16) |
TIMER_T::EXTCTL: ECNTSSEL Position
Definition at line 837 of file timer_reg.h.
| #define TIMER_EXTCTL_ICAPSEL_Msk (0x7ul << TIMER_EXTCTL_ICAPSEL_Pos) |
TIMER_T::EXTCTL: ICAPSEL Mask
Definition at line 832 of file timer_reg.h.
| #define TIMER_EXTCTL_ICAPSEL_Pos (8) |
TIMER_T::EXTCTL: ICAPSEL Position
Definition at line 831 of file timer_reg.h.
| #define TIMER_INTSTS_TIF_Msk (0x1ul << TIMER_INTSTS_TIF_Pos) |
TIMER_T::INTSTS: TIF Mask
Definition at line 799 of file timer_reg.h.
| #define TIMER_INTSTS_TIF_Pos (0) |
TIMER_T::INTSTS: TIF Position
Definition at line 798 of file timer_reg.h.
| #define TIMER_INTSTS_TWKF_Msk (0x1ul << TIMER_INTSTS_TWKF_Pos) |
TIMER_T::INTSTS: TWKF Mask
Definition at line 802 of file timer_reg.h.
| #define TIMER_INTSTS_TWKF_Pos (1) |
TIMER_T::INTSTS: TWKF Position
Definition at line 801 of file timer_reg.h.
| #define TIMER_PWMBNF_BKPINSRC_Msk (0x3ul << TIMER_PWMBNF_BKPINSRC_Pos) |
TIMER_T::PWMBNF: BKPINSRC Mask
Definition at line 943 of file timer_reg.h.
| #define TIMER_PWMBNF_BKPINSRC_Pos (16) |
TIMER_T::PWMBNF: BKPINSRC Position
Definition at line 942 of file timer_reg.h.
| #define TIMER_PWMBNF_BRKFCNT_Msk (0x7ul << TIMER_PWMBNF_BRKFCNT_Pos) |
TIMER_T::PWMBNF: BRKFCNT Mask
Definition at line 937 of file timer_reg.h.
| #define TIMER_PWMBNF_BRKFCNT_Pos (4) |
TIMER_T::PWMBNF: BRKFCNT Position
Definition at line 936 of file timer_reg.h.
| #define TIMER_PWMBNF_BRKNFEN_Msk (0x1ul << TIMER_PWMBNF_BRKNFEN_Pos) |
TIMER_T::PWMBNF: BRKNFEN Mask
Definition at line 931 of file timer_reg.h.
| #define TIMER_PWMBNF_BRKNFEN_Pos (0) |
TIMER_T::PWMBNF: BRKNFEN Position
Definition at line 930 of file timer_reg.h.
| #define TIMER_PWMBNF_BRKNFSEL_Msk (0x7ul << TIMER_PWMBNF_BRKNFSEL_Pos) |
TIMER_T::PWMBNF: BRKNFSEL Mask
Definition at line 934 of file timer_reg.h.
| #define TIMER_PWMBNF_BRKNFSEL_Pos (1) |
TIMER_T::PWMBNF: BRKNFSEL Position
Definition at line 933 of file timer_reg.h.
| #define TIMER_PWMBNF_BRKPINV_Msk (0x1ul << TIMER_PWMBNF_BRKPINV_Pos) |
TIMER_T::PWMBNF: BRKPINV Mask
Definition at line 940 of file timer_reg.h.
| #define TIMER_PWMBNF_BRKPINV_Pos (7) |
TIMER_T::PWMBNF: BRKPINV Position
Definition at line 939 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_BRKAEVEN_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAEVEN_Pos) |
TIMER_T::PWMBRKCTL: BRKAEVEN Mask
Definition at line 982 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_BRKAEVEN_Pos (16) |
TIMER_T::PWMBRKCTL: BRKAEVEN Position
Definition at line 981 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_BRKAODD_Msk (0x3ul << TIMER_PWMBRKCTL_BRKAODD_Pos) |
TIMER_T::PWMBRKCTL: BRKAODD Mask
Definition at line 985 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_BRKAODD_Pos (18) |
TIMER_T::PWMBRKCTL: BRKAODD Position
Definition at line 984 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_BRKPEEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPEEN_Pos) |
TIMER_T::PWMBRKCTL: BRKPEEN Mask
Definition at line 964 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_BRKPEEN_Pos (4) |
TIMER_T::PWMBRKCTL: BRKPEEN Position
Definition at line 963 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_BRKPLEN_Msk (0x1ul << TIMER_PWMBRKCTL_BRKPLEN_Pos) |
TIMER_T::PWMBRKCTL: BRKPLEN Mask
Definition at line 976 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_BRKPLEN_Pos (12) |
TIMER_T::PWMBRKCTL: BRKPLEN Position
Definition at line 975 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_CPO0EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0EBEN_Pos) |
TIMER_T::PWMBRKCTL: CPO0EBEN Mask
Definition at line 958 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_CPO0EBEN_Pos (0) |
TIMER_T::PWMBRKCTL: CPO0EBEN Position
Definition at line 957 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_CPO0LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO0LBEN_Pos) |
TIMER_T::PWMBRKCTL: CPO0LBEN Mask
Definition at line 970 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_CPO0LBEN_Pos (8) |
TIMER_T::PWMBRKCTL: CPO0LBEN Position
Definition at line 969 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_CPO1EBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1EBEN_Pos) |
TIMER_T::PWMBRKCTL: CPO1EBEN Mask
Definition at line 961 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_CPO1EBEN_Pos (1) |
TIMER_T::PWMBRKCTL: CPO1EBEN Position
Definition at line 960 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_CPO1LBEN_Msk (0x1ul << TIMER_PWMBRKCTL_CPO1LBEN_Pos) |
TIMER_T::PWMBRKCTL: CPO1LBEN Mask
Definition at line 973 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_CPO1LBEN_Pos (9) |
TIMER_T::PWMBRKCTL: CPO1LBEN Position
Definition at line 972 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_SYSEBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSEBEN_Pos) |
TIMER_T::PWMBRKCTL: SYSEBEN Mask
Definition at line 967 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_SYSEBEN_Pos (7) |
TIMER_T::PWMBRKCTL: SYSEBEN Position
Definition at line 966 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_SYSLBEN_Msk (0x1ul << TIMER_PWMBRKCTL_SYSLBEN_Pos) |
TIMER_T::PWMBRKCTL: SYSLBEN Mask
Definition at line 979 of file timer_reg.h.
| #define TIMER_PWMBRKCTL_SYSLBEN_Pos (15) |
TIMER_T::PWMBRKCTL: SYSLBEN Position
Definition at line 978 of file timer_reg.h.
| #define TIMER_PWMCLKPSC_CLKPSC_Msk (0xffful << TIMER_PWMCLKPSC_CLKPSC_Pos) |
TIMER_T::PWMCLKPSC: CLKPSC Mask
Definition at line 892 of file timer_reg.h.
| #define TIMER_PWMCLKPSC_CLKPSC_Pos (0) |
TIMER_T::PWMCLKPSC: CLKPSC Position
Definition at line 891 of file timer_reg.h.
| #define TIMER_PWMCLKSRC_CLKSRC_Msk (0x7ul << TIMER_PWMCLKSRC_CLKSRC_Pos) |
TIMER_T::PWMCLKSRC: CLKSRC Mask
Definition at line 889 of file timer_reg.h.
| #define TIMER_PWMCLKSRC_CLKSRC_Pos (0) |
TIMER_T::PWMCLKSRC: CLKSRC Position
Definition at line 888 of file timer_reg.h.
| #define TIMER_PWMCMPBUF_CMPBUF_Msk (0xfffful << TIMER_PWMCMPBUF_CMPBUF_Pos) |
TIMER_T::PWMCMPBUF: CMPBUF Mask
Definition at line 1084 of file timer_reg.h.
| #define TIMER_PWMCMPBUF_CMPBUF_Pos (0) |
TIMER_T::PWMCMPBUF: CMPBUF Position
Definition at line 1083 of file timer_reg.h.
| #define TIMER_PWMCMPDAT_CMP_Msk (0xfffful << TIMER_PWMCMPDAT_CMP_Pos) |
TIMER_T::PWMCMPDAT: CMP Mask
Definition at line 901 of file timer_reg.h.
| #define TIMER_PWMCMPDAT_CMP_Pos (0) |
TIMER_T::PWMCMPDAT: CMP Position
Definition at line 900 of file timer_reg.h.
| #define TIMER_PWMCNT_CNT_Msk (0xfffful << TIMER_PWMCNT_CNT_Pos) |
TIMER_T::PWMCNT: CNT Mask
Definition at line 913 of file timer_reg.h.
| #define TIMER_PWMCNT_CNT_Pos (0) |
TIMER_T::PWMCNT: CNT Position
Definition at line 912 of file timer_reg.h.
| #define TIMER_PWMCNT_DIRF_Msk (0x1ul << TIMER_PWMCNT_DIRF_Pos) |
TIMER_T::PWMCNT: DIRF Mask
Definition at line 916 of file timer_reg.h.
| #define TIMER_PWMCNT_DIRF_Pos (16) |
TIMER_T::PWMCNT: DIRF Position
Definition at line 915 of file timer_reg.h.
| #define TIMER_PWMCNTCLR_CNTCLR_Msk (0x1ul << TIMER_PWMCNTCLR_CNTCLR_Pos) |
TIMER_T::PWMCNTCLR: CNTCLR Mask
Definition at line 895 of file timer_reg.h.
| #define TIMER_PWMCNTCLR_CNTCLR_Pos (0) |
TIMER_T::PWMCNTCLR: CNTCLR Position
Definition at line 894 of file timer_reg.h.
| #define TIMER_PWMCTL_CNTEN_Msk (0x1ul << TIMER_PWMCTL_CNTEN_Pos) |
TIMER_T::PWMCTL: CNTEN Mask
Definition at line 865 of file timer_reg.h.
| #define TIMER_PWMCTL_CNTEN_Pos (0) |
TIMER_T::PWMCTL: CNTEN Position
Definition at line 864 of file timer_reg.h.
| #define TIMER_PWMCTL_CNTMODE_Msk (0x1ul << TIMER_PWMCTL_CNTMODE_Pos) |
TIMER_T::PWMCTL: CNTMODE Mask
Definition at line 871 of file timer_reg.h.
| #define TIMER_PWMCTL_CNTMODE_Pos (3) |
TIMER_T::PWMCTL: CNTMODE Position
Definition at line 870 of file timer_reg.h.
| #define TIMER_PWMCTL_CNTTYPE_Msk (0x3ul << TIMER_PWMCTL_CNTTYPE_Pos) |
TIMER_T::PWMCTL: CNTTYPE Mask
Definition at line 868 of file timer_reg.h.
| #define TIMER_PWMCTL_CNTTYPE_Pos (1) |
TIMER_T::PWMCTL: CNTTYPE Position
Definition at line 867 of file timer_reg.h.
| #define TIMER_PWMCTL_CTRLD_Msk (0x1ul << TIMER_PWMCTL_CTRLD_Pos) |
TIMER_T::PWMCTL: CTRLD Mask
Definition at line 874 of file timer_reg.h.
| #define TIMER_PWMCTL_CTRLD_Pos (8) |
TIMER_T::PWMCTL: CTRLD Position
Definition at line 873 of file timer_reg.h.
| #define TIMER_PWMCTL_DBGHALT_Msk (0x1ul << TIMER_PWMCTL_DBGHALT_Pos) |
TIMER_T::PWMCTL: DBGHALT Mask
Definition at line 883 of file timer_reg.h.
| #define TIMER_PWMCTL_DBGHALT_Pos (30) |
TIMER_T::PWMCTL: DBGHALT Position
Definition at line 882 of file timer_reg.h.
| #define TIMER_PWMCTL_DBGTRIOFF_Msk (0x1ul << TIMER_PWMCTL_DBGTRIOFF_Pos) |
TIMER_T::PWMCTL: DBGTRIOFF Mask
Definition at line 886 of file timer_reg.h.
| #define TIMER_PWMCTL_DBGTRIOFF_Pos (31) |
TIMER_T::PWMCTL: DBGTRIOFF Position
Definition at line 885 of file timer_reg.h.
| #define TIMER_PWMCTL_IMMLDEN_Msk (0x1ul << TIMER_PWMCTL_IMMLDEN_Pos) |
TIMER_T::PWMCTL: IMMLDEN Mask
Definition at line 877 of file timer_reg.h.
| #define TIMER_PWMCTL_IMMLDEN_Pos (9) |
TIMER_T::PWMCTL: IMMLDEN Position
Definition at line 876 of file timer_reg.h.
| #define TIMER_PWMCTL_OUTMODE_Msk (0x1ul << TIMER_PWMCTL_OUTMODE_Pos) |
TIMER_T::PWMCTL: OUTMODE Mask
Definition at line 880 of file timer_reg.h.
| #define TIMER_PWMCTL_OUTMODE_Pos (16) |
TIMER_T::PWMCTL: OUTMODE Position
Definition at line 879 of file timer_reg.h.
| #define TIMER_PWMDTCTL_DTCKSEL_Msk (0x1ul << TIMER_PWMDTCTL_DTCKSEL_Pos) |
TIMER_T::PWMDTCTL: DTCKSEL Mask
Definition at line 910 of file timer_reg.h.
| #define TIMER_PWMDTCTL_DTCKSEL_Pos (24) |
TIMER_T::PWMDTCTL: DTCKSEL Position
Definition at line 909 of file timer_reg.h.
| #define TIMER_PWMDTCTL_DTCNT_Msk (0xffful << TIMER_PWMDTCTL_DTCNT_Pos) |
TIMER_T::PWMDTCTL: DTCNT Mask
Definition at line 904 of file timer_reg.h.
| #define TIMER_PWMDTCTL_DTCNT_Pos (0) |
TIMER_T::PWMDTCTL: DTCNT Position
Definition at line 903 of file timer_reg.h.
| #define TIMER_PWMDTCTL_DTEN_Msk (0x1ul << TIMER_PWMDTCTL_DTEN_Pos) |
TIMER_T::PWMDTCTL: DTEN Mask
Definition at line 907 of file timer_reg.h.
| #define TIMER_PWMDTCTL_DTEN_Pos (16) |
TIMER_T::PWMDTCTL: DTEN Position
Definition at line 906 of file timer_reg.h.
| #define TIMER_PWMEADCTS_TRGEN_Msk (0x1ul << TIMER_PWMEADCTS_TRGEN_Pos) |
TIMER_T::PWMEADCTS: TRGEN Mask
Definition at line 1063 of file timer_reg.h.
| #define TIMER_PWMEADCTS_TRGEN_Pos (7) |
TIMER_T::PWMEADCTS: TRGEN Position
Definition at line 1062 of file timer_reg.h.
| #define TIMER_PWMEADCTS_TRGSEL_Msk (0x7ul << TIMER_PWMEADCTS_TRGSEL_Pos) |
TIMER_T::PWMEADCTS: TRGSEL Mask
Definition at line 1060 of file timer_reg.h.
| #define TIMER_PWMEADCTS_TRGSEL_Pos (0) |
TIMER_T::PWMEADCTS: TRGSEL Position
Definition at line 1059 of file timer_reg.h.
| #define TIMER_PWMFAILBRK_BODBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_BODBRKEN_Pos) |
TIMER_T::PWMFAILBRK: BODBRKEN Mask
Definition at line 949 of file timer_reg.h.
| #define TIMER_PWMFAILBRK_BODBRKEN_Pos (1) |
TIMER_T::PWMFAILBRK: BODBRKEN Position
Definition at line 948 of file timer_reg.h.
| #define TIMER_PWMFAILBRK_CORBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CORBRKEN_Pos) |
TIMER_T::PWMFAILBRK: CORBRKEN Mask
Definition at line 955 of file timer_reg.h.
| #define TIMER_PWMFAILBRK_CORBRKEN_Pos (3) |
TIMER_T::PWMFAILBRK: CORBRKEN Position
Definition at line 954 of file timer_reg.h.
| #define TIMER_PWMFAILBRK_CSSBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_CSSBRKEN_Pos) |
TIMER_T::PWMFAILBRK: CSSBRKEN Mask
Definition at line 946 of file timer_reg.h.
| #define TIMER_PWMFAILBRK_CSSBRKEN_Pos (0) |
TIMER_T::PWMFAILBRK: CSSBRKEN Position
Definition at line 945 of file timer_reg.h.
| #define TIMER_PWMFAILBRK_RAMBRKEN_Msk (0x1ul << TIMER_PWMFAILBRK_RAMBRKEN_Pos) |
TIMER_T::PWMFAILBRK: RAMBRKEN Mask
Definition at line 952 of file timer_reg.h.
| #define TIMER_PWMFAILBRK_RAMBRKEN_Pos (2) |
TIMER_T::PWMFAILBRK: RAMBRKEN Position
Definition at line 951 of file timer_reg.h.
| #define TIMER_PWMINTEN0_CMPDIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPDIEN_Pos) |
TIMER_T::PWMINTEN0: CMPDIEN Mask
Definition at line 1015 of file timer_reg.h.
| #define TIMER_PWMINTEN0_CMPDIEN_Pos (3) |
TIMER_T::PWMINTEN0: CMPDIEN Position
Definition at line 1014 of file timer_reg.h.
| #define TIMER_PWMINTEN0_CMPUIEN_Msk (0x1ul << TIMER_PWMINTEN0_CMPUIEN_Pos) |
TIMER_T::PWMINTEN0: CMPUIEN Mask
Definition at line 1012 of file timer_reg.h.
| #define TIMER_PWMINTEN0_CMPUIEN_Pos (2) |
TIMER_T::PWMINTEN0: CMPUIEN Position
Definition at line 1011 of file timer_reg.h.
| #define TIMER_PWMINTEN0_PIEN_Msk (0x1ul << TIMER_PWMINTEN0_PIEN_Pos) |
TIMER_T::PWMINTEN0: PIEN Mask
Definition at line 1009 of file timer_reg.h.
| #define TIMER_PWMINTEN0_PIEN_Pos (1) |
TIMER_T::PWMINTEN0: PIEN Position
Definition at line 1008 of file timer_reg.h.
| #define TIMER_PWMINTEN0_ZIEN_Msk (0x1ul << TIMER_PWMINTEN0_ZIEN_Pos) |
TIMER_T::PWMINTEN0: ZIEN Mask
Definition at line 1006 of file timer_reg.h.
| #define TIMER_PWMINTEN0_ZIEN_Pos (0) |
TIMER_T::PWMINTEN0: ZIEN Position
Definition at line 1005 of file timer_reg.h.
| #define TIMER_PWMINTEN1_BRKEIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKEIEN_Pos) |
TIMER_T::PWMINTEN1: BRKEIEN Mask
Definition at line 1018 of file timer_reg.h.
| #define TIMER_PWMINTEN1_BRKEIEN_Pos (0) |
TIMER_T::PWMINTEN1: BRKEIEN Position
Definition at line 1017 of file timer_reg.h.
| #define TIMER_PWMINTEN1_BRKLIEN_Msk (0x1ul << TIMER_PWMINTEN1_BRKLIEN_Pos) |
TIMER_T::PWMINTEN1: BRKLIEN Mask
Definition at line 1021 of file timer_reg.h.
| #define TIMER_PWMINTEN1_BRKLIEN_Pos (8) |
TIMER_T::PWMINTEN1: BRKLIEN Position
Definition at line 1020 of file timer_reg.h.
| #define TIMER_PWMINTSTS0_CMPDIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPDIF_Pos) |
TIMER_T::PWMINTSTS0: CMPDIF Mask
Definition at line 1033 of file timer_reg.h.
| #define TIMER_PWMINTSTS0_CMPDIF_Pos (3) |
TIMER_T::PWMINTSTS0: CMPDIF Position
Definition at line 1032 of file timer_reg.h.
| #define TIMER_PWMINTSTS0_CMPUIF_Msk (0x1ul << TIMER_PWMINTSTS0_CMPUIF_Pos) |
TIMER_T::PWMINTSTS0: CMPUIF Mask
Definition at line 1030 of file timer_reg.h.
| #define TIMER_PWMINTSTS0_CMPUIF_Pos (2) |
TIMER_T::PWMINTSTS0: CMPUIF Position
Definition at line 1029 of file timer_reg.h.
| #define TIMER_PWMINTSTS0_PIF_Msk (0x1ul << TIMER_PWMINTSTS0_PIF_Pos) |
TIMER_T::PWMINTSTS0: PIF Mask
Definition at line 1027 of file timer_reg.h.
| #define TIMER_PWMINTSTS0_PIF_Pos (1) |
TIMER_T::PWMINTSTS0: PIF Position
Definition at line 1026 of file timer_reg.h.
| #define TIMER_PWMINTSTS0_ZIF_Msk (0x1ul << TIMER_PWMINTSTS0_ZIF_Pos) |
TIMER_T::PWMINTSTS0: ZIF Mask
Definition at line 1024 of file timer_reg.h.
| #define TIMER_PWMINTSTS0_ZIF_Pos (0) |
TIMER_T::PWMINTSTS0: ZIF Position
Definition at line 1023 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKEIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF0_Pos) |
TIMER_T::PWMINTSTS1: BRKEIF0 Mask
Definition at line 1036 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKEIF0_Pos (0) |
TIMER_T::PWMINTSTS1: BRKEIF0 Position
Definition at line 1035 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKEIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKEIF1_Pos) |
TIMER_T::PWMINTSTS1: BRKEIF1 Mask
Definition at line 1039 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKEIF1_Pos (1) |
TIMER_T::PWMINTSTS1: BRKEIF1 Position
Definition at line 1038 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKESTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS0_Pos) |
TIMER_T::PWMINTSTS1: BRKESTS0 Mask
Definition at line 1048 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKESTS0_Pos (16) |
TIMER_T::PWMINTSTS1: BRKESTS0 Position
Definition at line 1047 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKESTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKESTS1_Pos) |
TIMER_T::PWMINTSTS1: BRKESTS1 Mask
Definition at line 1051 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKESTS1_Pos (17) |
TIMER_T::PWMINTSTS1: BRKESTS1 Position
Definition at line 1050 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKLIF0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF0_Pos) |
TIMER_T::PWMINTSTS1: BRKLIF0 Mask
Definition at line 1042 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKLIF0_Pos (8) |
TIMER_T::PWMINTSTS1: BRKLIF0 Position
Definition at line 1041 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKLIF1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLIF1_Pos) |
TIMER_T::PWMINTSTS1: BRKLIF1 Mask
Definition at line 1045 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKLIF1_Pos (9) |
TIMER_T::PWMINTSTS1: BRKLIF1 Position
Definition at line 1044 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKLSTS0_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS0_Pos) |
TIMER_T::PWMINTSTS1: BRKLSTS0 Mask
Definition at line 1054 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKLSTS0_Pos (24) |
TIMER_T::PWMINTSTS1: BRKLSTS0 Position
Definition at line 1053 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKLSTS1_Msk (0x1ul << TIMER_PWMINTSTS1_BRKLSTS1_Pos) |
TIMER_T::PWMINTSTS1: BRKLSTS1 Mask
Definition at line 1057 of file timer_reg.h.
| #define TIMER_PWMINTSTS1_BRKLSTS1_Pos (25) |
TIMER_T::PWMINTSTS1: BRKLSTS1 Position
Definition at line 1056 of file timer_reg.h.
| #define TIMER_PWMMSK_MSKDAT0_Msk (0x1ul << TIMER_PWMMSK_MSKDAT0_Pos) |
TIMER_T::PWMMSK: MSKDAT0 Mask
Definition at line 925 of file timer_reg.h.
| #define TIMER_PWMMSK_MSKDAT0_Pos (0) |
TIMER_T::PWMMSK: MSKDAT0 Position
Definition at line 924 of file timer_reg.h.
| #define TIMER_PWMMSK_MSKDAT1_Msk (0x1ul << TIMER_PWMMSK_MSKDAT1_Pos) |
TIMER_T::PWMMSK: MSKDAT1 Mask
Definition at line 928 of file timer_reg.h.
| #define TIMER_PWMMSK_MSKDAT1_Pos (1) |
TIMER_T::PWMMSK: MSKDAT1 Position
Definition at line 927 of file timer_reg.h.
| #define TIMER_PWMMSKEN_MSKEN0_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN0_Pos) |
TIMER_T::PWMMSKEN: MSKEN0 Mask
Definition at line 919 of file timer_reg.h.
| #define TIMER_PWMMSKEN_MSKEN0_Pos (0) |
TIMER_T::PWMMSKEN: MSKEN0 Position
Definition at line 918 of file timer_reg.h.
| #define TIMER_PWMMSKEN_MSKEN1_Msk (0x1ul << TIMER_PWMMSKEN_MSKEN1_Pos) |
TIMER_T::PWMMSKEN: MSKEN1 Mask
Definition at line 922 of file timer_reg.h.
| #define TIMER_PWMMSKEN_MSKEN1_Pos (1) |
TIMER_T::PWMMSKEN: MSKEN1 Position
Definition at line 921 of file timer_reg.h.
| #define TIMER_PWMPBUF_PBUF_Msk (0xfffful << TIMER_PWMPBUF_PBUF_Pos) |
TIMER_T::PWMPBUF: PBUF Mask
Definition at line 1081 of file timer_reg.h.
| #define TIMER_PWMPBUF_PBUF_Pos (0) |
TIMER_T::PWMPBUF: PBUF Position
Definition at line 1080 of file timer_reg.h.
| #define TIMER_PWMPERIOD_PERIOD_Msk (0xfffful << TIMER_PWMPERIOD_PERIOD_Pos) |
TIMER_T::PWMPERIOD: PERIOD Mask
Definition at line 898 of file timer_reg.h.
| #define TIMER_PWMPERIOD_PERIOD_Pos (0) |
TIMER_T::PWMPERIOD: PERIOD Position
Definition at line 897 of file timer_reg.h.
| #define TIMER_PWMPOEN_POEN0_Msk (0x1ul << TIMER_PWMPOEN_POEN0_Pos) |
TIMER_T::PWMPOEN: POEN0 Mask
Definition at line 994 of file timer_reg.h.
| #define TIMER_PWMPOEN_POEN0_Pos (0) |
TIMER_T::PWMPOEN: POEN0 Position
Definition at line 993 of file timer_reg.h.
| #define TIMER_PWMPOEN_POEN1_Msk (0x1ul << TIMER_PWMPOEN_POEN1_Pos) |
TIMER_T::PWMPOEN: POEN1 Mask
Definition at line 997 of file timer_reg.h.
| #define TIMER_PWMPOEN_POEN1_Pos (1) |
TIMER_T::PWMPOEN: POEN1 Position
Definition at line 996 of file timer_reg.h.
| #define TIMER_PWMPOLCTL_PINV0_Msk (0x1ul << TIMER_PWMPOLCTL_PINV0_Pos) |
TIMER_T::PWMPOLCTL: PINV0 Mask
Definition at line 988 of file timer_reg.h.
| #define TIMER_PWMPOLCTL_PINV0_Pos (0) |
TIMER_T::PWMPOLCTL: PINV0 Position
Definition at line 987 of file timer_reg.h.
| #define TIMER_PWMPOLCTL_PINV1_Msk (0x1ul << TIMER_PWMPOLCTL_PINV1_Pos) |
TIMER_T::PWMPOLCTL: PINV1 Mask
Definition at line 991 of file timer_reg.h.
| #define TIMER_PWMPOLCTL_PINV1_Pos (1) |
TIMER_T::PWMPOLCTL: PINV1 Position
Definition at line 990 of file timer_reg.h.
| #define TIMER_PWMSCTL_SYNCMODE_Msk (0x3ul << TIMER_PWMSCTL_SYNCMODE_Pos) |
TIMER_T::PWMSCTL: SYNCMODE Mask
Definition at line 1066 of file timer_reg.h.
| #define TIMER_PWMSCTL_SYNCMODE_Pos (0) |
TIMER_T::PWMSCTL: SYNCMODE Position
Definition at line 1065 of file timer_reg.h.
| #define TIMER_PWMSCTL_SYNCSRC_Msk (0x1ul << TIMER_PWMSCTL_SYNCSRC_Pos) |
TIMER_T::PWMSCTL: SYNCSRC Mask
Definition at line 1069 of file timer_reg.h.
| #define TIMER_PWMSCTL_SYNCSRC_Pos (8) |
TIMER_T::PWMSCTL: SYNCSRC Position
Definition at line 1068 of file timer_reg.h.
| #define TIMER_PWMSTATUS_CNTMAXF_Msk (0x1ul << TIMER_PWMSTATUS_CNTMAXF_Pos) |
TIMER_T::PWMSTATUS: CNTMAXF Mask
Definition at line 1075 of file timer_reg.h.
| #define TIMER_PWMSTATUS_CNTMAXF_Pos (0) |
TIMER_T::PWMSTATUS: CNTMAXF Position
Definition at line 1074 of file timer_reg.h.
| #define TIMER_PWMSTATUS_EADCTRGF_Msk (0x1ul << TIMER_PWMSTATUS_EADCTRGF_Pos) |
TIMER_T::PWMSTATUS: EADCTRGF Mask
Definition at line 1078 of file timer_reg.h.
| #define TIMER_PWMSTATUS_EADCTRGF_Pos (16) |
TIMER_T::PWMSTATUS: EADCTRGF Position
Definition at line 1077 of file timer_reg.h.
| #define TIMER_PWMSTRG_STRGEN_Msk (0x1ul << TIMER_PWMSTRG_STRGEN_Pos) |
TIMER_T::PWMSTRG: STRGEN Mask
Definition at line 1072 of file timer_reg.h.
| #define TIMER_PWMSTRG_STRGEN_Pos (0) |
TIMER_T::PWMSTRG: STRGEN Position
Definition at line 1071 of file timer_reg.h.
| #define TIMER_PWMSWBRK_BRKETRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKETRG_Pos) |
TIMER_T::PWMSWBRK: BRKETRG Mask
Definition at line 1000 of file timer_reg.h.
| #define TIMER_PWMSWBRK_BRKETRG_Pos (0) |
TIMER_T::PWMSWBRK: BRKETRG Position
Definition at line 999 of file timer_reg.h.
| #define TIMER_PWMSWBRK_BRKLTRG_Msk (0x1ul << TIMER_PWMSWBRK_BRKLTRG_Pos) |
TIMER_T::PWMSWBRK: BRKLTRG Mask
Definition at line 1003 of file timer_reg.h.
| #define TIMER_PWMSWBRK_BRKLTRG_Pos (8) |
TIMER_T::PWMSWBRK: BRKLTRG Position
Definition at line 1002 of file timer_reg.h.
| #define TIMER_TRGCTL_TRGDAC_Msk (0x1ul << TIMER_TRGCTL_TRGDAC_Pos) |
TIMER_T::TRGCTL: TRGDAC Mask
Definition at line 856 of file timer_reg.h.
| #define TIMER_TRGCTL_TRGDAC_Pos (3) |
TIMER_T::TRGCTL: TRGDAC Position
Definition at line 855 of file timer_reg.h.
| #define TIMER_TRGCTL_TRGEADC_Msk (0x1ul << TIMER_TRGCTL_TRGEADC_Pos) |
TIMER_T::TRGCTL: TRGEADC Mask
Definition at line 853 of file timer_reg.h.
| #define TIMER_TRGCTL_TRGEADC_Pos (2) |
TIMER_T::TRGCTL: TRGEADC Position
Definition at line 852 of file timer_reg.h.
| #define TIMER_TRGCTL_TRGEPWM_Msk (0x1ul << TIMER_TRGCTL_TRGEPWM_Pos) |
TIMER_T::TRGCTL: TRGEPWM Mask
Definition at line 850 of file timer_reg.h.
| #define TIMER_TRGCTL_TRGEPWM_Pos (1) |
TIMER_T::TRGCTL: TRGEPWM Position
Definition at line 849 of file timer_reg.h.
| #define TIMER_TRGCTL_TRGPDMA_Msk (0x1ul << TIMER_TRGCTL_TRGPDMA_Pos) |
TIMER_T::TRGCTL: TRGPDMA Mask
Definition at line 859 of file timer_reg.h.
| #define TIMER_TRGCTL_TRGPDMA_Pos (4) |
TIMER_T::TRGCTL: TRGPDMA Position
Definition at line 858 of file timer_reg.h.
| #define TIMER_TRGCTL_TRGSSEL_Msk (0x1ul << TIMER_TRGCTL_TRGSSEL_Pos) |
TIMER_T::TRGCTL: TRGSSEL Mask
Definition at line 847 of file timer_reg.h.
| #define TIMER_TRGCTL_TRGSSEL_Pos (0) |
TIMER_T::TRGCTL: TRGSSEL Position
Definition at line 846 of file timer_reg.h.
| #define UART_ALTCTL_ABRDBITS_Msk (0x3ul << UART_ALTCTL_ABRDBITS_Pos) |
UART_T::ALTCTL: ABRDBITS Mask
Definition at line 1155 of file uart_reg.h.
| #define UART_ALTCTL_ABRDBITS_Pos (19) |
UART_T::ALTCTL: ABRDBITS Position
Definition at line 1154 of file uart_reg.h.
| #define UART_ALTCTL_ABRDEN_Msk (0x1ul << UART_ALTCTL_ABRDEN_Pos) |
UART_T::ALTCTL: ABRDEN Mask
Definition at line 1152 of file uart_reg.h.
| #define UART_ALTCTL_ABRDEN_Pos (18) |
UART_T::ALTCTL: ABRDEN Position
Definition at line 1151 of file uart_reg.h.
| #define UART_ALTCTL_ABRIF_Msk (0x1ul << UART_ALTCTL_ABRIF_Pos) |
UART_T::ALTCTL: ABRIF Mask
Definition at line 1149 of file uart_reg.h.
| #define UART_ALTCTL_ABRIF_Pos (17) |
UART_T::ALTCTL: ABRIF Position
Definition at line 1148 of file uart_reg.h.
| #define UART_ALTCTL_ADDRDEN_Msk (0x1ul << UART_ALTCTL_ADDRDEN_Pos) |
UART_T::ALTCTL: ADDRDEN Mask
Definition at line 1146 of file uart_reg.h.
| #define UART_ALTCTL_ADDRDEN_Pos (15) |
UART_T::ALTCTL: ADDRDEN Position
Definition at line 1145 of file uart_reg.h.
| #define UART_ALTCTL_ADDRMV_Msk (0xfful << UART_ALTCTL_ADDRMV_Pos) |
UART_T::ALTCTL: ADDRMV Mask
Definition at line 1158 of file uart_reg.h.
| #define UART_ALTCTL_ADDRMV_Pos (24) |
UART_T::ALTCTL: ADDRMV Position
Definition at line 1157 of file uart_reg.h.
| #define UART_ALTCTL_BRKFL_Msk (0xful << UART_ALTCTL_BRKFL_Pos) |
UART_T::ALTCTL: BRKFL Mask
Definition at line 1128 of file uart_reg.h.
| #define UART_ALTCTL_BRKFL_Pos (0) |
UART_T::ALTCTL: BRKFL Position
Definition at line 1127 of file uart_reg.h.
| #define UART_ALTCTL_LINRXEN_Msk (0x1ul << UART_ALTCTL_LINRXEN_Pos) |
UART_T::ALTCTL: LINRXEN Mask
Definition at line 1131 of file uart_reg.h.
| #define UART_ALTCTL_LINRXEN_Pos (6) |
UART_T::ALTCTL: LINRXEN Position
Definition at line 1130 of file uart_reg.h.
| #define UART_ALTCTL_LINTXEN_Msk (0x1ul << UART_ALTCTL_LINTXEN_Pos) |
UART_T::ALTCTL: LINTXEN Mask
Definition at line 1134 of file uart_reg.h.
| #define UART_ALTCTL_LINTXEN_Pos (7) |
UART_T::ALTCTL: LINTXEN Position
Definition at line 1133 of file uart_reg.h.
| #define UART_ALTCTL_RS485AAD_Msk (0x1ul << UART_ALTCTL_RS485AAD_Pos) |
UART_T::ALTCTL: RS485AAD Mask
Definition at line 1140 of file uart_reg.h.
| #define UART_ALTCTL_RS485AAD_Pos (9) |
UART_T::ALTCTL: RS485AAD Position
Definition at line 1139 of file uart_reg.h.
| #define UART_ALTCTL_RS485AUD_Msk (0x1ul << UART_ALTCTL_RS485AUD_Pos) |
UART_T::ALTCTL: RS485AUD Mask
Definition at line 1143 of file uart_reg.h.
| #define UART_ALTCTL_RS485AUD_Pos (10) |
UART_T::ALTCTL: RS485AUD Position
Definition at line 1142 of file uart_reg.h.
| #define UART_ALTCTL_RS485NMM_Msk (0x1ul << UART_ALTCTL_RS485NMM_Pos) |
UART_T::ALTCTL: RS485NMM Mask
Definition at line 1137 of file uart_reg.h.
| #define UART_ALTCTL_RS485NMM_Pos (8) |
UART_T::ALTCTL: RS485NMM Position
Definition at line 1136 of file uart_reg.h.
| #define UART_BAUD_BAUDM0_Msk (0x1ul << UART_BAUD_BAUDM0_Pos) |
UART_T::BAUD: BAUDM0 Mask
Definition at line 1113 of file uart_reg.h.
| #define UART_BAUD_BAUDM0_Pos (28) |
UART_T::BAUD: BAUDM0 Position
Definition at line 1112 of file uart_reg.h.
| #define UART_BAUD_BAUDM1_Msk (0x1ul << UART_BAUD_BAUDM1_Pos) |
UART_T::BAUD: BAUDM1 Mask
Definition at line 1116 of file uart_reg.h.
| #define UART_BAUD_BAUDM1_Pos (29) |
UART_T::BAUD: BAUDM1 Position
Definition at line 1115 of file uart_reg.h.
| #define UART_BAUD_BRD_Msk (0xfffful << UART_BAUD_BRD_Pos) |
UART_T::BAUD: BRD Mask
Definition at line 1107 of file uart_reg.h.
| #define UART_BAUD_BRD_Pos (0) |
UART_T::BAUD: BRD Position
Definition at line 1106 of file uart_reg.h.
| #define UART_BAUD_EDIVM1_Msk (0xful << UART_BAUD_EDIVM1_Pos) |
UART_T::BAUD: EDIVM1 Mask
Definition at line 1110 of file uart_reg.h.
| #define UART_BAUD_EDIVM1_Pos (24) |
UART_T::BAUD: EDIVM1 Position
Definition at line 1109 of file uart_reg.h.
| #define UART_BRCOMP_BRCOMP_Msk (0x1fful << UART_BRCOMP_BRCOMP_Pos) |
UART_T::BRCOMP: BRCOMP Mask
Definition at line 1227 of file uart_reg.h.
| #define UART_BRCOMP_BRCOMP_Pos (0) |
UART_T::BRCOMP: BRCOMP Position
Definition at line 1226 of file uart_reg.h.
| #define UART_BRCOMP_BRCOMPDEC_Msk (0x1ul << UART_BRCOMP_BRCOMPDEC_Pos) |
UART_T::BRCOMP: BRCOMPDEC Mask
Definition at line 1230 of file uart_reg.h.
| #define UART_BRCOMP_BRCOMPDEC_Pos (31) |
UART_T::BRCOMP: BRCOMPDEC Position
Definition at line 1229 of file uart_reg.h.
| #define UART_DAT_DAT_Msk (0xfful << UART_DAT_DAT_Pos) |
UART_T::DAT: DAT Mask
Definition at line 858 of file uart_reg.h.
| #define UART_DAT_DAT_Pos (0) |
@addtogroup UART_CONST UART Bit Field Definition Constant Definitions for UART Controller
UART_T::DAT: DAT Position
Definition at line 857 of file uart_reg.h.
| #define UART_DAT_PARITY_Msk (0x1ul << UART_DAT_PARITY_Pos) |
UART_T::DAT: PARITY Mask
Definition at line 861 of file uart_reg.h.
| #define UART_DAT_PARITY_Pos (8) |
UART_T::DAT: PARITY Position
Definition at line 860 of file uart_reg.h.
| #define UART_DWKCOMP_STCOMP_Msk (0xfffful << UART_DWKCOMP_STCOMP_Pos) |
UART_T::DWKCOMP: STCOMP Mask
Definition at line 1263 of file uart_reg.h.
| #define UART_DWKCOMP_STCOMP_Pos (0) |
UART_T::DWKCOMP: STCOMP Position
Definition at line 1262 of file uart_reg.h.
| #define UART_FIFO_RFITL_Msk (0xful << UART_FIFO_RFITL_Pos) |
UART_T::FIFO: RFITL Mask
Definition at line 915 of file uart_reg.h.
| #define UART_FIFO_RFITL_Pos (4) |
UART_T::FIFO: RFITL Position
Definition at line 914 of file uart_reg.h.
| #define UART_FIFO_RTSTRGLV_Msk (0xful << UART_FIFO_RTSTRGLV_Pos) |
UART_T::FIFO: RTSTRGLV Mask
Definition at line 921 of file uart_reg.h.
| #define UART_FIFO_RTSTRGLV_Pos (16) |
UART_T::FIFO: RTSTRGLV Position
Definition at line 920 of file uart_reg.h.
| #define UART_FIFO_RXOFF_Msk (0x1ul << UART_FIFO_RXOFF_Pos) |
UART_T::FIFO: RXOFF Mask
Definition at line 918 of file uart_reg.h.
| #define UART_FIFO_RXOFF_Pos (8) |
UART_T::FIFO: RXOFF Position
Definition at line 917 of file uart_reg.h.
| #define UART_FIFO_RXRST_Msk (0x1ul << UART_FIFO_RXRST_Pos) |
UART_T::FIFO: RXRST Mask
Definition at line 909 of file uart_reg.h.
| #define UART_FIFO_RXRST_Pos (1) |
UART_T::FIFO: RXRST Position
Definition at line 908 of file uart_reg.h.
| #define UART_FIFO_TXRST_Msk (0x1ul << UART_FIFO_TXRST_Pos) |
UART_T::FIFO: TXRST Mask
Definition at line 912 of file uart_reg.h.
| #define UART_FIFO_TXRST_Pos (2) |
UART_T::FIFO: TXRST Position
Definition at line 911 of file uart_reg.h.
| #define UART_FIFOSTS_ABRDIF_Msk (0x1ul << UART_FIFOSTS_ABRDIF_Pos) |
UART_T::FIFOSTS: ABRDIF Mask
Definition at line 972 of file uart_reg.h.
| #define UART_FIFOSTS_ABRDIF_Pos (1) |
UART_T::FIFOSTS: ABRDIF Position
Definition at line 971 of file uart_reg.h.
| #define UART_FIFOSTS_ABRDTOIF_Msk (0x1ul << UART_FIFOSTS_ABRDTOIF_Pos) |
UART_T::FIFOSTS: ABRDTOIF Mask
Definition at line 975 of file uart_reg.h.
| #define UART_FIFOSTS_ABRDTOIF_Pos (2) |
UART_T::FIFOSTS: ABRDTOIF Position
Definition at line 974 of file uart_reg.h.
| #define UART_FIFOSTS_ADDRDETF_Msk (0x1ul << UART_FIFOSTS_ADDRDETF_Pos) |
UART_T::FIFOSTS: ADDRDETF Mask
Definition at line 978 of file uart_reg.h.
| #define UART_FIFOSTS_ADDRDETF_Pos (3) |
UART_T::FIFOSTS: ADDRDETF Position
Definition at line 977 of file uart_reg.h.
| #define UART_FIFOSTS_BIF_Msk (0x1ul << UART_FIFOSTS_BIF_Pos) |
UART_T::FIFOSTS: BIF Mask
Definition at line 987 of file uart_reg.h.
| #define UART_FIFOSTS_BIF_Pos (6) |
UART_T::FIFOSTS: BIF Position
Definition at line 986 of file uart_reg.h.
| #define UART_FIFOSTS_FEF_Msk (0x1ul << UART_FIFOSTS_FEF_Pos) |
UART_T::FIFOSTS: FEF Mask
Definition at line 984 of file uart_reg.h.
| #define UART_FIFOSTS_FEF_Pos (5) |
UART_T::FIFOSTS: FEF Position
Definition at line 983 of file uart_reg.h.
| #define UART_FIFOSTS_PEF_Msk (0x1ul << UART_FIFOSTS_PEF_Pos) |
UART_T::FIFOSTS: PEF Mask
Definition at line 981 of file uart_reg.h.
| #define UART_FIFOSTS_PEF_Pos (4) |
UART_T::FIFOSTS: PEF Position
Definition at line 980 of file uart_reg.h.
| #define UART_FIFOSTS_RXEMPTY_Msk (0x1ul << UART_FIFOSTS_RXEMPTY_Pos) |
UART_T::FIFOSTS: RXEMPTY Mask
Definition at line 993 of file uart_reg.h.
| #define UART_FIFOSTS_RXEMPTY_Pos (14) |
UART_T::FIFOSTS: RXEMPTY Position
Definition at line 992 of file uart_reg.h.
| #define UART_FIFOSTS_RXFULL_Msk (0x1ul << UART_FIFOSTS_RXFULL_Pos) |
UART_T::FIFOSTS: RXFULL Mask
Definition at line 996 of file uart_reg.h.
| #define UART_FIFOSTS_RXFULL_Pos (15) |
UART_T::FIFOSTS: RXFULL Position
Definition at line 995 of file uart_reg.h.
| #define UART_FIFOSTS_RXIDLE_Msk (0x1ul << UART_FIFOSTS_RXIDLE_Pos) |
UART_T::FIFOSTS: RXIDLE Mask
Definition at line 1014 of file uart_reg.h.
| #define UART_FIFOSTS_RXIDLE_Pos (29) |
UART_T::FIFOSTS: RXIDLE Position
Definition at line 1013 of file uart_reg.h.
| #define UART_FIFOSTS_RXOVIF_Msk (0x1ul << UART_FIFOSTS_RXOVIF_Pos) |
UART_T::FIFOSTS: RXOVIF Mask
Definition at line 969 of file uart_reg.h.
| #define UART_FIFOSTS_RXOVIF_Pos (0) |
UART_T::FIFOSTS: RXOVIF Position
Definition at line 968 of file uart_reg.h.
| #define UART_FIFOSTS_RXPTR_Msk (0x3ful << UART_FIFOSTS_RXPTR_Pos) |
UART_T::FIFOSTS: RXPTR Mask
Definition at line 990 of file uart_reg.h.
| #define UART_FIFOSTS_RXPTR_Pos (8) |
UART_T::FIFOSTS: RXPTR Position
Definition at line 989 of file uart_reg.h.
| #define UART_FIFOSTS_TXEMPTY_Msk (0x1ul << UART_FIFOSTS_TXEMPTY_Pos) |
UART_T::FIFOSTS: TXEMPTY Mask
Definition at line 1002 of file uart_reg.h.
| #define UART_FIFOSTS_TXEMPTY_Pos (22) |
UART_T::FIFOSTS: TXEMPTY Position
Definition at line 1001 of file uart_reg.h.
| #define UART_FIFOSTS_TXEMPTYF_Msk (0x1ul << UART_FIFOSTS_TXEMPTYF_Pos) |
UART_T::FIFOSTS: TXEMPTYF Mask
Definition at line 1011 of file uart_reg.h.
| #define UART_FIFOSTS_TXEMPTYF_Pos (28) |
UART_T::FIFOSTS: TXEMPTYF Position
Definition at line 1010 of file uart_reg.h.
| #define UART_FIFOSTS_TXFULL_Msk (0x1ul << UART_FIFOSTS_TXFULL_Pos) |
UART_T::FIFOSTS: TXFULL Mask
Definition at line 1005 of file uart_reg.h.
| #define UART_FIFOSTS_TXFULL_Pos (23) |
UART_T::FIFOSTS: TXFULL Position
Definition at line 1004 of file uart_reg.h.
| #define UART_FIFOSTS_TXOVIF_Msk (0x1ul << UART_FIFOSTS_TXOVIF_Pos) |
UART_T::FIFOSTS: TXOVIF Mask
Definition at line 1008 of file uart_reg.h.
| #define UART_FIFOSTS_TXOVIF_Pos (24) |
UART_T::FIFOSTS: TXOVIF Position
Definition at line 1007 of file uart_reg.h.
| #define UART_FIFOSTS_TXPTR_Msk (0x3ful << UART_FIFOSTS_TXPTR_Pos) |
UART_T::FIFOSTS: TXPTR Mask
Definition at line 999 of file uart_reg.h.
| #define UART_FIFOSTS_TXPTR_Pos (16) |
UART_T::FIFOSTS: TXPTR Position
Definition at line 998 of file uart_reg.h.
| #define UART_FIFOSTS_TXRXACT_Msk (0x1ul << UART_FIFOSTS_TXRXACT_Pos) |
UART_T::FIFOSTS: TXRXACT Mask
Definition at line 1017 of file uart_reg.h.
| #define UART_FIFOSTS_TXRXACT_Pos (31) |
UART_T::FIFOSTS: TXRXACT Position
Definition at line 1016 of file uart_reg.h.
| #define UART_FUNCSEL_FUNCSEL_Msk (0x3ul << UART_FUNCSEL_FUNCSEL_Pos) |
UART_T::FUNCSEL: FUNCSEL Mask
Definition at line 1161 of file uart_reg.h.
| #define UART_FUNCSEL_FUNCSEL_Pos (0) |
UART_T::FUNCSEL: FUNCSEL Position
Definition at line 1160 of file uart_reg.h.
| #define UART_FUNCSEL_TXRXDIS_Msk (0x1ul << UART_FUNCSEL_TXRXDIS_Pos) |
UART_T::FUNCSEL: TXRXDIS Mask
Definition at line 1164 of file uart_reg.h.
| #define UART_FUNCSEL_TXRXDIS_Pos (3) |
UART_T::FUNCSEL: TXRXDIS Position
Definition at line 1163 of file uart_reg.h.
| #define UART_INTEN_ABRIEN_Msk (0x1ul << UART_INTEN_ABRIEN_Pos) |
UART_T::INTEN: ABRIEN Mask
Definition at line 903 of file uart_reg.h.
| #define UART_INTEN_ABRIEN_Pos (18) |
UART_T::INTEN: ABRIEN Position
Definition at line 902 of file uart_reg.h.
| #define UART_INTEN_ATOCTSEN_Msk (0x1ul << UART_INTEN_ATOCTSEN_Pos) |
UART_T::INTEN: ATOCTSEN Mask
Definition at line 894 of file uart_reg.h.
| #define UART_INTEN_ATOCTSEN_Pos (13) |
UART_T::INTEN: ATOCTSEN Position
Definition at line 893 of file uart_reg.h.
| #define UART_INTEN_ATORTSEN_Msk (0x1ul << UART_INTEN_ATORTSEN_Pos) |
UART_T::INTEN: ATORTSEN Mask
Definition at line 891 of file uart_reg.h.
| #define UART_INTEN_ATORTSEN_Pos (12) |
UART_T::INTEN: ATORTSEN Position
Definition at line 890 of file uart_reg.h.
| #define UART_INTEN_BUFERRIEN_Msk (0x1ul << UART_INTEN_BUFERRIEN_Pos) |
UART_T::INTEN: BUFERRIEN Mask
Definition at line 879 of file uart_reg.h.
| #define UART_INTEN_BUFERRIEN_Pos (5) |
UART_T::INTEN: BUFERRIEN Position
Definition at line 878 of file uart_reg.h.
| #define UART_INTEN_LINIEN_Msk (0x1ul << UART_INTEN_LINIEN_Pos) |
UART_T::INTEN: LINIEN Mask
Definition at line 885 of file uart_reg.h.
| #define UART_INTEN_LINIEN_Pos (8) |
UART_T::INTEN: LINIEN Position
Definition at line 884 of file uart_reg.h.
| #define UART_INTEN_MODEMIEN_Msk (0x1ul << UART_INTEN_MODEMIEN_Pos) |
UART_T::INTEN: MODEMIEN Mask
Definition at line 873 of file uart_reg.h.
| #define UART_INTEN_MODEMIEN_Pos (3) |
UART_T::INTEN: MODEMIEN Position
Definition at line 872 of file uart_reg.h.
| #define UART_INTEN_RDAIEN_Msk (0x1ul << UART_INTEN_RDAIEN_Pos) |
UART_T::INTEN: RDAIEN Mask
Definition at line 864 of file uart_reg.h.
| #define UART_INTEN_RDAIEN_Pos (0) |
UART_T::INTEN: RDAIEN Position
Definition at line 863 of file uart_reg.h.
| #define UART_INTEN_RLSIEN_Msk (0x1ul << UART_INTEN_RLSIEN_Pos) |
UART_T::INTEN: RLSIEN Mask
Definition at line 870 of file uart_reg.h.
| #define UART_INTEN_RLSIEN_Pos (2) |
UART_T::INTEN: RLSIEN Position
Definition at line 869 of file uart_reg.h.
| #define UART_INTEN_RXPDMAEN_Msk (0x1ul << UART_INTEN_RXPDMAEN_Pos) |
UART_T::INTEN: RXPDMAEN Mask
Definition at line 900 of file uart_reg.h.
| #define UART_INTEN_RXPDMAEN_Pos (15) |
UART_T::INTEN: RXPDMAEN Position
Definition at line 899 of file uart_reg.h.
| #define UART_INTEN_RXTOIEN_Msk (0x1ul << UART_INTEN_RXTOIEN_Pos) |
UART_T::INTEN: RXTOIEN Mask
Definition at line 876 of file uart_reg.h.
| #define UART_INTEN_RXTOIEN_Pos (4) |
UART_T::INTEN: RXTOIEN Position
Definition at line 875 of file uart_reg.h.
| #define UART_INTEN_THREIEN_Msk (0x1ul << UART_INTEN_THREIEN_Pos) |
UART_T::INTEN: THREIEN Mask
Definition at line 867 of file uart_reg.h.
| #define UART_INTEN_THREIEN_Pos (1) |
UART_T::INTEN: THREIEN Position
Definition at line 866 of file uart_reg.h.
| #define UART_INTEN_TOCNTEN_Msk (0x1ul << UART_INTEN_TOCNTEN_Pos) |
UART_T::INTEN: TOCNTEN Mask
Definition at line 888 of file uart_reg.h.
| #define UART_INTEN_TOCNTEN_Pos (11) |
UART_T::INTEN: TOCNTEN Position
Definition at line 887 of file uart_reg.h.
| #define UART_INTEN_TXENDIEN_Msk (0x1ul << UART_INTEN_TXENDIEN_Pos) |
UART_T::INTEN: TXENDIEN Mask
Definition at line 906 of file uart_reg.h.
| #define UART_INTEN_TXENDIEN_Pos (22) |
UART_T::INTEN: TXENDIEN Position
Definition at line 905 of file uart_reg.h.
| #define UART_INTEN_TXPDMAEN_Msk (0x1ul << UART_INTEN_TXPDMAEN_Pos) |
UART_T::INTEN: TXPDMAEN Mask
Definition at line 897 of file uart_reg.h.
| #define UART_INTEN_TXPDMAEN_Pos (14) |
UART_T::INTEN: TXPDMAEN Position
Definition at line 896 of file uart_reg.h.
| #define UART_INTEN_WKIEN_Msk (0x1ul << UART_INTEN_WKIEN_Pos) |
UART_T::INTEN: WKIEN Mask
Definition at line 882 of file uart_reg.h.
| #define UART_INTEN_WKIEN_Pos (6) |
UART_T::INTEN: WKIEN Position
Definition at line 881 of file uart_reg.h.
| #define UART_INTSTS_ABRINT_Msk (0x1ul << UART_INTSTS_ABRINT_Pos) |
UART_T::INTSTS: ABRINT Mask
Definition at line 1098 of file uart_reg.h.
| #define UART_INTSTS_ABRINT_Pos (31) |
UART_T::INTSTS: ABRINT Position
Definition at line 1097 of file uart_reg.h.
| #define UART_INTSTS_BUFERRIF_Msk (0x1ul << UART_INTSTS_BUFERRIF_Pos) |
UART_T::INTSTS: BUFERRIF Mask
Definition at line 1035 of file uart_reg.h.
| #define UART_INTSTS_BUFERRIF_Pos (5) |
UART_T::INTSTS: BUFERRIF Position
Definition at line 1034 of file uart_reg.h.
| #define UART_INTSTS_BUFERRINT_Msk (0x1ul << UART_INTSTS_BUFERRINT_Pos) |
UART_T::INTSTS: BUFERRINT Mask
Definition at line 1059 of file uart_reg.h.
| #define UART_INTSTS_BUFERRINT_Pos (13) |
UART_T::INTSTS: BUFERRINT Position
Definition at line 1058 of file uart_reg.h.
| #define UART_INTSTS_HWBUFEIF_Msk (0x1ul << UART_INTSTS_HWBUFEIF_Pos) |
UART_T::INTSTS: HWBUFEIF Mask
Definition at line 1077 of file uart_reg.h.
| #define UART_INTSTS_HWBUFEIF_Pos (21) |
UART_T::INTSTS: HWBUFEIF Position
Definition at line 1076 of file uart_reg.h.
| #define UART_INTSTS_HWBUFEINT_Msk (0x1ul << UART_INTSTS_HWBUFEINT_Pos) |
UART_T::INTSTS: HWBUFEINT Mask
Definition at line 1092 of file uart_reg.h.
| #define UART_INTSTS_HWBUFEINT_Pos (29) |
UART_T::INTSTS: HWBUFEINT Position
Definition at line 1091 of file uart_reg.h.
| #define UART_INTSTS_HWMODIF_Msk (0x1ul << UART_INTSTS_HWMODIF_Pos) |
UART_T::INTSTS: HWMODIF Mask
Definition at line 1071 of file uart_reg.h.
| #define UART_INTSTS_HWMODIF_Pos (19) |
UART_T::INTSTS: HWMODIF Position
Definition at line 1070 of file uart_reg.h.
| #define UART_INTSTS_HWMODINT_Msk (0x1ul << UART_INTSTS_HWMODINT_Pos) |
UART_T::INTSTS: HWMODINT Mask
Definition at line 1086 of file uart_reg.h.
| #define UART_INTSTS_HWMODINT_Pos (27) |
UART_T::INTSTS: HWMODINT Position
Definition at line 1085 of file uart_reg.h.
| #define UART_INTSTS_HWRLSIF_Msk (0x1ul << UART_INTSTS_HWRLSIF_Pos) |
UART_T::INTSTS: HWRLSIF Mask
Definition at line 1068 of file uart_reg.h.
| #define UART_INTSTS_HWRLSIF_Pos (18) |
UART_T::INTSTS: HWRLSIF Position
Definition at line 1067 of file uart_reg.h.
| #define UART_INTSTS_HWRLSINT_Msk (0x1ul << UART_INTSTS_HWRLSINT_Pos) |
UART_T::INTSTS: HWRLSINT Mask
Definition at line 1083 of file uart_reg.h.
| #define UART_INTSTS_HWRLSINT_Pos (26) |
UART_T::INTSTS: HWRLSINT Position
Definition at line 1082 of file uart_reg.h.
| #define UART_INTSTS_HWTOIF_Msk (0x1ul << UART_INTSTS_HWTOIF_Pos) |
UART_T::INTSTS: HWTOIF Mask
Definition at line 1074 of file uart_reg.h.
| #define UART_INTSTS_HWTOIF_Pos (20) |
UART_T::INTSTS: HWTOIF Position
Definition at line 1073 of file uart_reg.h.
| #define UART_INTSTS_HWTOINT_Msk (0x1ul << UART_INTSTS_HWTOINT_Pos) |
UART_T::INTSTS: HWTOINT Mask
Definition at line 1089 of file uart_reg.h.
| #define UART_INTSTS_HWTOINT_Pos (28) |
UART_T::INTSTS: HWTOINT Position
Definition at line 1088 of file uart_reg.h.
| #define UART_INTSTS_LINIF_Msk (0x1ul << UART_INTSTS_LINIF_Pos) |
UART_T::INTSTS: LINIF Mask
Definition at line 1041 of file uart_reg.h.
| #define UART_INTSTS_LINIF_Pos (7) |
UART_T::INTSTS: LINIF Position
Definition at line 1040 of file uart_reg.h.
| #define UART_INTSTS_LININT_Msk (0x1ul << UART_INTSTS_LININT_Pos) |
UART_T::INTSTS: LININT Mask
Definition at line 1065 of file uart_reg.h.
| #define UART_INTSTS_LININT_Pos (15) |
UART_T::INTSTS: LININT Position
Definition at line 1064 of file uart_reg.h.
| #define UART_INTSTS_MODEMIF_Msk (0x1ul << UART_INTSTS_MODEMIF_Pos) |
UART_T::INTSTS: MODEMIF Mask
Definition at line 1029 of file uart_reg.h.
| #define UART_INTSTS_MODEMIF_Pos (3) |
UART_T::INTSTS: MODEMIF Position
Definition at line 1028 of file uart_reg.h.
| #define UART_INTSTS_MODEMINT_Msk (0x1ul << UART_INTSTS_MODEMINT_Pos) |
UART_T::INTSTS: MODEMINT Mask
Definition at line 1053 of file uart_reg.h.
| #define UART_INTSTS_MODEMINT_Pos (11) |
UART_T::INTSTS: MODEMINT Position
Definition at line 1052 of file uart_reg.h.
| #define UART_INTSTS_RDAIF_Msk (0x1ul << UART_INTSTS_RDAIF_Pos) |
UART_T::INTSTS: RDAIF Mask
Definition at line 1020 of file uart_reg.h.
| #define UART_INTSTS_RDAIF_Pos (0) |
UART_T::INTSTS: RDAIF Position
Definition at line 1019 of file uart_reg.h.
| #define UART_INTSTS_RDAINT_Msk (0x1ul << UART_INTSTS_RDAINT_Pos) |
UART_T::INTSTS: RDAINT Mask
Definition at line 1044 of file uart_reg.h.
| #define UART_INTSTS_RDAINT_Pos (8) |
UART_T::INTSTS: RDAINT Position
Definition at line 1043 of file uart_reg.h.
| #define UART_INTSTS_RLSIF_Msk (0x1ul << UART_INTSTS_RLSIF_Pos) |
UART_T::INTSTS: RLSIF Mask
Definition at line 1026 of file uart_reg.h.
| #define UART_INTSTS_RLSIF_Pos (2) |
UART_T::INTSTS: RLSIF Position
Definition at line 1025 of file uart_reg.h.
| #define UART_INTSTS_RLSINT_Msk (0x1ul << UART_INTSTS_RLSINT_Pos) |
UART_T::INTSTS: RLSINT Mask
Definition at line 1050 of file uart_reg.h.
| #define UART_INTSTS_RLSINT_Pos (10) |
UART_T::INTSTS: RLSINT Position
Definition at line 1049 of file uart_reg.h.
| #define UART_INTSTS_RXTOIF_Msk (0x1ul << UART_INTSTS_RXTOIF_Pos) |
UART_T::INTSTS: RXTOIF Mask
Definition at line 1032 of file uart_reg.h.
| #define UART_INTSTS_RXTOIF_Pos (4) |
UART_T::INTSTS: RXTOIF Position
Definition at line 1031 of file uart_reg.h.
| #define UART_INTSTS_RXTOINT_Msk (0x1ul << UART_INTSTS_RXTOINT_Pos) |
UART_T::INTSTS: RXTOINT Mask
Definition at line 1056 of file uart_reg.h.
| #define UART_INTSTS_RXTOINT_Pos (12) |
UART_T::INTSTS: RXTOINT Position
Definition at line 1055 of file uart_reg.h.
| #define UART_INTSTS_THREIF_Msk (0x1ul << UART_INTSTS_THREIF_Pos) |
UART_T::INTSTS: THREIF Mask
Definition at line 1023 of file uart_reg.h.
| #define UART_INTSTS_THREIF_Pos (1) |
UART_T::INTSTS: THREIF Position
Definition at line 1022 of file uart_reg.h.
| #define UART_INTSTS_THREINT_Msk (0x1ul << UART_INTSTS_THREINT_Pos) |
UART_T::INTSTS: THREINT Mask
Definition at line 1047 of file uart_reg.h.
| #define UART_INTSTS_THREINT_Pos (9) |
UART_T::INTSTS: THREINT Position
Definition at line 1046 of file uart_reg.h.
| #define UART_INTSTS_TXENDIF_Msk (0x1ul << UART_INTSTS_TXENDIF_Pos) |
UART_T::INTSTS: TXENDIF Mask
Definition at line 1080 of file uart_reg.h.
| #define UART_INTSTS_TXENDIF_Pos (22) |
UART_T::INTSTS: TXENDIF Position
Definition at line 1079 of file uart_reg.h.
| #define UART_INTSTS_TXENDINT_Msk (0x1ul << UART_INTSTS_TXENDINT_Pos) |
UART_T::INTSTS: TXENDINT Mask
Definition at line 1095 of file uart_reg.h.
| #define UART_INTSTS_TXENDINT_Pos (30) |
UART_T::INTSTS: TXENDINT Position
Definition at line 1094 of file uart_reg.h.
| #define UART_INTSTS_WKIF_Msk (0x1ul << UART_INTSTS_WKIF_Pos) |
UART_T::INTSTS: WKIF Mask
Definition at line 1038 of file uart_reg.h.
| #define UART_INTSTS_WKIF_Pos (6) |
UART_T::INTSTS: WKIF Position
Definition at line 1037 of file uart_reg.h.
| #define UART_INTSTS_WKINT_Msk (0x1ul << UART_INTSTS_WKINT_Pos) |
UART_T::INTSTS: WKINT Mask
Definition at line 1062 of file uart_reg.h.
| #define UART_INTSTS_WKINT_Pos (14) |
UART_T::INTSTS: WKINT Position
Definition at line 1061 of file uart_reg.h.
| #define UART_IRDA_RXINV_Msk (0x1ul << UART_IRDA_RXINV_Pos) |
UART_T::IRDA: RXINV Mask
Definition at line 1125 of file uart_reg.h.
| #define UART_IRDA_RXINV_Pos (6) |
UART_T::IRDA: RXINV Position
Definition at line 1124 of file uart_reg.h.
| #define UART_IRDA_TXEN_Msk (0x1ul << UART_IRDA_TXEN_Pos) |
UART_T::IRDA: TXEN Mask
Definition at line 1119 of file uart_reg.h.
| #define UART_IRDA_TXEN_Pos (1) |
UART_T::IRDA: TXEN Position
Definition at line 1118 of file uart_reg.h.
| #define UART_IRDA_TXINV_Msk (0x1ul << UART_IRDA_TXINV_Pos) |
UART_T::IRDA: TXINV Mask
Definition at line 1122 of file uart_reg.h.
| #define UART_IRDA_TXINV_Pos (5) |
UART_T::IRDA: TXINV Position
Definition at line 1121 of file uart_reg.h.
| #define UART_LINCTL_BITERREN_Msk (0x1ul << UART_LINCTL_BITERREN_Pos) |
UART_T::LINCTL: BITERREN Mask
Definition at line 1194 of file uart_reg.h.
| #define UART_LINCTL_BITERREN_Pos (12) |
UART_T::LINCTL: BITERREN Position
Definition at line 1193 of file uart_reg.h.
| #define UART_LINCTL_BRKDETEN_Msk (0x1ul << UART_LINCTL_BRKDETEN_Pos) |
UART_T::LINCTL: BRKDETEN Mask
Definition at line 1188 of file uart_reg.h.
| #define UART_LINCTL_BRKDETEN_Pos (10) |
UART_T::LINCTL: BRKDETEN Position
Definition at line 1187 of file uart_reg.h.
| #define UART_LINCTL_BRKFL_Msk (0xful << UART_LINCTL_BRKFL_Pos) |
UART_T::LINCTL: BRKFL Mask
Definition at line 1197 of file uart_reg.h.
| #define UART_LINCTL_BRKFL_Pos (16) |
UART_T::LINCTL: BRKFL Position
Definition at line 1196 of file uart_reg.h.
| #define UART_LINCTL_BSL_Msk (0x3ul << UART_LINCTL_BSL_Pos) |
UART_T::LINCTL: BSL Mask
Definition at line 1200 of file uart_reg.h.
| #define UART_LINCTL_BSL_Pos (20) |
UART_T::LINCTL: BSL Position
Definition at line 1199 of file uart_reg.h.
| #define UART_LINCTL_HSEL_Msk (0x3ul << UART_LINCTL_HSEL_Pos) |
UART_T::LINCTL: HSEL Mask
Definition at line 1203 of file uart_reg.h.
| #define UART_LINCTL_HSEL_Pos (22) |
UART_T::LINCTL: HSEL Position
Definition at line 1202 of file uart_reg.h.
| #define UART_LINCTL_IDPEN_Msk (0x1ul << UART_LINCTL_IDPEN_Pos) |
UART_T::LINCTL: IDPEN Mask
Definition at line 1185 of file uart_reg.h.
| #define UART_LINCTL_IDPEN_Pos (9) |
UART_T::LINCTL: IDPEN Position
Definition at line 1184 of file uart_reg.h.
| #define UART_LINCTL_LINRXOFF_Msk (0x1ul << UART_LINCTL_LINRXOFF_Pos) |
UART_T::LINCTL: LINRXOFF Mask
Definition at line 1191 of file uart_reg.h.
| #define UART_LINCTL_LINRXOFF_Pos (11) |
UART_T::LINCTL: LINRXOFF Position
Definition at line 1190 of file uart_reg.h.
| #define UART_LINCTL_MUTE_Msk (0x1ul << UART_LINCTL_MUTE_Pos) |
UART_T::LINCTL: MUTE Mask
Definition at line 1179 of file uart_reg.h.
| #define UART_LINCTL_MUTE_Pos (4) |
UART_T::LINCTL: MUTE Position
Definition at line 1178 of file uart_reg.h.
| #define UART_LINCTL_PID_Msk (0xfful << UART_LINCTL_PID_Pos) |
UART_T::LINCTL: PID Mask
Definition at line 1206 of file uart_reg.h.
| #define UART_LINCTL_PID_Pos (24) |
UART_T::LINCTL: PID Position
Definition at line 1205 of file uart_reg.h.
| #define UART_LINCTL_SENDH_Msk (0x1ul << UART_LINCTL_SENDH_Pos) |
UART_T::LINCTL: SENDH Mask
Definition at line 1182 of file uart_reg.h.
| #define UART_LINCTL_SENDH_Pos (8) |
UART_T::LINCTL: SENDH Position
Definition at line 1181 of file uart_reg.h.
| #define UART_LINCTL_SLVAREN_Msk (0x1ul << UART_LINCTL_SLVAREN_Pos) |
UART_T::LINCTL: SLVAREN Mask
Definition at line 1173 of file uart_reg.h.
| #define UART_LINCTL_SLVAREN_Pos (2) |
UART_T::LINCTL: SLVAREN Position
Definition at line 1172 of file uart_reg.h.
| #define UART_LINCTL_SLVDUEN_Msk (0x1ul << UART_LINCTL_SLVDUEN_Pos) |
UART_T::LINCTL: SLVDUEN Mask
Definition at line 1176 of file uart_reg.h.
| #define UART_LINCTL_SLVDUEN_Pos (3) |
UART_T::LINCTL: SLVDUEN Position
Definition at line 1175 of file uart_reg.h.
| #define UART_LINCTL_SLVEN_Msk (0x1ul << UART_LINCTL_SLVEN_Pos) |
UART_T::LINCTL: SLVEN Mask
Definition at line 1167 of file uart_reg.h.
| #define UART_LINCTL_SLVEN_Pos (0) |
UART_T::LINCTL: SLVEN Position
Definition at line 1166 of file uart_reg.h.
| #define UART_LINCTL_SLVHDEN_Msk (0x1ul << UART_LINCTL_SLVHDEN_Pos) |
UART_T::LINCTL: SLVHDEN Mask
Definition at line 1170 of file uart_reg.h.
| #define UART_LINCTL_SLVHDEN_Pos (1) |
UART_T::LINCTL: SLVHDEN Position
Definition at line 1169 of file uart_reg.h.
| #define UART_LINE_BCB_Msk (0x1ul << UART_LINE_BCB_Pos) |
UART_T::LINE: BCB Mask
Definition at line 939 of file uart_reg.h.
| #define UART_LINE_BCB_Pos (6) |
UART_T::LINE: BCB Position
Definition at line 938 of file uart_reg.h.
| #define UART_LINE_EPE_Msk (0x1ul << UART_LINE_EPE_Pos) |
UART_T::LINE: EPE Mask
Definition at line 933 of file uart_reg.h.
| #define UART_LINE_EPE_Pos (4) |
UART_T::LINE: EPE Position
Definition at line 932 of file uart_reg.h.
| #define UART_LINE_NSB_Msk (0x1ul << UART_LINE_NSB_Pos) |
UART_T::LINE: NSB Mask
Definition at line 927 of file uart_reg.h.
| #define UART_LINE_NSB_Pos (2) |
UART_T::LINE: NSB Position
Definition at line 926 of file uart_reg.h.
| #define UART_LINE_PBE_Msk (0x1ul << UART_LINE_PBE_Pos) |
UART_T::LINE: PBE Mask
Definition at line 930 of file uart_reg.h.
| #define UART_LINE_PBE_Pos (3) |
UART_T::LINE: PBE Position
Definition at line 929 of file uart_reg.h.
| #define UART_LINE_PSS_Msk (0x1ul << UART_LINE_PSS_Pos) |
UART_T::LINE: PSS Mask
Definition at line 942 of file uart_reg.h.
| #define UART_LINE_PSS_Pos (7) |
UART_T::LINE: PSS Position
Definition at line 941 of file uart_reg.h.
| #define UART_LINE_RXDINV_Msk (0x1ul << UART_LINE_RXDINV_Pos) |
UART_T::LINE: RXDINV Mask
Definition at line 948 of file uart_reg.h.
| #define UART_LINE_RXDINV_Pos (9) |
UART_T::LINE: RXDINV Position
Definition at line 947 of file uart_reg.h.
| #define UART_LINE_SPE_Msk (0x1ul << UART_LINE_SPE_Pos) |
UART_T::LINE: SPE Mask
Definition at line 936 of file uart_reg.h.
| #define UART_LINE_SPE_Pos (5) |
UART_T::LINE: SPE Position
Definition at line 935 of file uart_reg.h.
| #define UART_LINE_TXDINV_Msk (0x1ul << UART_LINE_TXDINV_Pos) |
UART_T::LINE: TXDINV Mask
Definition at line 945 of file uart_reg.h.
| #define UART_LINE_TXDINV_Pos (8) |
UART_T::LINE: TXDINV Position
Definition at line 944 of file uart_reg.h.
| #define UART_LINE_WLS_Msk (0x3ul << UART_LINE_WLS_Pos) |
UART_T::LINE: WLS Mask
Definition at line 924 of file uart_reg.h.
| #define UART_LINE_WLS_Pos (0) |
UART_T::LINE: WLS Position
Definition at line 923 of file uart_reg.h.
| #define UART_LINSTS_BITEF_Msk (0x1ul << UART_LINSTS_BITEF_Pos) |
UART_T::LINSTS: BITEF Mask
Definition at line 1224 of file uart_reg.h.
| #define UART_LINSTS_BITEF_Pos (9) |
UART_T::LINSTS: BITEF Position
Definition at line 1223 of file uart_reg.h.
| #define UART_LINSTS_BRKDETF_Msk (0x1ul << UART_LINSTS_BRKDETF_Pos) |
UART_T::LINSTS: BRKDETF Mask
Definition at line 1221 of file uart_reg.h.
| #define UART_LINSTS_BRKDETF_Pos (8) |
UART_T::LINSTS: BRKDETF Position
Definition at line 1220 of file uart_reg.h.
| #define UART_LINSTS_SLVHDETF_Msk (0x1ul << UART_LINSTS_SLVHDETF_Pos) |
UART_T::LINSTS: SLVHDETF Mask
Definition at line 1209 of file uart_reg.h.
| #define UART_LINSTS_SLVHDETF_Pos (0) |
UART_T::LINSTS: SLVHDETF Position
Definition at line 1208 of file uart_reg.h.
| #define UART_LINSTS_SLVHEF_Msk (0x1ul << UART_LINSTS_SLVHEF_Pos) |
UART_T::LINSTS: SLVHEF Mask
Definition at line 1212 of file uart_reg.h.
| #define UART_LINSTS_SLVHEF_Pos (1) |
UART_T::LINSTS: SLVHEF Position
Definition at line 1211 of file uart_reg.h.
| #define UART_LINSTS_SLVIDPEF_Msk (0x1ul << UART_LINSTS_SLVIDPEF_Pos) |
UART_T::LINSTS: SLVIDPEF Mask
Definition at line 1215 of file uart_reg.h.
| #define UART_LINSTS_SLVIDPEF_Pos (2) |
UART_T::LINSTS: SLVIDPEF Position
Definition at line 1214 of file uart_reg.h.
| #define UART_LINSTS_SLVSYNCF_Msk (0x1ul << UART_LINSTS_SLVSYNCF_Pos) |
UART_T::LINSTS: SLVSYNCF Mask
Definition at line 1218 of file uart_reg.h.
| #define UART_LINSTS_SLVSYNCF_Pos (3) |
UART_T::LINSTS: SLVSYNCF Position
Definition at line 1217 of file uart_reg.h.
| #define UART_MODEM_RTS_Msk (0x1ul << UART_MODEM_RTS_Pos) |
UART_T::MODEM: RTS Mask
Definition at line 951 of file uart_reg.h.
| #define UART_MODEM_RTS_Pos (1) |
UART_T::MODEM: RTS Position
Definition at line 950 of file uart_reg.h.
| #define UART_MODEM_RTSACTLV_Msk (0x1ul << UART_MODEM_RTSACTLV_Pos) |
UART_T::MODEM: RTSACTLV Mask
Definition at line 954 of file uart_reg.h.
| #define UART_MODEM_RTSACTLV_Pos (9) |
UART_T::MODEM: RTSACTLV Position
Definition at line 953 of file uart_reg.h.
| #define UART_MODEM_RTSSTS_Msk (0x1ul << UART_MODEM_RTSSTS_Pos) |
UART_T::MODEM: RTSSTS Mask
Definition at line 957 of file uart_reg.h.
| #define UART_MODEM_RTSSTS_Pos (13) |
UART_T::MODEM: RTSSTS Position
Definition at line 956 of file uart_reg.h.
| #define UART_MODEMSTS_CTSACTLV_Msk (0x1ul << UART_MODEMSTS_CTSACTLV_Pos) |
UART_T::MODEMSTS: CTSACTLV Mask
Definition at line 966 of file uart_reg.h.
| #define UART_MODEMSTS_CTSACTLV_Pos (8) |
UART_T::MODEMSTS: CTSACTLV Position
Definition at line 965 of file uart_reg.h.
| #define UART_MODEMSTS_CTSDETF_Msk (0x1ul << UART_MODEMSTS_CTSDETF_Pos) |
UART_T::MODEMSTS: CTSDETF Mask
Definition at line 960 of file uart_reg.h.
| #define UART_MODEMSTS_CTSDETF_Pos (0) |
UART_T::MODEMSTS: CTSDETF Position
Definition at line 959 of file uart_reg.h.
| #define UART_MODEMSTS_CTSSTS_Msk (0x1ul << UART_MODEMSTS_CTSSTS_Pos) |
UART_T::MODEMSTS: CTSSTS Mask
Definition at line 963 of file uart_reg.h.
| #define UART_MODEMSTS_CTSSTS_Pos (4) |
UART_T::MODEMSTS: CTSSTS Position
Definition at line 962 of file uart_reg.h.
| #define UART_TOUT_DLY_Msk (0xfful << UART_TOUT_DLY_Pos) |
UART_T::TOUT: DLY Mask
Definition at line 1104 of file uart_reg.h.
| #define UART_TOUT_DLY_Pos (8) |
UART_T::TOUT: DLY Position
Definition at line 1103 of file uart_reg.h.
| #define UART_TOUT_TOIC_Msk (0xfful << UART_TOUT_TOIC_Pos) |
UART_T::TOUT: TOIC Mask
Definition at line 1101 of file uart_reg.h.
| #define UART_TOUT_TOIC_Pos (0) |
UART_T::TOUT: TOIC Position
Definition at line 1100 of file uart_reg.h.
| #define UART_WKCTL_WKCTSEN_Msk (0x1ul << UART_WKCTL_WKCTSEN_Pos) |
UART_T::WKCTL: WKCTSEN Mask
Definition at line 1233 of file uart_reg.h.
| #define UART_WKCTL_WKCTSEN_Pos (0) |
UART_T::WKCTL: WKCTSEN Position
Definition at line 1232 of file uart_reg.h.
| #define UART_WKCTL_WKDATEN_Msk (0x1ul << UART_WKCTL_WKDATEN_Pos) |
UART_T::WKCTL: WKDATEN Mask
Definition at line 1236 of file uart_reg.h.
| #define UART_WKCTL_WKDATEN_Pos (1) |
UART_T::WKCTL: WKDATEN Position
Definition at line 1235 of file uart_reg.h.
| #define UART_WKCTL_WKRFRTEN_Msk (0x1ul << UART_WKCTL_WKRFRTEN_Pos) |
UART_T::WKCTL: WKRFRTEN Mask
Definition at line 1239 of file uart_reg.h.
| #define UART_WKCTL_WKRFRTEN_Pos (2) |
UART_T::WKCTL: WKRFRTEN Position
Definition at line 1238 of file uart_reg.h.
| #define UART_WKCTL_WKRS485EN_Msk (0x1ul << UART_WKCTL_WKRS485EN_Pos) |
UART_T::WKCTL: WKRS485EN Mask
Definition at line 1242 of file uart_reg.h.
| #define UART_WKCTL_WKRS485EN_Pos (3) |
UART_T::WKCTL: WKRS485EN Position
Definition at line 1241 of file uart_reg.h.
| #define UART_WKCTL_WKTOUTEN_Msk (0x1ul << UART_WKCTL_WKTOUTEN_Pos) |
UART_T::WKCTL: WKTOUTEN Mask
Definition at line 1245 of file uart_reg.h.
| #define UART_WKCTL_WKTOUTEN_Pos (4) |
UART_T::WKCTL: WKTOUTEN Position
Definition at line 1244 of file uart_reg.h.
| #define UART_WKSTS_CTSWKF_Msk (0x1ul << UART_WKSTS_CTSWKF_Pos) |
UART_T::WKSTS: CTSWKF Mask
Definition at line 1248 of file uart_reg.h.
| #define UART_WKSTS_CTSWKF_Pos (0) |
UART_T::WKSTS: CTSWKF Position
Definition at line 1247 of file uart_reg.h.
| #define UART_WKSTS_DATWKF_Msk (0x1ul << UART_WKSTS_DATWKF_Pos) |
UART_T::WKSTS: DATWKF Mask
Definition at line 1251 of file uart_reg.h.
| #define UART_WKSTS_DATWKF_Pos (1) |
UART_T::WKSTS: DATWKF Position
Definition at line 1250 of file uart_reg.h.
| #define UART_WKSTS_RFRTWKF_Msk (0x1ul << UART_WKSTS_RFRTWKF_Pos) |
UART_T::WKSTS: RFRTWKF Mask
Definition at line 1254 of file uart_reg.h.
| #define UART_WKSTS_RFRTWKF_Pos (2) |
UART_T::WKSTS: RFRTWKF Position
Definition at line 1253 of file uart_reg.h.
| #define UART_WKSTS_RS485WKF_Msk (0x1ul << UART_WKSTS_RS485WKF_Pos) |
UART_T::WKSTS: RS485WKF Mask
Definition at line 1257 of file uart_reg.h.
| #define UART_WKSTS_RS485WKF_Pos (3) |
UART_T::WKSTS: RS485WKF Position
Definition at line 1256 of file uart_reg.h.
| #define UART_WKSTS_TOUTWKF_Msk (0x1ul << UART_WKSTS_TOUTWKF_Pos) |
UART_T::WKSTS: TOUTWKF Mask
Definition at line 1260 of file uart_reg.h.
| #define UART_WKSTS_TOUTWKF_Pos (4) |
UART_T::WKSTS: TOUTWKF Position
Definition at line 1259 of file uart_reg.h.
| #define USBD_ATTR_BYTEM_Msk (0x1ul << USBD_ATTR_BYTEM_Pos) |
USBD_T::ATTR: BYTEM Mask
Definition at line 546 of file usbd_reg.h.
| #define USBD_ATTR_BYTEM_Pos (10) |
USBD_T::ATTR: BYTEM Position
Definition at line 545 of file usbd_reg.h.
| #define USBD_ATTR_DPPUEN_Msk (0x1ul << USBD_ATTR_DPPUEN_Pos) |
USBD_T::ATTR: DPPUEN Mask
Definition at line 543 of file usbd_reg.h.
| #define USBD_ATTR_DPPUEN_Pos (8) |
USBD_T::ATTR: DPPUEN Position
Definition at line 542 of file usbd_reg.h.
| #define USBD_ATTR_L1RESUME_Msk (0x1ul << USBD_ATTR_L1RESUME_Pos) |
USBD_T::ATTR: L1RESUME Mask
Definition at line 555 of file usbd_reg.h.
| #define USBD_ATTR_L1RESUME_Pos (13) |
USBD_T::ATTR: L1RESUME Position
Definition at line 554 of file usbd_reg.h.
| #define USBD_ATTR_L1SUSPEND_Msk (0x1ul << USBD_ATTR_L1SUSPEND_Pos) |
USBD_T::ATTR: L1SUSPEND Mask
Definition at line 552 of file usbd_reg.h.
| #define USBD_ATTR_L1SUSPEND_Pos (12) |
USBD_T::ATTR: L1SUSPEND Position
Definition at line 551 of file usbd_reg.h.
| #define USBD_ATTR_LPMACK_Msk (0x1ul << USBD_ATTR_LPMACK_Pos) |
USBD_T::ATTR: LPMACK Mask
Definition at line 549 of file usbd_reg.h.
| #define USBD_ATTR_LPMACK_Pos (11) |
USBD_T::ATTR: LPMACK Position
Definition at line 548 of file usbd_reg.h.
| #define USBD_ATTR_PHYEN_Msk (0x1ul << USBD_ATTR_PHYEN_Pos) |
USBD_T::ATTR: PHYEN Mask
Definition at line 534 of file usbd_reg.h.
| #define USBD_ATTR_PHYEN_Pos (4) |
USBD_T::ATTR: PHYEN Position
Definition at line 533 of file usbd_reg.h.
| #define USBD_ATTR_RESUME_Msk (0x1ul << USBD_ATTR_RESUME_Pos) |
USBD_T::ATTR: RESUME Mask
Definition at line 528 of file usbd_reg.h.
| #define USBD_ATTR_RESUME_Pos (2) |
USBD_T::ATTR: RESUME Position
Definition at line 527 of file usbd_reg.h.
| #define USBD_ATTR_RWAKEUP_Msk (0x1ul << USBD_ATTR_RWAKEUP_Pos) |
USBD_T::ATTR: RWAKEUP Mask
Definition at line 537 of file usbd_reg.h.
| #define USBD_ATTR_RWAKEUP_Pos (5) |
USBD_T::ATTR: RWAKEUP Position
Definition at line 536 of file usbd_reg.h.
| #define USBD_ATTR_SUSPEND_Msk (0x1ul << USBD_ATTR_SUSPEND_Pos) |
USBD_T::ATTR: SUSPEND Mask
Definition at line 525 of file usbd_reg.h.
| #define USBD_ATTR_SUSPEND_Pos (1) |
USBD_T::ATTR: SUSPEND Position
Definition at line 524 of file usbd_reg.h.
| #define USBD_ATTR_TOUT_Msk (0x1ul << USBD_ATTR_TOUT_Pos) |
USBD_T::ATTR: TOUT Mask
Definition at line 531 of file usbd_reg.h.
| #define USBD_ATTR_TOUT_Pos (3) |
USBD_T::ATTR: TOUT Position
Definition at line 530 of file usbd_reg.h.
| #define USBD_ATTR_USBEN_Msk (0x1ul << USBD_ATTR_USBEN_Pos) |
USBD_T::ATTR: USBEN Mask
Definition at line 540 of file usbd_reg.h.
| #define USBD_ATTR_USBEN_Pos (7) |
USBD_T::ATTR: USBEN Position
Definition at line 539 of file usbd_reg.h.
| #define USBD_ATTR_USBRST_Msk (0x1ul << USBD_ATTR_USBRST_Pos) |
USBD_T::ATTR: USBRST Mask
Definition at line 522 of file usbd_reg.h.
| #define USBD_ATTR_USBRST_Pos (0) |
USBD_T::ATTR: USBRST Position
Definition at line 521 of file usbd_reg.h.
| #define USBD_BUFSEG_BUFSEG_Msk (0x3ful << USBD_BUFSEG_BUFSEG_Pos) |
USBD_EP_T::BUFSEG: BUFSEG Mask
Definition at line 615 of file usbd_reg.h.
| #define USBD_BUFSEG_BUFSEG_Pos (3) |
USBD_EP_T::BUFSEG: BUFSEG Position
Definition at line 614 of file usbd_reg.h.
| #define USBD_CFG_CSTALL_Msk (0x1ul << USBD_CFG_CSTALL_Pos) |
USBD_EP_T::CFG: CSTALL Mask
Definition at line 633 of file usbd_reg.h.
| #define USBD_CFG_CSTALL_Pos (9) |
USBD_EP_T::CFG: CSTALL Position
Definition at line 632 of file usbd_reg.h.
| #define USBD_CFG_DSQSYNC_Msk (0x1ul << USBD_CFG_DSQSYNC_Pos) |
USBD_EP_T::CFG: DSQSYNC Mask
Definition at line 630 of file usbd_reg.h.
| #define USBD_CFG_DSQSYNC_Pos (7) |
USBD_EP_T::CFG: DSQSYNC Position
Definition at line 629 of file usbd_reg.h.
| #define USBD_CFG_EPNUM_Msk (0xful << USBD_CFG_EPNUM_Pos) |
USBD_EP_T::CFG: EPNUM Mask
Definition at line 621 of file usbd_reg.h.
| #define USBD_CFG_EPNUM_Pos (0) |
USBD_EP_T::CFG: EPNUM Position
Definition at line 620 of file usbd_reg.h.
| #define USBD_CFG_ISOCH_Msk (0x1ul << USBD_CFG_ISOCH_Pos) |
USBD_EP_T::CFG: ISOCH Mask
Definition at line 624 of file usbd_reg.h.
| #define USBD_CFG_ISOCH_Pos (4) |
USBD_EP_T::CFG: ISOCH Position
Definition at line 623 of file usbd_reg.h.
| #define USBD_CFG_STATE_Msk (0x3ul << USBD_CFG_STATE_Pos) |
USBD_EP_T::CFG: STATE Mask
Definition at line 627 of file usbd_reg.h.
| #define USBD_CFG_STATE_Pos (5) |
USBD_EP_T::CFG: STATE Position
Definition at line 626 of file usbd_reg.h.
| #define USBD_CFGP_CLRRDY_Msk (0x1ul << USBD_CFGP_CLRRDY_Pos) |
USBD_EP_T::CFGP: CLRRDY Mask
Definition at line 636 of file usbd_reg.h.
| #define USBD_CFGP_CLRRDY_Pos (0) |
USBD_EP_T::CFGP: CLRRDY Position
Definition at line 635 of file usbd_reg.h.
| #define USBD_CFGP_SSTALL_Msk (0x1ul << USBD_CFGP_SSTALL_Pos) |
USBD_EP_T::CFGP: SSTALL Mask
Definition at line 639 of file usbd_reg.h.
| #define USBD_CFGP_SSTALL_Pos (1) |
USBD_EP_T::CFGP: SSTALL Position
Definition at line 638 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS0_Msk (0xful << USBD_EPSTS0_EPSTS0_Pos) |
USBD_T::EPSTS0: EPSTS0 Mask
Definition at line 564 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS0_Pos (0) |
USBD_T::EPSTS0: EPSTS0 Position
Definition at line 563 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS1_Msk (0xful << USBD_EPSTS0_EPSTS1_Pos) |
USBD_T::EPSTS0: EPSTS1 Mask
Definition at line 567 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS1_Pos (4) |
USBD_T::EPSTS0: EPSTS1 Position
Definition at line 566 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS2_Msk (0xful << USBD_EPSTS0_EPSTS2_Pos) |
USBD_T::EPSTS0: EPSTS2 Mask
Definition at line 570 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS2_Pos (8) |
USBD_T::EPSTS0: EPSTS2 Position
Definition at line 569 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS3_Msk (0xful << USBD_EPSTS0_EPSTS3_Pos) |
USBD_T::EPSTS0: EPSTS3 Mask
Definition at line 573 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS3_Pos (12) |
USBD_T::EPSTS0: EPSTS3 Position
Definition at line 572 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS4_Msk (0xful << USBD_EPSTS0_EPSTS4_Pos) |
USBD_T::EPSTS0: EPSTS4 Mask
Definition at line 576 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS4_Pos (16) |
USBD_T::EPSTS0: EPSTS4 Position
Definition at line 575 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS5_Msk (0xful << USBD_EPSTS0_EPSTS5_Pos) |
USBD_T::EPSTS0: EPSTS5 Mask
Definition at line 579 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS5_Pos (20) |
USBD_T::EPSTS0: EPSTS5 Position
Definition at line 578 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS6_Msk (0xful << USBD_EPSTS0_EPSTS6_Pos) |
USBD_T::EPSTS0: EPSTS6 Mask
Definition at line 582 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS6_Pos (24) |
USBD_T::EPSTS0: EPSTS6 Position
Definition at line 581 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS7_Msk (0xful << USBD_EPSTS0_EPSTS7_Pos) |
USBD_T::EPSTS0: EPSTS7 Mask
Definition at line 585 of file usbd_reg.h.
| #define USBD_EPSTS0_EPSTS7_Pos (28) |
USBD_T::EPSTS0: EPSTS7 Position
Definition at line 584 of file usbd_reg.h.
| #define USBD_EPSTS1_EPSTS10_Msk (0xful << USBD_EPSTS1_EPSTS10_Pos) |
USBD_T::EPSTS1: EPSTS10 Mask
Definition at line 594 of file usbd_reg.h.
| #define USBD_EPSTS1_EPSTS10_Pos (8) |
USBD_T::EPSTS1: EPSTS10 Position
Definition at line 593 of file usbd_reg.h.
| #define USBD_EPSTS1_EPSTS11_Msk (0xful << USBD_EPSTS1_EPSTS11_Pos) |
USBD_T::EPSTS1: EPSTS11 Mask
Definition at line 597 of file usbd_reg.h.
| #define USBD_EPSTS1_EPSTS11_Pos (12) |
USBD_T::EPSTS1: EPSTS11 Position
Definition at line 596 of file usbd_reg.h.
| #define USBD_EPSTS1_EPSTS8_Msk (0xful << USBD_EPSTS1_EPSTS8_Pos) |
USBD_T::EPSTS1: EPSTS8 Mask
Definition at line 588 of file usbd_reg.h.
| #define USBD_EPSTS1_EPSTS8_Pos (0) |
USBD_T::EPSTS1: EPSTS8 Position
Definition at line 587 of file usbd_reg.h.
| #define USBD_EPSTS1_EPSTS9_Msk (0xful << USBD_EPSTS1_EPSTS9_Pos) |
USBD_T::EPSTS1: EPSTS9 Mask
Definition at line 591 of file usbd_reg.h.
| #define USBD_EPSTS1_EPSTS9_Pos (4) |
USBD_T::EPSTS1: EPSTS9 Position
Definition at line 590 of file usbd_reg.h.
| #define USBD_EPSTS_OV_Msk (0x1ul << USBD_EPSTS_OV_Pos) |
USBD_T::EPSTS: OV Mask
Definition at line 519 of file usbd_reg.h.
| #define USBD_EPSTS_OV_Pos (7) |
USBD_T::EPSTS: OV Position
Definition at line 518 of file usbd_reg.h.
| #define USBD_FADDR_FADDR_Msk (0x7ful << USBD_FADDR_FADDR_Pos) |
USBD_T::FADDR: FADDR Mask
Definition at line 516 of file usbd_reg.h.
| #define USBD_FADDR_FADDR_Pos (0) |
USBD_T::FADDR: FADDR Position
Definition at line 515 of file usbd_reg.h.
| #define USBD_FN_FN_Msk (0x7fful << USBD_FN_FN_Pos) |
USBD_T::FN: FN Mask
Definition at line 609 of file usbd_reg.h.
| #define USBD_FN_FN_Pos (0) |
USBD_T::FN: FN Position
Definition at line 608 of file usbd_reg.h.
| #define USBD_INTEN_BUSIEN_Msk (0x1ul << USBD_INTEN_BUSIEN_Pos) |
USBD_T::INTEN: BUSIEN Mask
Definition at line 441 of file usbd_reg.h.
| #define USBD_INTEN_BUSIEN_Pos (0) |
@addtogroup USBD_CONST USBD Bit Field Definition Constant Definitions for USBD Controller
USBD_T::INTEN: BUSIEN Position
Definition at line 440 of file usbd_reg.h.
| #define USBD_INTEN_INNAKEN_Msk (0x1ul << USBD_INTEN_INNAKEN_Pos) |
USBD_T::INTEN: INNAKEN Mask
Definition at line 459 of file usbd_reg.h.
| #define USBD_INTEN_INNAKEN_Pos (15) |
USBD_T::INTEN: INNAKEN Position
Definition at line 458 of file usbd_reg.h.
| #define USBD_INTEN_NEVWKIEN_Msk (0x1ul << USBD_INTEN_NEVWKIEN_Pos) |
USBD_T::INTEN: NEVWKIEN Mask
Definition at line 450 of file usbd_reg.h.
| #define USBD_INTEN_NEVWKIEN_Pos (3) |
USBD_T::INTEN: NEVWKIEN Position
Definition at line 449 of file usbd_reg.h.
| #define USBD_INTEN_SOFIEN_Msk (0x1ul << USBD_INTEN_SOFIEN_Pos) |
USBD_T::INTEN: SOFIEN Mask
Definition at line 453 of file usbd_reg.h.
| #define USBD_INTEN_SOFIEN_Pos (4) |
USBD_T::INTEN: SOFIEN Position
Definition at line 452 of file usbd_reg.h.
| #define USBD_INTEN_USBIEN_Msk (0x1ul << USBD_INTEN_USBIEN_Pos) |
USBD_T::INTEN: USBIEN Mask
Definition at line 444 of file usbd_reg.h.
| #define USBD_INTEN_USBIEN_Pos (1) |
USBD_T::INTEN: USBIEN Position
Definition at line 443 of file usbd_reg.h.
| #define USBD_INTEN_VBDETIEN_Msk (0x1ul << USBD_INTEN_VBDETIEN_Pos) |
USBD_T::INTEN: VBDETIEN Mask
Definition at line 447 of file usbd_reg.h.
| #define USBD_INTEN_VBDETIEN_Pos (2) |
USBD_T::INTEN: VBDETIEN Position
Definition at line 446 of file usbd_reg.h.
| #define USBD_INTEN_WKEN_Msk (0x1ul << USBD_INTEN_WKEN_Pos) |
USBD_T::INTEN: WKEN Mask
Definition at line 456 of file usbd_reg.h.
| #define USBD_INTEN_WKEN_Pos (8) |
USBD_T::INTEN: WKEN Position
Definition at line 455 of file usbd_reg.h.
| #define USBD_INTSTS_BUSIF_Msk (0x1ul << USBD_INTSTS_BUSIF_Pos) |
USBD_T::INTSTS: BUSIF Mask
Definition at line 462 of file usbd_reg.h.
| #define USBD_INTSTS_BUSIF_Pos (0) |
USBD_T::INTSTS: BUSIF Position
Definition at line 461 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT0_Msk (0x1ul << USBD_INTSTS_EPEVT0_Pos) |
USBD_T::INTSTS: EPEVT0 Mask
Definition at line 477 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT0_Pos (16) |
USBD_T::INTSTS: EPEVT0 Position
Definition at line 476 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT10_Msk (0x1ul << USBD_INTSTS_EPEVT10_Pos) |
USBD_T::INTSTS: EPEVT10 Mask
Definition at line 507 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT10_Pos (26) |
USBD_T::INTSTS: EPEVT10 Position
Definition at line 506 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT11_Msk (0x1ul << USBD_INTSTS_EPEVT11_Pos) |
USBD_T::INTSTS: EPEVT11 Mask
Definition at line 510 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT11_Pos (27) |
USBD_T::INTSTS: EPEVT11 Position
Definition at line 509 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT1_Msk (0x1ul << USBD_INTSTS_EPEVT1_Pos) |
USBD_T::INTSTS: EPEVT1 Mask
Definition at line 480 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT1_Pos (17) |
USBD_T::INTSTS: EPEVT1 Position
Definition at line 479 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT2_Msk (0x1ul << USBD_INTSTS_EPEVT2_Pos) |
USBD_T::INTSTS: EPEVT2 Mask
Definition at line 483 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT2_Pos (18) |
USBD_T::INTSTS: EPEVT2 Position
Definition at line 482 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT3_Msk (0x1ul << USBD_INTSTS_EPEVT3_Pos) |
USBD_T::INTSTS: EPEVT3 Mask
Definition at line 486 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT3_Pos (19) |
USBD_T::INTSTS: EPEVT3 Position
Definition at line 485 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT4_Msk (0x1ul << USBD_INTSTS_EPEVT4_Pos) |
USBD_T::INTSTS: EPEVT4 Mask
Definition at line 489 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT4_Pos (20) |
USBD_T::INTSTS: EPEVT4 Position
Definition at line 488 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT5_Msk (0x1ul << USBD_INTSTS_EPEVT5_Pos) |
USBD_T::INTSTS: EPEVT5 Mask
Definition at line 492 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT5_Pos (21) |
USBD_T::INTSTS: EPEVT5 Position
Definition at line 491 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT6_Msk (0x1ul << USBD_INTSTS_EPEVT6_Pos) |
USBD_T::INTSTS: EPEVT6 Mask
Definition at line 495 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT6_Pos (22) |
USBD_T::INTSTS: EPEVT6 Position
Definition at line 494 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT7_Msk (0x1ul << USBD_INTSTS_EPEVT7_Pos) |
USBD_T::INTSTS: EPEVT7 Mask
Definition at line 498 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT7_Pos (23) |
USBD_T::INTSTS: EPEVT7 Position
Definition at line 497 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT8_Msk (0x1ul << USBD_INTSTS_EPEVT8_Pos) |
USBD_T::INTSTS: EPEVT8 Mask
Definition at line 501 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT8_Pos (24) |
USBD_T::INTSTS: EPEVT8 Position
Definition at line 500 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT9_Msk (0x1ul << USBD_INTSTS_EPEVT9_Pos) |
USBD_T::INTSTS: EPEVT9 Mask
Definition at line 504 of file usbd_reg.h.
| #define USBD_INTSTS_EPEVT9_Pos (25) |
USBD_T::INTSTS: EPEVT9 Position
Definition at line 503 of file usbd_reg.h.
| #define USBD_INTSTS_NEVWKIF_Msk (0x1ul << USBD_INTSTS_NEVWKIF_Pos) |
USBD_T::INTSTS: NEVWKIF Mask
Definition at line 471 of file usbd_reg.h.
| #define USBD_INTSTS_NEVWKIF_Pos (3) |
USBD_T::INTSTS: NEVWKIF Position
Definition at line 470 of file usbd_reg.h.
| #define USBD_INTSTS_SETUP_Msk (0x1ul << USBD_INTSTS_SETUP_Pos) |
USBD_T::INTSTS: SETUP Mask
Definition at line 513 of file usbd_reg.h.
| #define USBD_INTSTS_SETUP_Pos (31) |
USBD_T::INTSTS: SETUP Position
Definition at line 512 of file usbd_reg.h.
| #define USBD_INTSTS_SOFIF_Msk (0x1ul << USBD_INTSTS_SOFIF_Pos) |
USBD_T::INTSTS: SOFIF Mask
Definition at line 474 of file usbd_reg.h.
| #define USBD_INTSTS_SOFIF_Pos (4) |
USBD_T::INTSTS: SOFIF Position
Definition at line 473 of file usbd_reg.h.
| #define USBD_INTSTS_USBIF_Msk (0x1ul << USBD_INTSTS_USBIF_Pos) |
USBD_T::INTSTS: USBIF Mask
Definition at line 465 of file usbd_reg.h.
| #define USBD_INTSTS_USBIF_Pos (1) |
USBD_T::INTSTS: USBIF Position
Definition at line 464 of file usbd_reg.h.
| #define USBD_INTSTS_VBDETIF_Msk (0x1ul << USBD_INTSTS_VBDETIF_Pos) |
USBD_T::INTSTS: VBDETIF Mask
Definition at line 468 of file usbd_reg.h.
| #define USBD_INTSTS_VBDETIF_Pos (2) |
USBD_T::INTSTS: VBDETIF Position
Definition at line 467 of file usbd_reg.h.
| #define USBD_LPMATTR_LPMBESL_Msk (0xful << USBD_LPMATTR_LPMBESL_Pos) |
USBD_T::LPMATTR: LPMBESL Mask
Definition at line 603 of file usbd_reg.h.
| #define USBD_LPMATTR_LPMBESL_Pos (4) |
USBD_T::LPMATTR: LPMBESL Position
Definition at line 602 of file usbd_reg.h.
| #define USBD_LPMATTR_LPMLINKSTS_Msk (0xful << USBD_LPMATTR_LPMLINKSTS_Pos) |
USBD_T::LPMATTR: LPMLINKSTS Mask
Definition at line 600 of file usbd_reg.h.
| #define USBD_LPMATTR_LPMLINKSTS_Pos (0) |
USBD_T::LPMATTR: LPMLINKSTS Position
Definition at line 599 of file usbd_reg.h.
| #define USBD_LPMATTR_LPMRWAKUP_Msk (0x1ul << USBD_LPMATTR_LPMRWAKUP_Pos) |
USBD_T::LPMATTR: LPMRWAKUP Mask
Definition at line 606 of file usbd_reg.h.
| #define USBD_LPMATTR_LPMRWAKUP_Pos (8) |
USBD_T::LPMATTR: LPMRWAKUP Position
Definition at line 605 of file usbd_reg.h.
| #define USBD_MXPLD_MXPLD_Msk (0x1fful << USBD_MXPLD_MXPLD_Pos) |
USBD_EP_T::MXPLD: MXPLD Mask
Definition at line 618 of file usbd_reg.h.
| #define USBD_MXPLD_MXPLD_Pos (0) |
USBD_EP_T::MXPLD: MXPLD Position
Definition at line 617 of file usbd_reg.h.
| #define USBD_SE0_SE0_Msk (0x1ul << USBD_SE0_SE0_Pos) |
USBD_T::SE0: SE0 Mask
Definition at line 612 of file usbd_reg.h.
| #define USBD_SE0_SE0_Pos (0) |
USBD_T::SE0: SE0 Position
Definition at line 611 of file usbd_reg.h.
| #define USBD_STBUFSEG_STBUFSEG_Msk (0x3ful << USBD_STBUFSEG_STBUFSEG_Pos) |
USBD_T::STBUFSEG: STBUFSEG Mask
Definition at line 561 of file usbd_reg.h.
| #define USBD_STBUFSEG_STBUFSEG_Pos (3) |
USBD_T::STBUFSEG: STBUFSEG Position
Definition at line 560 of file usbd_reg.h.
| #define USBD_VBUSDET_VBUSDET_Msk (0x1ul << USBD_VBUSDET_VBUSDET_Pos) |
USBD_T::VBUSDET: VBUSDET Mask
Definition at line 558 of file usbd_reg.h.
| #define USBD_VBUSDET_VBUSDET_Pos (0) |
USBD_T::VBUSDET: VBUSDET Position
Definition at line 557 of file usbd_reg.h.
| #define USBH_HcBulkCurrentED_BCED_Msk (0xffffffful << USBH_HcBulkCurrentED_BCED_Pos) |
USBH_T::HcBulkCurrentED: BCED Mask
Definition at line 679 of file usbh_reg.h.
| #define USBH_HcBulkCurrentED_BCED_Pos (4) |
USBH_T::HcBulkCurrentED: BCED Position
Definition at line 678 of file usbh_reg.h.
| #define USBH_HcBulkHeadED_BHED_Msk (0xffffffful << USBH_HcBulkHeadED_BHED_Pos) |
USBH_T::HcBulkHeadED: BHED Mask
Definition at line 676 of file usbh_reg.h.
| #define USBH_HcBulkHeadED_BHED_Pos (4) |
USBH_T::HcBulkHeadED: BHED Position
Definition at line 675 of file usbh_reg.h.
| #define USBH_HcCommandStatus_BLF_Msk (0x1ul << USBH_HcCommandStatus_BLF_Pos) |
USBH_T::HcCommandStatus: BLF Mask
Definition at line 598 of file usbh_reg.h.
| #define USBH_HcCommandStatus_BLF_Pos (2) |
USBH_T::HcCommandStatus: BLF Position
Definition at line 597 of file usbh_reg.h.
| #define USBH_HcCommandStatus_CLF_Msk (0x1ul << USBH_HcCommandStatus_CLF_Pos) |
USBH_T::HcCommandStatus: CLF Mask
Definition at line 595 of file usbh_reg.h.
| #define USBH_HcCommandStatus_CLF_Pos (1) |
USBH_T::HcCommandStatus: CLF Position
Definition at line 594 of file usbh_reg.h.
| #define USBH_HcCommandStatus_HCR_Msk (0x1ul << USBH_HcCommandStatus_HCR_Pos) |
USBH_T::HcCommandStatus: HCR Mask
Definition at line 592 of file usbh_reg.h.
| #define USBH_HcCommandStatus_HCR_Pos (0) |
USBH_T::HcCommandStatus: HCR Position
Definition at line 591 of file usbh_reg.h.
| #define USBH_HcCommandStatus_SOC_Msk (0x3ul << USBH_HcCommandStatus_SOC_Pos) |
USBH_T::HcCommandStatus: SOC Mask
Definition at line 601 of file usbh_reg.h.
| #define USBH_HcCommandStatus_SOC_Pos (16) |
USBH_T::HcCommandStatus: SOC Position
Definition at line 600 of file usbh_reg.h.
| #define USBH_HcControl_BLE_Msk (0x1ul << USBH_HcControl_BLE_Pos) |
USBH_T::HcControl: BLE Mask
Definition at line 586 of file usbh_reg.h.
| #define USBH_HcControl_BLE_Pos (5) |
USBH_T::HcControl: BLE Position
Definition at line 585 of file usbh_reg.h.
| #define USBH_HcControl_CBSR_Msk (0x3ul << USBH_HcControl_CBSR_Pos) |
USBH_T::HcControl: CBSR Mask
Definition at line 574 of file usbh_reg.h.
| #define USBH_HcControl_CBSR_Pos (0) |
USBH_T::HcControl: CBSR Position
Definition at line 573 of file usbh_reg.h.
| #define USBH_HcControl_CLE_Msk (0x1ul << USBH_HcControl_CLE_Pos) |
USBH_T::HcControl: CLE Mask
Definition at line 583 of file usbh_reg.h.
| #define USBH_HcControl_CLE_Pos (4) |
USBH_T::HcControl: CLE Position
Definition at line 582 of file usbh_reg.h.
| #define USBH_HcControl_HCFS_Msk (0x3ul << USBH_HcControl_HCFS_Pos) |
USBH_T::HcControl: HCFS Mask
Definition at line 589 of file usbh_reg.h.
| #define USBH_HcControl_HCFS_Pos (6) |
USBH_T::HcControl: HCFS Position
Definition at line 588 of file usbh_reg.h.
| #define USBH_HcControl_IE_Msk (0x1ul << USBH_HcControl_IE_Pos) |
USBH_T::HcControl: IE Mask
Definition at line 580 of file usbh_reg.h.
| #define USBH_HcControl_IE_Pos (3) |
USBH_T::HcControl: IE Position
Definition at line 579 of file usbh_reg.h.
| #define USBH_HcControl_PLE_Msk (0x1ul << USBH_HcControl_PLE_Pos) |
USBH_T::HcControl: PLE Mask
Definition at line 577 of file usbh_reg.h.
| #define USBH_HcControl_PLE_Pos (2) |
USBH_T::HcControl: PLE Position
Definition at line 576 of file usbh_reg.h.
| #define USBH_HcControlCurrentED_CCED_Msk (0xffffffful << USBH_HcControlCurrentED_CCED_Pos) |
USBH_T::HcControlCurrentED: CCED Mask
Definition at line 673 of file usbh_reg.h.
| #define USBH_HcControlCurrentED_CCED_Pos (4) |
USBH_T::HcControlCurrentED: CCED Position
Definition at line 672 of file usbh_reg.h.
| #define USBH_HcControlHeadED_CHED_Msk (0xffffffful << USBH_HcControlHeadED_CHED_Pos) |
USBH_T::HcControlHeadED: CHED Mask
Definition at line 670 of file usbh_reg.h.
| #define USBH_HcControlHeadED_CHED_Pos (4) |
USBH_T::HcControlHeadED: CHED Position
Definition at line 669 of file usbh_reg.h.
| #define USBH_HcDoneHead_DH_Msk (0xffffffful << USBH_HcDoneHead_DH_Pos) |
USBH_T::HcDoneHead: DH Mask
Definition at line 682 of file usbh_reg.h.
| #define USBH_HcDoneHead_DH_Pos (4) |
USBH_T::HcDoneHead: DH Position
Definition at line 681 of file usbh_reg.h.
| #define USBH_HcFmInterval_FI_Msk (0x3ffful << USBH_HcFmInterval_FI_Pos) |
USBH_T::HcFmInterval: FI Mask
Definition at line 685 of file usbh_reg.h.
| #define USBH_HcFmInterval_FI_Pos (0) |
USBH_T::HcFmInterval: FI Position
Definition at line 684 of file usbh_reg.h.
| #define USBH_HcFmInterval_FIT_Msk (0x1ul << USBH_HcFmInterval_FIT_Pos) |
USBH_T::HcFmInterval: FIT Mask
Definition at line 691 of file usbh_reg.h.
| #define USBH_HcFmInterval_FIT_Pos (31) |
USBH_T::HcFmInterval: FIT Position
Definition at line 690 of file usbh_reg.h.
| #define USBH_HcFmInterval_FSMPS_Msk (0x7ffful << USBH_HcFmInterval_FSMPS_Pos) |
USBH_T::HcFmInterval: FSMPS Mask
Definition at line 688 of file usbh_reg.h.
| #define USBH_HcFmInterval_FSMPS_Pos (16) |
USBH_T::HcFmInterval: FSMPS Position
Definition at line 687 of file usbh_reg.h.
| #define USBH_HcFmNumber_FN_Msk (0xfffful << USBH_HcFmNumber_FN_Pos) |
USBH_T::HcFmNumber: FN Mask
Definition at line 700 of file usbh_reg.h.
| #define USBH_HcFmNumber_FN_Pos (0) |
USBH_T::HcFmNumber: FN Position
Definition at line 699 of file usbh_reg.h.
| #define USBH_HcFmRemaining_FR_Msk (0x3ffful << USBH_HcFmRemaining_FR_Pos) |
USBH_T::HcFmRemaining: FR Mask
Definition at line 694 of file usbh_reg.h.
| #define USBH_HcFmRemaining_FR_Pos (0) |
USBH_T::HcFmRemaining: FR Position
Definition at line 693 of file usbh_reg.h.
| #define USBH_HcFmRemaining_FRT_Msk (0x1ul << USBH_HcFmRemaining_FRT_Pos) |
USBH_T::HcFmRemaining: FRT Mask
Definition at line 697 of file usbh_reg.h.
| #define USBH_HcFmRemaining_FRT_Pos (31) |
USBH_T::HcFmRemaining: FRT Position
Definition at line 696 of file usbh_reg.h.
| #define USBH_HcHCCA_HCCA_Msk (0xfffffful << USBH_HcHCCA_HCCA_Pos) |
USBH_T::HcHCCA: HCCA Mask
Definition at line 664 of file usbh_reg.h.
| #define USBH_HcHCCA_HCCA_Pos (8) |
USBH_T::HcHCCA: HCCA Position
Definition at line 663 of file usbh_reg.h.
| #define USBH_HcInterruptDisable_FNO_Msk (0x1ul << USBH_HcInterruptDisable_FNO_Pos) |
USBH_T::HcInterruptDisable: FNO Mask
Definition at line 655 of file usbh_reg.h.
| #define USBH_HcInterruptDisable_FNO_Pos (5) |
USBH_T::HcInterruptDisable: FNO Position
Definition at line 654 of file usbh_reg.h.
| #define USBH_HcInterruptDisable_MIE_Msk (0x1ul << USBH_HcInterruptDisable_MIE_Pos) |
USBH_T::HcInterruptDisable: MIE Mask
Definition at line 661 of file usbh_reg.h.
| #define USBH_HcInterruptDisable_MIE_Pos (31) |
USBH_T::HcInterruptDisable: MIE Position
Definition at line 660 of file usbh_reg.h.
| #define USBH_HcInterruptDisable_RD_Msk (0x1ul << USBH_HcInterruptDisable_RD_Pos) |
USBH_T::HcInterruptDisable: RD Mask
Definition at line 652 of file usbh_reg.h.
| #define USBH_HcInterruptDisable_RD_Pos (3) |
USBH_T::HcInterruptDisable: RD Position
Definition at line 651 of file usbh_reg.h.
| #define USBH_HcInterruptDisable_RHSC_Msk (0x1ul << USBH_HcInterruptDisable_RHSC_Pos) |
USBH_T::HcInterruptDisable: RHSC Mask
Definition at line 658 of file usbh_reg.h.
| #define USBH_HcInterruptDisable_RHSC_Pos (6) |
USBH_T::HcInterruptDisable: RHSC Position
Definition at line 657 of file usbh_reg.h.
| #define USBH_HcInterruptDisable_SF_Msk (0x1ul << USBH_HcInterruptDisable_SF_Pos) |
USBH_T::HcInterruptDisable: SF Mask
Definition at line 649 of file usbh_reg.h.
| #define USBH_HcInterruptDisable_SF_Pos (2) |
USBH_T::HcInterruptDisable: SF Position
Definition at line 648 of file usbh_reg.h.
| #define USBH_HcInterruptDisable_SO_Msk (0x1ul << USBH_HcInterruptDisable_SO_Pos) |
USBH_T::HcInterruptDisable: SO Mask
Definition at line 643 of file usbh_reg.h.
| #define USBH_HcInterruptDisable_SO_Pos (0) |
USBH_T::HcInterruptDisable: SO Position
Definition at line 642 of file usbh_reg.h.
| #define USBH_HcInterruptDisable_WDH_Msk (0x1ul << USBH_HcInterruptDisable_WDH_Pos) |
USBH_T::HcInterruptDisable: WDH Mask
Definition at line 646 of file usbh_reg.h.
| #define USBH_HcInterruptDisable_WDH_Pos (1) |
USBH_T::HcInterruptDisable: WDH Position
Definition at line 645 of file usbh_reg.h.
| #define USBH_HcInterruptEnable_FNO_Msk (0x1ul << USBH_HcInterruptEnable_FNO_Pos) |
USBH_T::HcInterruptEnable: FNO Mask
Definition at line 634 of file usbh_reg.h.
| #define USBH_HcInterruptEnable_FNO_Pos (5) |
USBH_T::HcInterruptEnable: FNO Position
Definition at line 633 of file usbh_reg.h.
| #define USBH_HcInterruptEnable_MIE_Msk (0x1ul << USBH_HcInterruptEnable_MIE_Pos) |
USBH_T::HcInterruptEnable: MIE Mask
Definition at line 640 of file usbh_reg.h.
| #define USBH_HcInterruptEnable_MIE_Pos (31) |
USBH_T::HcInterruptEnable: MIE Position
Definition at line 639 of file usbh_reg.h.
| #define USBH_HcInterruptEnable_RD_Msk (0x1ul << USBH_HcInterruptEnable_RD_Pos) |
USBH_T::HcInterruptEnable: RD Mask
Definition at line 631 of file usbh_reg.h.
| #define USBH_HcInterruptEnable_RD_Pos (3) |
USBH_T::HcInterruptEnable: RD Position
Definition at line 630 of file usbh_reg.h.
| #define USBH_HcInterruptEnable_RHSC_Msk (0x1ul << USBH_HcInterruptEnable_RHSC_Pos) |
USBH_T::HcInterruptEnable: RHSC Mask
Definition at line 637 of file usbh_reg.h.
| #define USBH_HcInterruptEnable_RHSC_Pos (6) |
USBH_T::HcInterruptEnable: RHSC Position
Definition at line 636 of file usbh_reg.h.
| #define USBH_HcInterruptEnable_SF_Msk (0x1ul << USBH_HcInterruptEnable_SF_Pos) |
USBH_T::HcInterruptEnable: SF Mask
Definition at line 628 of file usbh_reg.h.
| #define USBH_HcInterruptEnable_SF_Pos (2) |
USBH_T::HcInterruptEnable: SF Position
Definition at line 627 of file usbh_reg.h.
| #define USBH_HcInterruptEnable_SO_Msk (0x1ul << USBH_HcInterruptEnable_SO_Pos) |
USBH_T::HcInterruptEnable: SO Mask
Definition at line 622 of file usbh_reg.h.
| #define USBH_HcInterruptEnable_SO_Pos (0) |
USBH_T::HcInterruptEnable: SO Position
Definition at line 621 of file usbh_reg.h.
| #define USBH_HcInterruptEnable_WDH_Msk (0x1ul << USBH_HcInterruptEnable_WDH_Pos) |
USBH_T::HcInterruptEnable: WDH Mask
Definition at line 625 of file usbh_reg.h.
| #define USBH_HcInterruptEnable_WDH_Pos (1) |
USBH_T::HcInterruptEnable: WDH Position
Definition at line 624 of file usbh_reg.h.
| #define USBH_HcInterruptStatus_FNO_Msk (0x1ul << USBH_HcInterruptStatus_FNO_Pos) |
USBH_T::HcInterruptStatus: FNO Mask
Definition at line 616 of file usbh_reg.h.
| #define USBH_HcInterruptStatus_FNO_Pos (5) |
USBH_T::HcInterruptStatus: FNO Position
Definition at line 615 of file usbh_reg.h.
| #define USBH_HcInterruptStatus_RD_Msk (0x1ul << USBH_HcInterruptStatus_RD_Pos) |
USBH_T::HcInterruptStatus: RD Mask
Definition at line 613 of file usbh_reg.h.
| #define USBH_HcInterruptStatus_RD_Pos (3) |
USBH_T::HcInterruptStatus: RD Position
Definition at line 612 of file usbh_reg.h.
| #define USBH_HcInterruptStatus_RHSC_Msk (0x1ul << USBH_HcInterruptStatus_RHSC_Pos) |
USBH_T::HcInterruptStatus: RHSC Mask
Definition at line 619 of file usbh_reg.h.
| #define USBH_HcInterruptStatus_RHSC_Pos (6) |
USBH_T::HcInterruptStatus: RHSC Position
Definition at line 618 of file usbh_reg.h.
| #define USBH_HcInterruptStatus_SF_Msk (0x1ul << USBH_HcInterruptStatus_SF_Pos) |
USBH_T::HcInterruptStatus: SF Mask
Definition at line 610 of file usbh_reg.h.
| #define USBH_HcInterruptStatus_SF_Pos (2) |
USBH_T::HcInterruptStatus: SF Position
Definition at line 609 of file usbh_reg.h.
| #define USBH_HcInterruptStatus_SO_Msk (0x1ul << USBH_HcInterruptStatus_SO_Pos) |
USBH_T::HcInterruptStatus: SO Mask
Definition at line 604 of file usbh_reg.h.
| #define USBH_HcInterruptStatus_SO_Pos (0) |
USBH_T::HcInterruptStatus: SO Position
Definition at line 603 of file usbh_reg.h.
| #define USBH_HcInterruptStatus_WDH_Msk (0x1ul << USBH_HcInterruptStatus_WDH_Pos) |
USBH_T::HcInterruptStatus: WDH Mask
Definition at line 607 of file usbh_reg.h.
| #define USBH_HcInterruptStatus_WDH_Pos (1) |
USBH_T::HcInterruptStatus: WDH Position
Definition at line 606 of file usbh_reg.h.
| #define USBH_HcLSThreshold_LST_Msk (0xffful << USBH_HcLSThreshold_LST_Pos) |
USBH_T::HcLSThreshold: LST Mask
Definition at line 706 of file usbh_reg.h.
| #define USBH_HcLSThreshold_LST_Pos (0) |
USBH_T::HcLSThreshold: LST Position
Definition at line 705 of file usbh_reg.h.
| #define USBH_HcMiscControl_ABORT_Msk (0x1ul << USBH_HcMiscControl_ABORT_Pos) |
USBH_T::HcMiscControl: ABORT Mask
Definition at line 781 of file usbh_reg.h.
| #define USBH_HcMiscControl_ABORT_Pos (1) |
USBH_T::HcMiscControl: ABORT Position
Definition at line 780 of file usbh_reg.h.
| #define USBH_HcMiscControl_DPRT1_Msk (0x1ul << USBH_HcMiscControl_DPRT1_Pos) |
USBH_T::HcMiscControl: DPRT1 Mask
Definition at line 787 of file usbh_reg.h.
| #define USBH_HcMiscControl_DPRT1_Pos (16) |
USBH_T::HcMiscControl: DPRT1 Position
Definition at line 786 of file usbh_reg.h.
| #define USBH_HcMiscControl_OCAL_Msk (0x1ul << USBH_HcMiscControl_OCAL_Pos) |
USBH_T::HcMiscControl: OCAL Mask
Definition at line 784 of file usbh_reg.h.
| #define USBH_HcMiscControl_OCAL_Pos (3) |
USBH_T::HcMiscControl: OCAL Position
Definition at line 783 of file usbh_reg.h.
| #define USBH_HcPeriodCurrentED_PCED_Msk (0xffffffful << USBH_HcPeriodCurrentED_PCED_Pos) |
USBH_T::HcPeriodCurrentED: PCED Mask
Definition at line 667 of file usbh_reg.h.
| #define USBH_HcPeriodCurrentED_PCED_Pos (4) |
USBH_T::HcPeriodCurrentED: PCED Position
Definition at line 666 of file usbh_reg.h.
| #define USBH_HcPeriodicStart_PS_Msk (0x3ffful << USBH_HcPeriodicStart_PS_Pos) |
USBH_T::HcPeriodicStart: PS Mask
Definition at line 703 of file usbh_reg.h.
| #define USBH_HcPeriodicStart_PS_Pos (0) |
USBH_T::HcPeriodicStart: PS Position
Definition at line 702 of file usbh_reg.h.
| #define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) |
USBH_T::HcPhyControl: STBYEN Mask
Definition at line 778 of file usbh_reg.h.
| #define USBH_HcPhyControl_STBYEN_Pos (27) |
USBH_T::HcPhyControl: STBYEN Position
Definition at line 777 of file usbh_reg.h.
| #define USBH_HcRevision_REV_Msk (0xfful << USBH_HcRevision_REV_Pos) |
USBH_T::HcRevision: REV Mask
Definition at line 571 of file usbh_reg.h.
| #define USBH_HcRevision_REV_Pos (0) |
@addtogroup USBH_CONST USBH Bit Field Definition Constant Definitions for USBH Controller
USBH_T::HcRevision: REV Position
Definition at line 570 of file usbh_reg.h.
| #define USBH_HcRhDescriptorA_NDP_Msk (0xfful << USBH_HcRhDescriptorA_NDP_Pos) |
USBH_T::HcRhDescriptorA: NDP Mask
Definition at line 709 of file usbh_reg.h.
| #define USBH_HcRhDescriptorA_NDP_Pos (0) |
USBH_T::HcRhDescriptorA: NDP Position
Definition at line 708 of file usbh_reg.h.
| #define USBH_HcRhDescriptorA_NOCP_Msk (0x1ul << USBH_HcRhDescriptorA_NOCP_Pos) |
USBH_T::HcRhDescriptorA: NOCP Mask
Definition at line 718 of file usbh_reg.h.
| #define USBH_HcRhDescriptorA_NOCP_Pos (12) |
USBH_T::HcRhDescriptorA: NOCP Position
Definition at line 717 of file usbh_reg.h.
| #define USBH_HcRhDescriptorA_OCPM_Msk (0x1ul << USBH_HcRhDescriptorA_OCPM_Pos) |
USBH_T::HcRhDescriptorA: OCPM Mask
Definition at line 715 of file usbh_reg.h.
| #define USBH_HcRhDescriptorA_OCPM_Pos (11) |
USBH_T::HcRhDescriptorA: OCPM Position
Definition at line 714 of file usbh_reg.h.
| #define USBH_HcRhDescriptorA_PSM_Msk (0x1ul << USBH_HcRhDescriptorA_PSM_Pos) |
USBH_T::HcRhDescriptorA: PSM Mask
Definition at line 712 of file usbh_reg.h.
| #define USBH_HcRhDescriptorA_PSM_Pos (8) |
USBH_T::HcRhDescriptorA: PSM Position
Definition at line 711 of file usbh_reg.h.
| #define USBH_HcRhDescriptorB_PPCM_Msk (0xfffful << USBH_HcRhDescriptorB_PPCM_Pos) |
USBH_T::HcRhDescriptorB: PPCM Mask
Definition at line 721 of file usbh_reg.h.
| #define USBH_HcRhDescriptorB_PPCM_Pos (16) |
USBH_T::HcRhDescriptorB: PPCM Position
Definition at line 720 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) |
USBH_T::HcRhPortStatus1: CCS Mask
Definition at line 742 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_CCS_Pos (0) |
USBH_T::HcRhPortStatus1: CCS Position
Definition at line 741 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) |
USBH_T::HcRhPortStatus1: CSC Mask
Definition at line 763 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_CSC_Pos (16) |
USBH_T::HcRhPortStatus1: CSC Position
Definition at line 762 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) |
USBH_T::HcRhPortStatus1: LSDA Mask
Definition at line 760 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_LSDA_Pos (9) |
USBH_T::HcRhPortStatus1: LSDA Position
Definition at line 759 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) |
USBH_T::HcRhPortStatus1: OCIC Mask
Definition at line 772 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_OCIC_Pos (19) |
USBH_T::HcRhPortStatus1: OCIC Position
Definition at line 771 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) |
USBH_T::HcRhPortStatus1: PES Mask
Definition at line 745 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_PES_Pos (1) |
USBH_T::HcRhPortStatus1: PES Position
Definition at line 744 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) |
USBH_T::HcRhPortStatus1: PESC Mask
Definition at line 766 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_PESC_Pos (17) |
USBH_T::HcRhPortStatus1: PESC Position
Definition at line 765 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) |
USBH_T::HcRhPortStatus1: POCI Mask
Definition at line 751 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_POCI_Pos (3) |
USBH_T::HcRhPortStatus1: POCI Position
Definition at line 750 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) |
USBH_T::HcRhPortStatus1: PPS Mask
Definition at line 757 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_PPS_Pos (8) |
USBH_T::HcRhPortStatus1: PPS Position
Definition at line 756 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) |
USBH_T::HcRhPortStatus1: PRS Mask
Definition at line 754 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_PRS_Pos (4) |
USBH_T::HcRhPortStatus1: PRS Position
Definition at line 753 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) |
USBH_T::HcRhPortStatus1: PRSC Mask
Definition at line 775 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_PRSC_Pos (20) |
USBH_T::HcRhPortStatus1: PRSC Position
Definition at line 774 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) |
USBH_T::HcRhPortStatus1: PSS Mask
Definition at line 748 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_PSS_Pos (2) |
USBH_T::HcRhPortStatus1: PSS Position
Definition at line 747 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) |
USBH_T::HcRhPortStatus1: PSSC Mask
Definition at line 769 of file usbh_reg.h.
| #define USBH_HcRhPortStatus_PSSC_Pos (18) |
USBH_T::HcRhPortStatus1: PSSC Position
Definition at line 768 of file usbh_reg.h.
| #define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) |
USBH_T::HcRhStatus: CRWE Mask
Definition at line 739 of file usbh_reg.h.
| #define USBH_HcRhStatus_CRWE_Pos (31) |
USBH_T::HcRhStatus: CRWE Position
Definition at line 738 of file usbh_reg.h.
| #define USBH_HcRhStatus_DRWE_Msk (0x1ul << USBH_HcRhStatus_DRWE_Pos) |
USBH_T::HcRhStatus: DRWE Mask
Definition at line 730 of file usbh_reg.h.
| #define USBH_HcRhStatus_DRWE_Pos (15) |
USBH_T::HcRhStatus: DRWE Position
Definition at line 729 of file usbh_reg.h.
| #define USBH_HcRhStatus_LPS_Msk (0x1ul << USBH_HcRhStatus_LPS_Pos) |
USBH_T::HcRhStatus: LPS Mask
Definition at line 724 of file usbh_reg.h.
| #define USBH_HcRhStatus_LPS_Pos (0) |
USBH_T::HcRhStatus: LPS Position
Definition at line 723 of file usbh_reg.h.
| #define USBH_HcRhStatus_LPSC_Msk (0x1ul << USBH_HcRhStatus_LPSC_Pos) |
USBH_T::HcRhStatus: LPSC Mask
Definition at line 733 of file usbh_reg.h.
| #define USBH_HcRhStatus_LPSC_Pos (16) |
USBH_T::HcRhStatus: LPSC Position
Definition at line 732 of file usbh_reg.h.
| #define USBH_HcRhStatus_OCI_Msk (0x1ul << USBH_HcRhStatus_OCI_Pos) |
USBH_T::HcRhStatus: OCI Mask
Definition at line 727 of file usbh_reg.h.
| #define USBH_HcRhStatus_OCI_Pos (1) |
USBH_T::HcRhStatus: OCI Position
Definition at line 726 of file usbh_reg.h.
| #define USBH_HcRhStatus_OCIC_Msk (0x1ul << USBH_HcRhStatus_OCIC_Pos) |
USBH_T::HcRhStatus: OCIC Mask
Definition at line 736 of file usbh_reg.h.
| #define USBH_HcRhStatus_OCIC_Pos (17) |
USBH_T::HcRhStatus: OCIC Position
Definition at line 735 of file usbh_reg.h.
| #define WDT_ALTCTL_RSTDSEL_Msk (0x3ul << WDT_ALTCTL_RSTDSEL_Pos) |
WDT_T::ALTCTL: RSTDSEL Mask
| #define WDT_ALTCTL_RSTDSEL_Pos (0) |
WDT_T::ALTCTL: RSTDSEL Position
| #define WDT_CTL_ICEDEBUG_Msk (0x1ul << WDT_CTL_ICEDEBUG_Pos) |
WDT_T::CTL: ICEDEBUG Mask
| #define WDT_CTL_ICEDEBUG_Pos (31) |
WDT_T::CTL: ICEDEBUG Position
| #define WDT_CTL_IF_Msk (0x1ul << WDT_CTL_IF_Pos) |
WDT_T::CTL: IF Mask
| #define WDT_CTL_IF_Pos (3) |
WDT_T::CTL: IF Position
| #define WDT_CTL_INTEN_Msk (0x1ul << WDT_CTL_INTEN_Pos) |
WDT_T::CTL: INTEN Mask
| #define WDT_CTL_INTEN_Pos (6) |
WDT_T::CTL: INTEN Position
| #define WDT_CTL_RSTCNT_Msk (0x1ul << WDT_CTL_RSTCNT_Pos) |
WDT_T::CTL: RSTCNT Mask
| #define WDT_CTL_RSTCNT_Pos (0) |
@addtogroup WDT_CONST WDT Bit Field Definition Constant Definitions for WDT Controller
WDT_T::CTL: RSTCNT Position
| #define WDT_CTL_RSTEN_Msk (0x1ul << WDT_CTL_RSTEN_Pos) |
WDT_T::CTL: RSTEN Mask
| #define WDT_CTL_RSTEN_Pos (1) |
WDT_T::CTL: RSTEN Position
| #define WDT_CTL_RSTF_Msk (0x1ul << WDT_CTL_RSTF_Pos) |
WDT_T::CTL: RSTF Mask
| #define WDT_CTL_RSTF_Pos (2) |
WDT_T::CTL: RSTF Position
| #define WDT_CTL_SYNC_Msk (0x1ul << WDT_CTL_SYNC_Pos) |
WDT_T::CTL: SYNC Mask
| #define WDT_CTL_SYNC_Pos (30) |
WDT_T::CTL: SYNC Position
| #define WDT_CTL_TOUTSEL_Msk (0x7ul << WDT_CTL_TOUTSEL_Pos) |
WDT_T::CTL: TOUTSEL Mask
| #define WDT_CTL_TOUTSEL_Pos (8) |
WDT_T::CTL: TOUTSEL Position
| #define WDT_CTL_WDTEN_Msk (0x1ul << WDT_CTL_WDTEN_Pos) |
WDT_T::CTL: WDTEN Mask
| #define WDT_CTL_WDTEN_Pos (7) |
WDT_T::CTL: WDTEN Position
| #define WDT_CTL_WKEN_Msk (0x1ul << WDT_CTL_WKEN_Pos) |
WDT_T::CTL: WKEN Mask
| #define WDT_CTL_WKEN_Pos (4) |
WDT_T::CTL: WKEN Position
| #define WDT_CTL_WKF_Msk (0x1ul << WDT_CTL_WKF_Pos) |
WDT_T::CTL: WKF Mask
| #define WDT_CTL_WKF_Pos (5) |
WDT_T::CTL: WKF Position
| #define WDT_RSTCNT_RSTCNT_Msk (0xfffffffful << WDT_RSTCNT_RSTCNT_Pos) |
WDT_T::RSTCNT: RSTCNT Mask
| #define WDT_RSTCNT_RSTCNT_Pos (0) |
WDT_T::RSTCNT: RSTCNT Position
| #define WWDT_CNT_CNTDAT_Msk (0x3ful << WWDT_CNT_CNTDAT_Pos) |
WWDT_T::CNT: CNTDAT Mask
Definition at line 139 of file wwdt_reg.h.
| #define WWDT_CNT_CNTDAT_Pos (0) |
WWDT_T::CNT: CNTDAT Position
Definition at line 138 of file wwdt_reg.h.
| #define WWDT_CTL_CMPDAT_Msk (0x3ful << WWDT_CTL_CMPDAT_Pos) |
WWDT_T::CTL: CMPDAT Mask
Definition at line 127 of file wwdt_reg.h.
| #define WWDT_CTL_CMPDAT_Pos (16) |
WWDT_T::CTL: CMPDAT Position
Definition at line 126 of file wwdt_reg.h.
| #define WWDT_CTL_ICEDEBUG_Msk (0x1ul << WWDT_CTL_ICEDEBUG_Pos) |
WWDT_T::CTL: ICEDEBUG Mask
Definition at line 130 of file wwdt_reg.h.
| #define WWDT_CTL_ICEDEBUG_Pos (31) |
WWDT_T::CTL: ICEDEBUG Position
Definition at line 129 of file wwdt_reg.h.
| #define WWDT_CTL_INTEN_Msk (0x1ul << WWDT_CTL_INTEN_Pos) |
WWDT_T::CTL: INTEN Mask
Definition at line 121 of file wwdt_reg.h.
| #define WWDT_CTL_INTEN_Pos (1) |
WWDT_T::CTL: INTEN Position
Definition at line 120 of file wwdt_reg.h.
| #define WWDT_CTL_PSCSEL_Msk (0xful << WWDT_CTL_PSCSEL_Pos) |
WWDT_T::CTL: PSCSEL Mask
Definition at line 124 of file wwdt_reg.h.
| #define WWDT_CTL_PSCSEL_Pos (8) |
WWDT_T::CTL: PSCSEL Position
Definition at line 123 of file wwdt_reg.h.
| #define WWDT_CTL_WWDTEN_Msk (0x1ul << WWDT_CTL_WWDTEN_Pos) |
WWDT_T::CTL: WWDTEN Mask
Definition at line 118 of file wwdt_reg.h.
| #define WWDT_CTL_WWDTEN_Pos (0) |
WWDT_T::CTL: WWDTEN Position
Definition at line 117 of file wwdt_reg.h.
| #define WWDT_RLDCNT_RLDCNT_Msk (0xfffffffful << WWDT_RLDCNT_RLDCNT_Pos) |
WWDT_T::RLDCNT: RLDCNT Mask
Definition at line 115 of file wwdt_reg.h.
| #define WWDT_RLDCNT_RLDCNT_Pos (0) |
@addtogroup WWDT_CONST WWDT Bit Field Definition Constant Definitions for WWDT Controller
WWDT_T::RLDCNT: RLDCNT Position
Definition at line 114 of file wwdt_reg.h.
| #define WWDT_STATUS_WWDTIF_Msk (0x1ul << WWDT_STATUS_WWDTIF_Pos) |
WWDT_T::STATUS: WWDTIF Mask
Definition at line 133 of file wwdt_reg.h.
| #define WWDT_STATUS_WWDTIF_Pos (0) |
WWDT_T::STATUS: WWDTIF Position
Definition at line 132 of file wwdt_reg.h.
| #define WWDT_STATUS_WWDTRF_Msk (0x1ul << WWDT_STATUS_WWDTRF_Pos) |
WWDT_T::STATUS: WWDTRF Mask
Definition at line 136 of file wwdt_reg.h.
| #define WWDT_STATUS_WWDTRF_Pos (1) |
WWDT_T::STATUS: WWDTRF Position
Definition at line 135 of file wwdt_reg.h.